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| author | Stephen Warren <swarren@nvidia.com> | 2014-03-21 12:29:01 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-04-17 08:41:06 -0700 |
| commit | d68c9429271d31aadb048b536f177cc2a9bd5c26 (patch) | |
| tree | 42e0b4a7ad3a67a70aa885b31b184a929e8e58d2 /arch/arm/cpu/arm720t | |
| parent | 1fa3a634137c9f40b207cff1079fe0dfbd9b3378 (diff) | |
| download | u-boot-imx-d68c9429271d31aadb048b536f177cc2a9bd5c26.zip u-boot-imx-d68c9429271d31aadb048b536f177cc2a9bd5c26.tar.gz u-boot-imx-d68c9429271d31aadb048b536f177cc2a9bd5c26.tar.bz2 | |
ARM: tegra: Tegra124 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra124_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
There are differences in the set of drive groups. I have validated this
against the TRM. There are differences order of pin definitions in
pinmux.c; these previously had significant mismatches with the correct
order:-( I adjusted a few entries in pinmux-config-venice2.h since the
set of legal functions for some pins was updated to match the TRM.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/arm720t')
| -rw-r--r-- | arch/arm/cpu/arm720t/tegra124/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c index 97f5928..6ff6aeb 100644 --- a/arch/arm/cpu/arm720t/tegra124/cpu.c +++ b/arch/arm/cpu/arm720t/tegra124/cpu.c @@ -26,8 +26,8 @@ static void enable_cpu_power_rail(void) debug("enable_cpu_power_rail entry\n"); /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ - pinmux_tristate_disable(PINGRP_PWR_I2C_SCL); - pinmux_tristate_disable(PINGRP_PWR_I2C_SDA); + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); pmic_enable_cpu_vdd(); |