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| author | Allen Martin <amartin@nvidia.com> | 2012-08-31 08:30:07 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:21 +0200 |
| commit | c7da6c6757aa17bb6130833b0e1e7e2a068ea2f6 (patch) | |
| tree | 575e70bcbc27cb8cc496ff5597967ce0975b57a4 /arch/arm/cpu/arm720t | |
| parent | aa2e279d2a0ec7fa904a91d3392b57b51ea6264b (diff) | |
| download | u-boot-imx-c7da6c6757aa17bb6130833b0e1e7e2a068ea2f6.zip u-boot-imx-c7da6c6757aa17bb6130833b0e1e7e2a068ea2f6.tar.gz u-boot-imx-c7da6c6757aa17bb6130833b0e1e7e2a068ea2f6.tar.bz2 | |
ARM: Fix arm720t SPL build
Take a few SPL fixes from armv7 and apply them to arm720t:
-Use dummy exception handlers for SPL build
-Initialize relocation register r9 to 0 for the case of no relocation
-ifdef out interrupt handler code
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/arm720t')
| -rw-r--r-- | arch/arm/cpu/arm720t/start.S | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 3b97e80..dc047b8 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -51,6 +51,15 @@ _start: b reset ldr pc, _irq ldr pc, _fiq +#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -58,6 +67,7 @@ _data_abort: .word data_abort _not_used: .word not_used _irq: .word irq _fiq: .word fiq +#endif /* CONFIG_SPL_BUILD */ .balignl 16,0xdeadbeef @@ -167,6 +177,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs @@ -427,6 +438,7 @@ lock_loop: mov pc, lr +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -589,6 +601,7 @@ fiq: bl do_fiq #endif +#endif /* CONFIG_SPL_BUILD */ #if defined(CONFIG_NETARM) .align 5 |