diff options
| author | Ye.Li <B37916@freescale.com> | 2015-08-25 15:07:15 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2015-08-25 15:56:16 +0800 |
| commit | e7d4767331f1a2cbef61b4e89beb73731f267499 (patch) | |
| tree | 68426b4587a6697a25bab2568757196516d1417c /arch/arm/cpu/Makefile | |
| parent | 3b548a3ddf03dcbb646912ef7bbdd3cdb2daf81a (diff) | |
| download | u-boot-imx-e7d4767331f1a2cbef61b4e89beb73731f267499.zip u-boot-imx-e7d4767331f1a2cbef61b4e89beb73731f267499.tar.gz u-boot-imx-e7d4767331f1a2cbef61b4e89beb73731f267499.tar.bz2 | |
MLK-11408-2 imx: mx7d: Isolate 26 IP resources to domain 0 for A core
In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time.
There are 26 peripherals impacted by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is set M4 to a different domain with A core.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only.
CM4 image will set the M4 to domain 1 only.
This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and
setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/cpu/Makefile')
0 files changed, 0 insertions, 0 deletions