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| author | Alexey Brodkin <Alexey.Brodkin@synopsys.com> | 2015-12-14 17:14:46 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2016-02-20 11:19:53 +0300 |
| commit | 379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1 (patch) | |
| tree | dee63afdf0dd287b0daef4b3552513babff0fea3 /arch/arc/include | |
| parent | 86a0df732853d1a11eb3eaa3cda688d9ef7b34e5 (diff) | |
| download | u-boot-imx-379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1.zip u-boot-imx-379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1.tar.gz u-boot-imx-379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1.tar.bz2 | |
arc: cache - accommodate different L1 cache line lengths
ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.
Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.
With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/include')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 432606a..d26d9fb 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -9,13 +9,13 @@ #include <config.h> -#ifdef CONFIG_ARC_CACHE_LINE_SHIFT -#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT) -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -/* Satisfy users of ARCH_DMA_MINALIGN */ -#define ARCH_DMA_MINALIGN 128 -#endif +/* + * As of today we may handle any L1 cache line length right in software. + * For that essentially cache line length is a variable not constant. + * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length + * that may exist in either L1 or L2 (AKA SLC) caches on ARC. + */ +#define ARCH_DMA_MINALIGN 128 #if defined(ARC_MMU_ABSENT) #define CONFIG_ARC_MMU_VER 0 |