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authorYe.Li <B37916@freescale.com>2014-06-10 17:58:05 +0800
committerYe.Li <B37916@freescale.com>2014-06-17 11:13:53 +0800
commitdd32db7e21d849e70958ef3584f7b2b0265f8289 (patch)
treec1f6c182927520ada7550bb432725cde7ae8cb23 /api
parentb18346b6b48dc23f1095208b4157164c001ad9e5 (diff)
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ENGR00315894-50 QuadSPI: Add Freescale QuadSPI driver
Enable the Quadspi read/write/erase functions. Add two configurations "CONFIG_QSPI_BASE" and "CONFIG_QSPI_MEMMAP_BASE" for QSPI registers base and AHB memory base. Use "bus" and "cs" parameters to denote 4 flash chip connected on one QuadSPI: SFA1: bus 0, cs 0 SFA2: bus 0, cs 1 SFB1: bus 1, cs 0 SFB2: bus 1, cs 1 Currently in uboot, the SPI flash framework does not have way to notify the flash size to the driver. It brings a problem for QSPI driver to set the memory map space of each chip. In this patch, we fix the mem map space of each chip to 64MB(total is 256MB). So for each flash device, driver support 64MB at most. In addition, because u-boot SPI flash framework only supports 24bits address mode, and uses EAR register to switch bank for flash larger than 16MB. The QuadSPI does not support this way when reading data from AHB address. Thus, only lower 16MB is supported. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Allen Xu <b45815@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
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