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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-05-20 00:39:21 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-05-20 00:48:41 -0500 |
| commit | 8f29084a4f020ddc2d15a0f374f08f80aa8b39a0 (patch) | |
| tree | 082264a204ce9ce513059d583f742411b4f10d41 /README | |
| parent | 7a82c208143bbc774ffcb4e53239410f867a0794 (diff) | |
| download | u-boot-imx-8f29084a4f020ddc2d15a0f374f08f80aa8b39a0.zip u-boot-imx-8f29084a4f020ddc2d15a0f374f08f80aa8b39a0.tar.gz u-boot-imx-8f29084a4f020ddc2d15a0f374f08f80aa8b39a0.tar.bz2 | |
powerpc/fsl_pci: Fix device tree fixups for newer platforms
We assumed that only a small set of compatiable strings would be needed
to find the PCIe device tree nodes to be fixed up. However on newer
platforms the simple rules no longer work. We need to allow specifying
the PCIe compatiable string for each individual SoC.
We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if
the default isn't sufficient.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -363,6 +363,11 @@ The following options need to be configured: system clock. On most PQ3 devices this is 8, on newer QorIQ devices it can be 16 or 32. The ratio varies from SoC to Soc. + CONFIG_SYS_FSL_PCIE_COMPAT + + Defines the string to utilize when trying to match PCIe device + tree nodes for the given platform. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO |