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| author | Aneesh V <aneesh@ti.com> | 2011-06-16 23:30:51 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-07-04 10:55:25 +0200 |
| commit | 93bc21930a1bfbc98e3121035207eafa427ee07f (patch) | |
| tree | a0149a349481b704aedfe31cfd6733ee17a692d6 /README | |
| parent | e05f00792b71184428fdb34a303644a1e457f000 (diff) | |
| download | u-boot-imx-93bc21930a1bfbc98e3121035207eafa427ee07f.zip u-boot-imx-93bc21930a1bfbc98e3121035207eafa427ee07f.tar.gz u-boot-imx-93bc21930a1bfbc98e3121035207eafa427ee07f.tar.bz2 | |
armv7: add PL310 support to u-boot
PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430
Add support for some of the key PL310 operations
- Invalidate all
- Invalidate range
- Flush(clean & invalidate) all
- Flush range
Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -465,6 +465,12 @@ The following options need to be configured: CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot +- Cache Configuration for ARM: + CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache + controller + CONFIG_SYS_PL310_BASE - Physical base address of PL310 + controller register space + - Serial Ports: CONFIG_PL010_SERIAL |