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| author | Aneesh Bansal <aneesh.bansal@freescale.com> | 2014-03-18 23:40:26 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:46 -0700 |
| commit | fb4a2409b46c98672557bb07dec8e873bef1e23c (patch) | |
| tree | 776fe2f1a2b4f98dc0ae9cc8186ccaeabda3f72d /README | |
| parent | bea3cbb07fb4c47c2a0324a22bb83c020769f151 (diff) | |
| download | u-boot-imx-fb4a2409b46c98672557bb07dec8e873bef1e23c.zip u-boot-imx-fb4a2409b46c98672557bb07dec8e873bef1e23c.tar.gz u-boot-imx-fb4a2409b46c98672557bb07dec8e873bef1e23c.tar.bz2 | |
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -427,6 +427,10 @@ The following options need to be configured: In this mode, a single differential clock is used to supply clocks to the sysclock, ddrclock and usbclock. + CONFIG_SYS_CPC_REINIT_F + This CONFIG is defined when the CPC is configured as SRAM at the + time of U-boot entry and is required to be re-initialized. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN |