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author | Tom Rini <trini@ti.com> | 2015-01-01 15:10:39 -0500 |
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committer | Tom Rini <trini@ti.com> | 2015-01-01 15:10:39 -0500 |
commit | a74a4a86a53726ba17de8ab863bec1cd60cf545e (patch) | |
tree | 2dcb09a706850fa6cb1377b00815be6b8f71f606 /README | |
parent | b7b3b8c6a0bfc87047cb18a7abfa06fb6e9d0331 (diff) | |
parent | cc0856cd149acc7069ae97ebe10b92090a65f575 (diff) | |
download | u-boot-imx-a74a4a86a53726ba17de8ab863bec1cd60cf545e.zip u-boot-imx-a74a4a86a53726ba17de8ab863bec1cd60cf545e.tar.gz u-boot-imx-a74a4a86a53726ba17de8ab863bec1cd60cf545e.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Diffstat (limited to 'README')
-rw-r--r-- | README | 19 |
1 files changed, 19 insertions, 0 deletions
@@ -4016,6 +4016,25 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC_START). +- CONFIG_SYS_NONCACHED_MEMORY: + Size of non-cached memory area. This area of memory will be + typically located right below the malloc() area and mapped + uncached in the MMU. This is useful for drivers that would + otherwise require a lot of explicit cache maintenance. For + some drivers it's also impossible to properly maintain the + cache. For example if the regions that need to be flushed + are not a multiple of the cache-line size, *and* padding + cannot be allocated between the regions to align them (i.e. + if the HW requires a contiguous array of regions, and the + size of each region is not cache-aligned), then a flush of + one region may result in overwriting data that hardware has + written to another region in the same cache-line. This can + happen for example in network drivers where descriptors for + buffers are typically smaller than the CPU cache-line (e.g. + 16 bytes vs. 32 or 64 bytes). + + Non-cached memory is only supported on 32-bit ARM at present. + - CONFIG_SYS_BOOTM_LEN: Normally compressed uImages are limited to an uncompressed size of 8 MBytes. If this is not enough, |