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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2014-04-08 19:13:34 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:51 -0700 |
| commit | 89ad7be8e713f33ec677cf4576e0c9b0ed83f7c6 (patch) | |
| tree | 4cc2d7b402e94354e4928d4da9dedc8dbceb53e0 /README | |
| parent | 1eaa742d85a59ed3602a78445adf903f26d9b594 (diff) | |
| download | u-boot-imx-89ad7be8e713f33ec677cf4576e0c9b0ed83f7c6.zip u-boot-imx-89ad7be8e713f33ec677cf4576e0c9b0ed83f7c6.tar.gz u-boot-imx-89ad7be8e713f33ec677cf4576e0c9b0ed83f7c6.tar.bz2 | |
Makefile: Add support of CONFIG_SPL_FSL_PBL
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binary
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -505,6 +505,10 @@ The following options need to be configured: PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details + CONFIG_SPL_FSL_PBL + It adds a target to create boot binary having SPL binary in PBI format + concatenated with u-boot binary. + CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian |