diff options
| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2014-01-18 12:28:30 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-02-03 08:38:51 -0800 |
| commit | 1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba (patch) | |
| tree | d5aa577b493fc7e44de173445bcda11f29721f38 /README | |
| parent | 27c78e06f2b42bd6285ed104ece23f6c69e42e6f (diff) | |
| download | u-boot-imx-1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba.zip u-boot-imx-1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba.tar.gz u-boot-imx-1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba.tar.bz2 | |
driver/ifc:Change accessor function to take care of endianness
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.
So update acessor functions with common IFC acessor functions to take care
both type of endianness.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -472,6 +472,12 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details |