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authorPriyanka Jain <Priyanka.Jain@freescale.com>2013-12-17 14:25:52 +0530
committerYork Sun <yorksun@freescale.com>2014-01-02 14:10:13 -0800
commitb135991a3cddd1a266c5fbd64e25eaaa61bde2d8 (patch)
tree8969fd749e188219c441fa104bd6240e9f3e6b81 /README
parent562de1d6da5bdc1789bd258d464d6ca57571861d (diff)
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powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Diffstat (limited to 'README')
-rw-r--r--README5
1 files changed, 5 insertions, 0 deletions
diff --git a/README b/README
index e58e9c0..a0646c3 100644
--- a/README
+++ b/README
@@ -423,6 +423,11 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
+ CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ Single Source Clock is clocking mode present in some of FSL SoC's.
+ In this mode, a single differential clock is used to supply
+ clocks to the sysclock, ddrclock and usbclock.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN