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authorScott Wood <scottwood@freescale.com>2012-08-14 10:14:53 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 12:16:54 -0500
commit33eee330cc8a445ff05f39a58af3c87324798230 (patch)
tree183b1fd72ce4cdd395aa009ea739602a992df56c /README
parent3e978f5dc85db40432f73380aa5be53096205f18 (diff)
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powerpc/fsl-corenet: work around erratum A004510
Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'README')
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diff --git a/README b/README
index 81ee7d4..8197235 100644
--- a/README
+++ b/README
@@ -383,6 +383,31 @@ The following options need to be configured:
symbol should be set to the TLB1 entry to be used for this
purpose.
+ CONFIG_SYS_FSL_ERRATUM_A004510
+
+ Enables a workaround for erratum A004510. If set,
+ then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
+ CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+
+ CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
+ CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
+
+ Defines one or two SoC revisions (low 8 bits of SVR)
+ for which the A004510 workaround should be applied.
+
+ The rest of SVR is either not relevant to the decision
+ of whether the erratum is present (e.g. p2040 versus
+ p2041) or is implied by the build target, which controls
+ whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
+
+ See Freescale App Note 4493 for more information about
+ this erratum.
+
+ CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+
+ This is the value to write into CCSR offset 0x18600
+ according to the A004510 workaround.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN