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authorTimur Tabi <timur@freescale.com>2006-10-31 18:44:42 -0600
committerKim Phillips <kim.phillips@freescale.com>2006-11-03 19:42:20 -0600
commit2ad6b513b31070bd0c003792ed1c3e7f5d740357 (patch)
treee4d9493e7f6cdc1086a90db4c64bbd265a1acaa6 /README
parent183da6d9b446cc12123455844ad1187e2375626f (diff)
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mpc83xx: Add support for the MPC8349E-mITX
PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'README')
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diff --git a/README b/README
index 6b94f84..5c907c8 100644
--- a/README
+++ b/README
@@ -2249,6 +2249,14 @@ Low Level (hardware related) configuration options:
If SPD EEPROM is on an I2C bus other than the first one, specify here.
Note that the value must resolve to something your driver can deal with.
+- CFG_83XX_DDR_USES_CS0
+ Only for 83xx systems. If specified, then DDR should be configured
+ using CS0 and CS1 instead of CS2 and CS3.
+
+- CFG_83XX_DDR_USES_CS0
+ Only for 83xx systems. If specified, then DDR should be configured
+ using CS0 and CS1 instead of CS2 and CS3.
+
- CONFIG_ETHER_ON_FEC[12]
Define to enable FEC[12] on a 8xx series processor.