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| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-02-02 15:01:26 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-02-03 14:31:11 -0800 |
| commit | 1c40707e3fd791457e07e5e31975a096483ca345 (patch) | |
| tree | ee6b59ab57b5e237d9f7741e62f1c2adaa193c49 /README | |
| parent | d98b98d62e7d4326f254eda87d2fc4c76807b1f1 (diff) | |
| download | u-boot-imx-1c40707e3fd791457e07e5e31975a096483ca345.zip u-boot-imx-1c40707e3fd791457e07e5e31975a096483ca345.tar.gz u-boot-imx-1c40707e3fd791457e07e5e31975a096483ca345.tar.bz2 | |
arch: powerpc: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.
Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -504,6 +504,9 @@ The following options need to be configured: CONFIG_SYS_FSL_IFC_LE Defines the IFC controller register space as Little Endian + CONFIG_SYS_FSL_IFC_CLK_DIV + Defines divider of platform clock(clock input to IFC controller). + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details |