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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:18:55 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:09:42 -0800 |
| commit | e32d59a2fa6446b64167bba31c0dd40eb023e8bb (patch) | |
| tree | d2d58e20f9d05aabb5d1d12a4a91ef4cbbb545bd /README | |
| parent | 064d031ca6490d9641bbe308690b1f15b1f56077 (diff) | |
| download | u-boot-imx-e32d59a2fa6446b64167bba31c0dd40eb023e8bb.zip u-boot-imx-e32d59a2fa6446b64167bba31c0dd40eb023e8bb.tar.gz u-boot-imx-e32d59a2fa6446b64167bba31c0dd40eb023e8bb.tar.bz2 | |
driver/ddr/fsl: Add sync of refresh
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -4916,6 +4916,9 @@ Low Level (hardware related) configuration options: - CONFIG_FSL_DDR_INTERACTIVE Enable interactive DDR debugging. See doc/README.fsl-ddr. +- CONFIG_FSL_DDR_SYNC_REFRESH + Enable sync of refresh for multiple controllers. + - CONFIG_SYS_83XX_DDR_USES_CS0 Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. |