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| author | Tom Rini <trini@ti.com> | 2014-02-04 10:22:23 -0500 |
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| committer | Tom Rini <trini@ti.com> | 2014-02-04 11:51:20 -0500 |
| commit | b66af14dc9d0bb3b962e09b2d000f228e2d5b039 (patch) | |
| tree | 74cc58551075570603e2ad02ad7eb1cec63d7181 /README | |
| parent | c61d94d86035ab2165aedf208b8f3c768b277a3d (diff) | |
| parent | 1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba (diff) | |
| download | u-boot-imx-b66af14dc9d0bb3b962e09b2d000f228e2d5b039.zip u-boot-imx-b66af14dc9d0bb3b962e09b2d000f228e2d5b039.tar.gz u-boot-imx-b66af14dc9d0bb3b962e09b2d000f228e2d5b039.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -472,6 +472,12 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details |