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| author | York Sun <yorksun@freescale.com> | 2014-02-10 13:59:43 -0800 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-21 11:06:13 -0500 |
| commit | 6b9e309a8a7f0f33252288f0ed8794a83a488301 (patch) | |
| tree | 24ace80dceeb3c6e184bc4eb39529de5379b57b2 /README | |
| parent | 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c (diff) | |
| download | u-boot-imx-6b9e309a8a7f0f33252288f0ed8794a83a488301.zip u-boot-imx-6b9e309a8a7f0f33252288f0ed8794a83a488301.tar.gz u-boot-imx-6b9e309a8a7f0f33252288f0ed8794a83a488301.tar.bz2 | |
Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -492,6 +492,11 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_LE Defines the DDR controller register space as Little Endian + CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + Physical address from the view of DDR controllers. It is the + same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + it could be different for ARM SoCs. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO |