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authorMarek Vasut <marex@denx.de>2015-07-09 03:52:12 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:06 +0200
commit292260ca21723ab78d23fa2cf6b574cf17778991 (patch)
treede81cb64cc73fbc523c4f06b07c039f58df17f1e /Licenses
parenta71df7aa4fa775199280bba19072bd232cc35cb1 (diff)
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arm: socfpga: reset: Repair bridge reset handling
The current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and in case it was (!), the code called hang(). This makes no sense at all. Repair it such that the code instead checks whether the FPGA is programmed, but without any polling involved, and only if it is programmed, it de-asserts the reset. Signed-off-by: Marek Vasut <marex@denx.de>
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