summaryrefslogtreecommitdiff
path: root/Kbuild
diff options
context:
space:
mode:
authorFabio Estevam <fabio.estevam@freescale.com>2014-08-25 13:34:17 -0300
committerStefano Babic <sbabic@denx.de>2014-09-09 15:06:12 +0200
commitf599288d55e5816c2cf468880e3120ed0b34080e (patch)
treeee6079ca03d2758a63e931ffec9464a7dd0f42af /Kbuild
parentdb5b7f566e513dc1b7f364102010558e5ae7e14f (diff)
downloadu-boot-imx-f599288d55e5816c2cf468880e3120ed0b34080e.zip
u-boot-imx-f599288d55e5816c2cf468880e3120ed0b34080e.tar.gz
u-boot-imx-f599288d55e5816c2cf468880e3120ed0b34080e.tar.bz2
net: fec_mxc: Poll FEC_TBD_READY after polling TDAR
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'Kbuild')
0 files changed, 0 insertions, 0 deletions