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authorMahesh Mahadevan <r9aadq@freescale.com>2011-10-20 06:48:04 -0500
committerMahesh Mahadevan <r9aadq@freescale.com>2011-10-25 05:46:22 -0500
commit35c0640af2c2eaea8684d090b61886ddcff2c4fd (patch)
tree0f9bf1a0c1586b4ccf0db90c5e7522e7bdceff47
parent12603b0bd079c70acd8bf029675b8819184cc240 (diff)
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ENGR00160399 Added support for the MX6Q Sabre-lite board
Includes support for uSDHC read, write, FEC, SPI-NOR etc. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
-rw-r--r--Makefile3
-rw-r--r--board/freescale/mx6q_sabreauto/mx6q_sabreauto.c53
-rw-r--r--board/freescale/mx6q_sabrelite/Makefile47
-rw-r--r--board/freescale/mx6q_sabrelite/config.mk7
-rw-r--r--board/freescale/mx6q_sabrelite/flash_header.S179
-rw-r--r--board/freescale/mx6q_sabrelite/lowlevel_init.S163
-rw-r--r--board/freescale/mx6q_sabrelite/mx6q_sabrelite.c623
-rw-r--r--board/freescale/mx6q_sabrelite/u-boot.lds74
-rw-r--r--drivers/net/mxc_fec.c65
-rw-r--r--include/asm-arm/arch-mx6/mx6_pins.h58
-rw-r--r--include/asm-arm/mach-types.h15
-rw-r--r--include/configs/mx6q_sabrelite.h275
12 files changed, 1480 insertions, 82 deletions
diff --git a/Makefile b/Makefile
index 114351e..f389257 100644
--- a/Makefile
+++ b/Makefile
@@ -3316,6 +3316,9 @@ mx6q_sabreauto_iram_config : unconfig
}
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_sabreauto freescale mx6
+mx6q_sabrelite_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_sabrelite freescale mx6
+
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
diff --git a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c
index c63ec4b..7d2b9b5 100644
--- a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c
+++ b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c
@@ -26,7 +26,7 @@
#include <asm/arch/mx6_pins.h>
#include <asm/arch/iomux-v3.h>
#include <asm/errno.h>
-
+#include <miiphy.h>
#if defined(CONFIG_VIDEO_MX5)
#include <linux/list.h>
#include <linux/fb.h>
@@ -77,7 +77,6 @@ unsigned short colormap[16777216];
static int di = 1;
-
extern int ipuv3_fb_init(struct fb_videomode *mode, int di,
int interface_pix_fmt,
ipu_di_clk_parent_t di_clk_parent,
@@ -253,8 +252,6 @@ int setup_sata(void)
}
#endif
-
-
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
@@ -357,7 +354,6 @@ int fec_get_mac_addr(unsigned char *mac)
#endif
#endif
-
#ifdef CONFIG_NET_MULTI
int board_eth_init(bd_t *bis)
{
@@ -394,6 +390,7 @@ iomux_v3_cfg_t mx6q_usdhc1_pads[] = {
MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
};
+
iomux_v3_cfg_t mx6q_usdhc2_pads[] = {
MX6Q_PAD_SD2_CLK__USDHC2_CLK,
MX6Q_PAD_SD2_CMD__USDHC2_CMD,
@@ -402,6 +399,7 @@ iomux_v3_cfg_t mx6q_usdhc2_pads[] = {
MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
};
+
iomux_v3_cfg_t mx6q_usdhc3_pads[] = {
MX6Q_PAD_SD3_CLK__USDHC3_CLK,
MX6Q_PAD_SD3_CMD__USDHC3_CMD,
@@ -414,6 +412,7 @@ iomux_v3_cfg_t mx6q_usdhc3_pads[] = {
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
};
+
iomux_v3_cfg_t mx6q_usdhc4_pads[] = {
MX6Q_PAD_SD4_CLK__USDHC4_CLK,
MX6Q_PAD_SD4_CMD__USDHC4_CMD,
@@ -608,7 +607,6 @@ int board_init(void)
setup_sata();
#endif
-
#ifdef CONFIG_VIDEO_MX5
#ifdef CONFIG_I2C_MXC
@@ -633,6 +631,49 @@ int board_late_init(void)
return 0;
}
+static int phy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *pdata)
+{
+ int ret = miiphy_read(devname, addr, reg, pdata);
+ if (ret)
+ printf("Error reading from %s PHY addr=%02x reg=%02x\n",
+ devname, addr, reg);
+ return ret;
+}
+
+static int phy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ int ret = miiphy_write(devname, addr, reg, value);
+ if (ret)
+ printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
+ addr, reg);
+ return ret;
+}
+
+int mx6_rgmii_rework(char *devname, int phy_addr)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(devname, phy_addr, 0xd, 0x7);
+ phy_write(devname, phy_addr, 0xe, 0x8016);
+ phy_write(devname, phy_addr, 0xd, 0x4007);
+ phy_read(devname, phy_addr, 0xe, &val);
+
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(devname, phy_addr, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(devname, phy_addr, 0x1d, 0x5);
+ phy_read(devname, phy_addr, 0x1e, &val);
+ val |= 0x0100;
+ phy_write(devname, phy_addr, 0x1e, val);
+
+ return 0;
+}
+
iomux_v3_cfg_t enet_pads[] = {
MX6Q_PAD_KEY_COL1__ENET_MDIO,
MX6Q_PAD_KEY_COL2__ENET_MDC,
diff --git a/board/freescale/mx6q_sabrelite/Makefile b/board/freescale/mx6q_sabrelite/Makefile
new file mode 100644
index 0000000..5b040d4
--- /dev/null
+++ b/board/freescale/mx6q_sabrelite/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := lowlevel_init.o flash_header.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx6q_sabrelite/config.mk b/board/freescale/mx6q_sabrelite/config.mk
new file mode 100644
index 0000000..a0ce2a1
--- /dev/null
+++ b/board/freescale/mx6q_sabrelite/config.mk
@@ -0,0 +1,7 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
+
+ifndef TEXT_BASE
+ TEXT_BASE = 0x27800000
+endif
diff --git a/board/freescale/mx6q_sabrelite/flash_header.S b/board/freescale/mx6q_sabrelite/flash_header.S
new file mode 100644
index 0000000..2407c26
--- /dev/null
+++ b/board/freescale/mx6q_sabrelite/flash_header.S
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx6.h>
+
+#ifdef CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) & 0x000000FF) << 24) | \
+ (((l) & 0x0000FF00) << 8) | \
+ (((l) & 0x00FF0000) >> 8) | \
+ (((l) & 0xFF000000) >> 24))
+
+#define MXC_DCD_ITEM(i, addr, val) \
+dcd_node_##i: \
+ .word CPU_2_BE_32(addr) ; \
+ .word CPU_2_BE_32(val) ; \
+
+.section ".text.flasheader", "x"
+ b _start
+ .org CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v: .word _start
+reserv1: .word 0x0
+dcd_ptr: .word dcd_hdr
+boot_data_ptr: .word boot_data
+self_ptr: .word ivt_header
+app_code_csf: .word 0x0
+reserv2: .word 0x0
+
+boot_data: .word TEXT_BASE
+image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin: .word 0x0
+
+dcd_hdr: .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd: .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */
+
+/* DCD */
+
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
+
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
+
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00020030)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00020030)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00020030)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00020030)
+
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00020030)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00020030)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00020030)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00020030)
+
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00020030)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00020030)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00020030)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00020030)
+
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00020030)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
+
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
+
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
+
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
+
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x034C0359)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03650348)
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x4436383B)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x39393341)
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x35373933)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x48254A36)
+
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
+
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00440044)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00440044)
+
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+/* enable AXI cache for VDOA/VPU/IPU */
+MXC_DCD_ITEM(91, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
+/* set IPU Qos=0x7 */
+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x00070007)
+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x00070007)
+
+#endif
diff --git a/board/freescale/mx6q_sabrelite/lowlevel_init.S b/board/freescale/mx6q_sabrelite/lowlevel_init.S
new file mode 100644
index 0000000..dc00593
--- /dev/null
+++ b/board/freescale/mx6q_sabrelite/lowlevel_init.S
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx6.h>
+
+/*
+ Disable L2Cache because ROM turn it on when uboot use plug-in.
+ If L2Cache is on default, there are cache coherence problem if kernel have
+ not config L2Cache.
+*/
+.macro init_l2cc
+ ldr r1, =0xa02000
+ ldr r0, =0x0
+ str r0, [r1, #0x100]
+.endm /* init_l2cc */
+
+/* invalidate the D-CACHE */
+.macro inv_dcache
+ mov r0,#0
+ mcr p15,2,r0,c0,c0,0 /* cache size selection register, select dcache */
+ mrc p15,1,r0,c0,c0,0 /* cache size ID register */
+ mov r0,r0,ASR #13
+ ldr r3,=0xfff
+ and r0,r0,r3
+ cmp r0,#0x7f
+ moveq r6,#0x1000
+ beq size_done
+ cmp r0,#0xff
+ moveq r6,#0x2000
+ movne r6,#0x4000
+
+size_done:
+ mov r2,#0
+ mov r3,#0x40000000
+ mov r4,#0x80000000
+ mov r5,#0xc0000000
+
+d_inv_loop:
+ mcr p15,0,r2,c7,c6,2 /* invalidate dcache by set / way */
+ mcr p15,0,r3,c7,c6,2 /* invalidate dcache by set / way */
+ mcr p15,0,r4,c7,c6,2 /* invalidate dcache by set / way */
+ mcr p15,0,r5,c7,c6,2 /* invalidate dcache by set / way */
+ add r2,r2,#0x20
+ add r3,r3,#0x20
+ add r4,r4,#0x20
+ add r5,r5,#0x20
+
+ cmp r2,r6
+ bne d_inv_loop
+.endm
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_ON_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+
+ ldr r0, =AIPS2_ON_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+.endm
+
+.macro init_clock
+
+/* PLL1, PLL2, and PLL3 are enabled by ROM */
+#ifdef CONFIG_PLL3
+ /* enable PLL3 for UART */
+ ldr r0, ANATOP_BASE_ADDR_W
+
+ /* power up PLL */
+ ldr r1, [r0, #ANATOP_USB1]
+ orr r1, r1, #0x1000
+ str r1, [r0, #ANATOP_USB1]
+
+ /* enable PLL */
+ ldr r1, [r0, #ANATOP_USB1]
+ orr r1, r1, #0x2000
+ str r1, [r0, #ANATOP_USB1]
+
+ /* wait PLL lock */
+100:
+ ldr r1, [r0, #ANATOP_USB1]
+ mov r1, r1, lsr #31
+ cmp r1, #0x1
+ bne 100b
+
+ /* clear bypass bit */
+ ldr r1, [r0, #ANATOP_USB1]
+ and r1, r1, #0xfffeffff
+ str r1, [r0, #ANATOP_USB1]
+#endif
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ ldr r0, CCM_BASE_ADDR_W
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+ str r1, [r0, #CLKCTL_CCGR7]
+
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+ inv_dcache
+
+ init_l2cc
+
+ init_aips
+
+ init_clock
+
+ mov pc, lr
+
+/* Board level setting value */
+ANATOP_BASE_ADDR_W: .word ANATOP_BASE_ADDR
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
diff --git a/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c b/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
new file mode 100644
index 0000000..39cd827
--- /dev/null
+++ b/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
@@ -0,0 +1,623 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx6.h>
+#include <asm/arch/mx6_pins.h>
+#include <asm/arch/iomux-v3.h>
+#include <asm/errno.h>
+#include <miiphy.h>
+#if CONFIG_I2C_MXC
+#include <i2c.h>
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMU
+#include <asm/mmu.h>
+#include <asm/arch/mmu.h>
+#endif
+
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#include <asm/imx_iim.h>
+#endif
+
+#ifdef CONFIG_CMD_CLOCK
+#include <asm/clock.h>
+#endif
+
+#ifdef CONFIG_IMX_ECSPI
+#include <imx_spi.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+static enum boot_device boot_dev;
+
+static void set_gpio_output_val(unsigned base, unsigned mask, unsigned val)
+{
+ unsigned reg = readl(base + GPIO_DR);
+ if (val & 1)
+ reg |= mask; /* set high */
+ else
+ reg &= ~mask; /* clear low */
+ writel(reg, base + GPIO_DR);
+
+ reg = readl(base + GPIO_GDIR);
+ reg |= mask; /* configure GPIO line as output */
+ writel(reg, base + GPIO_GDIR);
+}
+
+static inline void setup_boot_device(void)
+{
+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4;
+ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
+
+ switch (bt_mem_ctl) {
+ case 0x0:
+ if (bt_mem_type)
+ boot_dev = ONE_NAND_BOOT;
+ else
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case 0x2:
+ boot_dev = SATA_BOOT;
+ break;
+ case 0x3:
+ if (bt_mem_type)
+ boot_dev = SPI_NOR_BOOT;
+ else
+ boot_dev = I2C_BOOT;
+ break;
+ case 0x4:
+ case 0x5:
+ boot_dev = SD_BOOT;
+ break;
+ case 0x6:
+ case 0x7:
+ boot_dev = MMC_BOOT;
+ break;
+ case 0x8 ... 0xf:
+ boot_dev = NAND_BOOT;
+ break;
+ default:
+ boot_dev = UNKNOWN_BOOT;
+ break;
+ }
+}
+
+enum boot_device get_boot_device(void)
+{
+ return boot_dev;
+}
+
+u32 get_board_rev(void)
+{
+
+ system_rev = 0x63000;
+
+ return system_rev;
+}
+
+#ifdef CONFIG_ARCH_MMU
+void board_mmu_init(void)
+{
+ unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r" (ttb_base) /*: */);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r" (i) /*: */);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x000, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
+ X_ARM_MMU_SECTION(0x001, 0x001, 0x008, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* 8M */
+ X_ARM_MMU_SECTION(0x009, 0x009, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* 246M */
+ /* 2 GB memory starting at 0x10000000, only map 1.875 GB */
+ X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
+ ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW);
+ /* uncached alias of the same 1.875 GB memory */
+ X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW);
+
+ /* Enable MMU */
+ MMU_ON();
+}
+#endif
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+static void setup_uart(void)
+{
+ /* UART1 TXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT6__UART1_TXD);
+
+ /* UART1 RXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_SD3_DAT7__UART1_RXD);
+
+ /* UART2 TXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D26__UART2_TXD);
+
+ /* UART2 RXD */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D27__UART2_RXD);
+}
+
+#ifdef CONFIG_I2C_MXC
+static void setup_i2c(unsigned int module_base)
+{
+ unsigned int reg;
+
+ switch (module_base) {
+ case I2C1_BASE_ADDR:
+ /* i2c1 SDA */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT8__I2C1_SDA);
+
+ /* i2c1 SCL */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT9__I2C1_SCL);
+
+ /* Enable i2c clock */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+ reg |= 0xC0;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+ break;
+ case I2C2_BASE_ADDR:
+ /* i2c2 SDA */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA);
+
+ /* i2c2 SCL */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL);
+
+ /* Enable i2c clock */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+ reg |= 0x300;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+ break;
+ case I2C3_BASE_ADDR:
+ /* GPIO_5 for I2C3_SCL */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_5__I2C3_SCL);
+
+ /* GPIO_16 for I2C3_SDA */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_16__I2C3_SDA);
+
+ /* Enable i2c clock */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+ reg |= 0xC00;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+ break;
+ default:
+ printf("Invalid I2C base: 0x%x\n", module_base);
+ break;
+ }
+}
+
+#endif
+
+#ifdef CONFIG_IMX_ECSPI
+s32 spi_get_cfg(struct imx_spi_dev_t *dev)
+{
+ switch (dev->slave.cs) {
+ case 0:
+ /* PMIC */
+ dev->base = ECSPI1_BASE_ADDR;
+ dev->freq = 25000000;
+ dev->ss_pol = IMX_SPI_ACTIVE_HIGH;
+ dev->ss = 0;
+ dev->fifo_sz = 64 * 4;
+ dev->us_delay = 0;
+ break;
+ case 1:
+ /* SPI-NOR */
+ dev->base = ECSPI1_BASE_ADDR;
+ dev->freq = 25000000;
+ dev->ss_pol = IMX_SPI_ACTIVE_LOW;
+ dev->ss = 1;
+ dev->fifo_sz = 64 * 4;
+ dev->us_delay = 0;
+ break;
+ default:
+ printf("Invalid Bus ID!\n");
+ }
+
+ return 0;
+}
+
+void spi_io_init(struct imx_spi_dev_t *dev)
+{
+ switch (dev->base) {
+ case ECSPI1_BASE_ADDR:
+ /* SCLK */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D16__ECSPI1_SCLK);
+
+ /* MISO */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D17__ECSPI1_MISO);
+
+ /* MOSI */
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D18__ECSPI1_MOSI);
+
+ if (dev->ss == 1)
+ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D19__ECSPI1_SS1);
+ break;
+ case ECSPI2_BASE_ADDR:
+ case ECSPI3_BASE_ADDR:
+ /* ecspi2-3 fall through */
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
+#define HW_OCOTP_MACn(n) (0x00000620 + (n) * 0x10)
+
+#ifdef CONFIG_MXC_FEC
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+
+int fec_get_mac_addr(unsigned char *mac)
+{
+ u32 *ocotp_mac_base = (u32 *) (OCOTP_BASE_ADDR + HW_OCOTP_MACn(0));
+ int i;
+
+ for (i = 0; i < 6; ++i, ++ocotp_mac_base)
+ mac[6 - 1 - i] = readl(++ocotp_mac_base);
+ return 0;
+}
+
+#endif
+#endif
+
+#ifdef CONFIG_NET_MULTI
+int board_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+ return rc;
+}
+#endif
+
+#ifdef CONFIG_CMD_MMC
+
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR, 1, 1, 1},
+ {USDHC4_BASE_ADDR, 1, 1, 1},
+};
+
+#ifdef CONFIG_DYNAMIC_MMC_DEVNO
+int get_mmc_env_devno(void)
+{
+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+
+ /* BOOT_CFG2[3] and BOOT_CFG2[4] */
+ return (soc_sbmr & 0x00001800) >> 11;
+}
+#endif
+
+iomux_v3_cfg_t mx6q_usdhc1_pads[] = {
+ MX6Q_PAD_SD1_CLK__USDHC1_CLK,
+ MX6Q_PAD_SD1_CMD__USDHC1_CMD,
+ MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
+ MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
+ MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
+ MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
+};
+
+iomux_v3_cfg_t mx6q_usdhc2_pads[] = {
+ MX6Q_PAD_SD2_CLK__USDHC2_CLK,
+ MX6Q_PAD_SD2_CMD__USDHC2_CMD,
+ MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
+ MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
+ MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
+ MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+};
+
+iomux_v3_cfg_t mx6q_usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK,
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD,
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
+};
+
+iomux_v3_cfg_t mx6q_usdhc4_pads[] = {
+ MX6Q_PAD_SD4_CLK__USDHC4_CLK,
+ MX6Q_PAD_SD4_CMD__USDHC4_CMD,
+ MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
+ MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
+ MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
+ MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
+};
+
+int usdhc_gpio_init(bd_t *bis)
+{
+ s32 status = 0;
+ u32 index = 0;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc3_pads,
+ sizeof
+ (mx6q_usdhc3_pads) /
+ sizeof(mx6q_usdhc3_pads
+ [0]));
+ break;
+ case 1:
+ mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc4_pads,
+ sizeof
+ (mx6q_usdhc4_pads) /
+ sizeof(mx6q_usdhc4_pads
+ [0]));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ }
+
+ return status;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ if (!usdhc_gpio_init(bis))
+ return 0;
+ else
+ return -1;
+}
+
+/* For DDR mode operation, provide target delay parameter for each SD port.
+ * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
+ * is dependent on signal layout for that particular port. If the following
+ * CONFIG is not defined, then the default target delay value will be used.
+ */
+#ifdef CONFIG_GET_DDR_TARGET_DELAY
+u32 get_ddr_delay(struct fsl_esdhc *cfg)
+{
+ /* No delay required */
+ return 0;
+}
+#endif
+
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_MFG
+/* MFG firmware need reset usb to avoid host crash firstly */
+#define USBCMD 0x140
+ int val = readl(OTG_BASE_ADDR + USBCMD);
+ val &= ~0x1; /*RS bit */
+ writel(val, OTG_BASE_ADDR + USBCMD);
+#endif
+ mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
+ setup_boot_device();
+
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_MX6Q_SABRELITE;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ setup_uart();
+
+#ifdef CONFIG_I2C_MXC
+ setup_i2c(CONFIG_SYS_I2C_PORT);
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+iomux_v3_cfg_t enet_pads[] = {
+ MX6Q_PAD_ENET_MDIO__ENET_MDIO,
+ MX6Q_PAD_ENET_MDC__ENET_MDC,
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
+ MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ MX6Q_PAD_RGMII_RXC__GPIO_6_30,
+ /* pin 32 - 1 - (MODE0) all */
+ MX6Q_PAD_RGMII_RD0__GPIO_6_25,
+ /* pin 31 - 1 - (MODE1) all */
+ MX6Q_PAD_RGMII_RD1__GPIO_6_27,
+ /* pin 28 - 1 - (MODE2) all */
+ MX6Q_PAD_RGMII_RD2__GPIO_6_28,
+ /* pin 27 - 1 - (MODE3) all */
+ MX6Q_PAD_RGMII_RD3__GPIO_6_29,
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
+ MX6Q_PAD_GPIO_0__CCM_CLKO,
+ MX6Q_PAD_GPIO_3__CCM_CLKO2,
+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
+};
+
+iomux_v3_cfg_t enet_pads_final[] = {
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
+ MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+};
+
+static int phy_read(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short *pdata)
+{
+ int ret = miiphy_read(devname, addr, reg, pdata);
+ if (ret)
+ printf("Error reading from %s PHY addr=%02x reg=%02x\n",
+ devname, addr, reg);
+ return ret;
+}
+
+static int phy_write(char *devname, unsigned char addr, unsigned char reg,
+ unsigned short value)
+{
+ int ret = miiphy_write(devname, addr, reg, value);
+ if (ret)
+ printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
+ addr, reg);
+
+ return ret;
+}
+
+int mx6_rgmii_rework(char *devname, int phy_addr)
+{
+#if 0
+ /* To advertise only 10 Mbs */
+ phy_write(devname, phy_addr, 0x4, 0x61);
+ phy_write(devname, phy_addr, 0x9, 0x0c00);
+#endif
+
+ /* prefer master mode, 1000 Base-T capable */
+ phy_write(devname, phy_addr, 0x9, 0x0f00);
+
+ /* min rx data delay */
+ phy_write(devname, phy_addr, 0x0b, 0x8105);
+ phy_write(devname, phy_addr, 0x0c, 0x0000);
+
+ /* max rx/tx clock delay, min rx/tx control delay */
+ phy_write(devname, phy_addr, 0x0b, 0x8104);
+ phy_write(devname, phy_addr, 0x0c, 0xf0f0);
+ phy_write(devname, phy_addr, 0x0b, 0x104);
+ return 0;
+}
+
+void enet_board_init(void)
+{
+ iomux_v3_cfg_t enet_reset =
+ (MX6Q_PAD_EIM_D23__GPIO_3_23 &
+ ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x48);
+
+ /* phy reset: gpio3-23 */
+ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 0);
+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 30),
+ (CONFIG_FEC0_PHY_ADDR >> 2));
+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 25), 1);
+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 27), 1);
+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 28), 1);
+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 29), 1);
+ mxc_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+ mxc_iomux_v3_setup_pad(enet_reset);
+ set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 24), 1);
+
+ udelay(500);
+ set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 1);
+ mxc_iomux_v3_setup_multiple_pads(enet_pads_final,
+ ARRAY_SIZE(enet_pads_final));
+}
+
+int checkboard(void)
+{
+ printf("Board: MX6Q-SABRELITE:[ ");
+
+ switch (__REG(SRC_BASE_ADDR + 0x8)) {
+ case 0x0001:
+ printf("POR");
+ break;
+ case 0x0009:
+ printf("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ printf("WDOG");
+ break;
+ default:
+ printf("unknown");
+ }
+ printf("]\n");
+
+ printf("Boot Device: ");
+ switch (get_boot_device()) {
+ case WEIM_NOR_BOOT:
+ printf("NOR\n");
+ break;
+ case ONE_NAND_BOOT:
+ printf("ONE NAND\n");
+ break;
+ case PATA_BOOT:
+ printf("PATA\n");
+ break;
+ case SATA_BOOT:
+ printf("SATA\n");
+ break;
+ case I2C_BOOT:
+ printf("I2C\n");
+ break;
+ case SPI_NOR_BOOT:
+ printf("SPI NOR\n");
+ break;
+ case SD_BOOT:
+ printf("SD\n");
+ break;
+ case MMC_BOOT:
+ printf("MMC\n");
+ break;
+ case NAND_BOOT:
+ printf("NAND\n");
+ break;
+ case UNKNOWN_BOOT:
+ default:
+ printf("UNKNOWN\n");
+ break;
+ }
+ return 0;
+}
diff --git a/board/freescale/mx6q_sabrelite/u-boot.lds b/board/freescale/mx6q_sabrelite/u-boot.lds
new file mode 100644
index 0000000..fe40969
--- /dev/null
+++ b/board/freescale/mx6q_sabrelite/u-boot.lds
@@ -0,0 +1,74 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+ board/freescale/mx6q_sabrelite/flash_header.o (.text.flasheader)
+ cpu/arm_cortexa8/start.o
+ board/freescale/mx6q_sabrelite/libmx6q_sabrelite.a (.text)
+ lib_arm/libarm.a (.text)
+ net/libnet.a (.text)
+ drivers/mtd/libmtd.a (.text)
+ drivers/mmc/libmmc.a (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o(.text)
+
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ _end_of_copy = .; /* end_of ROM copy code here */
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/drivers/net/mxc_fec.c b/drivers/net/mxc_fec.c
index ec8178c..093b4e4 100644
--- a/drivers/net/mxc_fec.c
+++ b/drivers/net/mxc_fec.c
@@ -76,6 +76,9 @@
#define FEC_MII_WRITE(pa, ra, v) (FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_WR)|\
FEC_MII_PA(pa) | FEC_MII_RA(ra) | FEC_MII_SET_DATA(v))
+#if defined (CONFIG_MX6Q)
+extern int mx6_rgmii_rework(char *devname, int phy_addr);
+#endif
#ifdef CONFIG_MX6Q_SABREAUTO
#define PHY_MIPSCR_LINK_UP (0x1 << 10)
#define PHY_MIPSCR_SPEED_MASK (0x3 << 14)
@@ -296,6 +299,7 @@ static void setFecDuplexSpeed(volatile fec_t *fecp, unsigned char addr,
{
unsigned short val = 0;
int ret;
+ int cnt;
#ifdef CONFIG_MX28
/* Dummy read with delay to get phy start working */
@@ -358,6 +362,36 @@ static void setFecDuplexSpeed(volatile fec_t *fecp, unsigned char addr,
else
dup_spd |= (HALF << 16);
}
+#elif defined(CONFIG_PHY_MICREL_KSZ9021)
+ for (cnt = 0; cnt < 100; cnt++) {
+ val = 0;
+ ret = __fec_mii_read(fecp, addr, PHY_BMSR, &val);
+ if (val & PHY_BMSR_LS)
+ break;
+ udelay(100*1000);
+ }
+ if (ret) {
+ /* set default speed and duplex */
+ dup_spd = _100BASET | (FULL << 16);
+ } else {
+ unsigned short reg31 = 0;
+ ret = __fec_mii_read(fecp, addr, 0x1f, &reg31);
+ if (val & PHY_BMSR_LS) {
+ printf("FEC: Link is Up %x, %x\n", val, reg31);
+ } else {
+ printf("FEC: Link is down %x, %x\n", val, reg31);
+ }
+ if (reg31 & (1 << 6))
+ dup_spd = _1000BASET;
+ else if (reg31 & (1 << 5))
+ dup_spd = _100BASET;
+ else
+ dup_spd = _10BASET;
+ if (reg31 & (1 << 3))
+ dup_spd |= (FULL << 16);
+ else
+ dup_spd |= (HALF << 16);
+ }
#else
ret = __fec_mii_read(fecp, addr, PHY_BMSR, &val);
if (ret) {
@@ -782,31 +816,6 @@ void dbgFecRegs(struct eth_device *dev)
}
#endif
-#ifdef CONFIG_MX6Q_SABREAUTO
-static int mx6_rgmii_rework(fec_t *fecp, int addr)
-{
- unsigned short val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- __fec_mii_write(fecp, addr, 0xd, 0x7);
- __fec_mii_write(fecp, addr, 0xe, 0x8016);
- __fec_mii_write(fecp, addr, 0xd, 0x4007);
- __fec_mii_read(fecp, addr, 0xe, &val);
-
- val &= 0xffe3;
- val |= 0x18;
- __fec_mii_write(fecp, addr, 0xe, val);
-
- /* introduce tx clock delay */
- __fec_mii_write(fecp, addr, 0x1d, 0x5);
- __fec_mii_read(fecp, addr, 0x1e, &val);
- val |= 0x0100;
- __fec_mii_write(fecp, addr, 0x1e, val);
-
- return 0;
-}
-#endif
-
int fec_init(struct eth_device *dev, bd_t *bd)
{
struct fec_info_s *info = dev->priv;
@@ -817,13 +826,11 @@ int fec_init(struct eth_device *dev, bd_t *bd)
fec_reset(dev);
fec_localhw_setup((fec_t *)fecp);
-
#if defined (CONFIG_CMD_MII) || defined (CONFIG_MII) || \
defined (CONFIG_DISCOVER_PHY)
-
mxc_fec_mii_init(fecp);
-#ifdef CONFIG_MX6Q_SABREAUTO
- mx6_rgmii_rework((fec_t *)fecp, info->phy_addr);
+#if defined (CONFIG_MX6Q)
+ mx6_rgmii_rework(dev->name, info->phy_addr);
#endif
#ifdef CONFIG_DISCOVER_PHY
diff --git a/include/asm-arm/arch-mx6/mx6_pins.h b/include/asm-arm/arch-mx6/mx6_pins.h
index 539231b..9648aa9 100644
--- a/include/asm-arm/arch-mx6/mx6_pins.h
+++ b/include/asm-arm/arch-mx6/mx6_pins.h
@@ -36,9 +36,9 @@ typedef enum iomux_config {
IOMUX_CONFIG_ALT5,
IOMUX_CONFIG_ALT6,
IOMUX_CONFIG_ALT7,
- IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
- IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
- } iomux_pin_cfg_t;
+ IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
+ IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
#define NON_MUX_I 0x3FF
#define NON_PAD_I 0x7FF
@@ -47,6 +47,9 @@ typedef enum iomux_config {
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX6Q_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
#define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -3651,8 +3654,6 @@ typedef enum iomux_config {
#define _MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 \
IOMUX_PAD(0x0744, 0x035C, 7, 0x0000, 0, 0)
-
-
#define MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 (_MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 (_MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 (_MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -3679,7 +3680,6 @@ typedef enum iomux_config {
#define MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT (_MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 (_MX6Q_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
#define MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA (_MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC (_MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK (_MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -3687,7 +3687,6 @@ typedef enum iomux_config {
#define MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 (_MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_TEST_IN_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT (_MX6Q_PAD_RGMII_TXC__ANATOP_ANATOP_24M_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
-
#define MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY (_MX6Q_PAD_RGMII_TD0__MIPI_HSI_CTRL_TX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 (_MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD0__GPIO_6_20 (_MX6Q_PAD_RGMII_TD0__GPIO_6_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -3699,32 +3698,27 @@ typedef enum iomux_config {
#define MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 (_MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_TEST_IN_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP (_MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-
#define MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA (_MX6Q_PAD_RGMII_TD2__MIPI_HSI_CTRL_RX_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 (_MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD2__GPIO_6_22 (_MX6Q_PAD_RGMII_TD2__GPIO_6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 (_MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_TEST_IN_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP (_MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
-
#define MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE (_MX6Q_PAD_RGMII_TD3__MIPI_HSI_CTRL_RX_WAKE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 (_MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD3__GPIO_6_23 (_MX6Q_PAD_RGMII_TD3__GPIO_6_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 (_MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_TEST_IN_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
#define MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA (_MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL (_MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 (_MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 (_MX6Q_PAD_RGMII_RX_CTL__MIPI_CORE_DPHY_TEST_IN_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
#define MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY (_MX6Q_PAD_RGMII_RD0__MIPI_HSI_CTRL_RX_READY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 (_MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_RGMII_RD0__GPIO_6_25 (_MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 (_MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_TEST_IN_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
-
#define MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE (_MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL (_MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 (_MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -3771,7 +3765,7 @@ typedef enum iomux_config {
#define MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 (_MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 (_MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK (_MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 (_MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 (_MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA (_MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -3779,7 +3773,7 @@ typedef enum iomux_config {
#define MX6Q_PAD_EIM_D16__I2C2_SDA (_MX6Q_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 (_MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D17__ECSPI1_MISO (_MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 (_MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK (_MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT (_MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -3788,7 +3782,7 @@ typedef enum iomux_config {
#define MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 (_MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 (_MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI (_MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 (_MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 (_MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS (_MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -3797,7 +3791,7 @@ typedef enum iomux_config {
#define MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 (_MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 (_MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 (_MX6Q_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(MX6Q_ECSPI_PAD_CTRL))
#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 (_MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 (_MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_EIM_D19__UART1_CTS (_MX6Q_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX6Q_UART_PAD_CTRL))
@@ -4460,7 +4454,7 @@ typedef enum iomux_config {
#define MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 (_MX6Q_PAD_DISP0_DAT23__PL301_MX6QPER1_HADDR_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDIO__ENET_MDIO (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT (_MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -4530,7 +4524,7 @@ typedef enum iomux_config {
#define MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD (_MX6Q_PAD_ENET_TXD0__ANATOP_USBPHY2_TSTO_RX_FS_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_ENET_MDC__MLB_MLBDAT (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX6Q_PAD_ENET_MDC__ENET_MDC (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL))
#define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN (_MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_ENET_MDC__GPIO_1_31 (_MX6Q_PAD_ENET_MDC__GPIO_1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -5619,31 +5613,3 @@ typedef enum iomux_config {
#define MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 (_MX6Q_PAD_SD2_DAT3__ANATOP_ANATOP_TESTO_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#endif
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diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 4255c07..8d8e14c 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -3254,7 +3254,8 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_SWEDA_TMS2 3272
#define MACH_TYPE_MX53_LOCO 3273
#define MACH_TYPE_MX53_PCBA 3274
-#define MACH_TYPE_MX6Q_SABREAUTO 3529
+#define MACH_TYPE_MX6Q_SABREAUTO 3529
+#define MACH_TYPE_MX6Q_SABRELITE 3769
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -42160,6 +42161,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_mx6q_sabreauto() (0)
#endif
+#ifdef CONFIG_MACH_MX6Q_SABRELITE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX6Q_SABRELITE
+# endif
+# define machine_is_mx6q_sabrelite() (machine_arch_type == MACH_TYPE_MX6Q_SABRELITE)
+#else
+# define machine_is_mx6q_sabrelite() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/include/configs/mx6q_sabrelite.h b/include/configs/mx6q_sabrelite.h
new file mode 100644
index 0000000..dd7c442
--- /dev/null
+++ b/include/configs/mx6q_sabrelite.h
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX6Q SABRE Automotive Infotainment Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx6.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
+#define CONFIG_MXC
+#define CONFIG_MX6Q
+#define CONFIG_MX6Q_SABRELITE
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_MX6_CLK32 32768
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_ARCH_MMU /* disable MMU first */
+#define CONFIG_L2_OFF /* disable L2 cache first*/
+
+#define CONFIG_MX6_HCLK_FREQ 24000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#define BOARD_LATE_INIT
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_UART_BASE_ADDR UART2_BASE_ADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+#define CONFIG_NET_MULTI 1
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_I2C
+
+/* Enable below configure when supporting nand */
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_ENV
+
+#define CONFIG_CMD_CLOCK
+#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ
+
+#define CONFIG_CMD_SATA
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
+#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "nfsroot=/opt/eldk/arm\0" \
+ "bootargs_base=setenv bootargs console=ttymxc1,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \
+ "root=/dev/mmcblk0p1 rootwait\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; " \
+ "mmc dev 1; " \
+ "mmc read ${loadaddr} 0x800 0x1800; bootm\0" \
+ "bootcmd=run bootcmd_net\0" \
+
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "MX6Q SABRELITE U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR
+#define CONFIG_FEC0_PINMUX -1
+#define CONFIG_FEC0_MIIBASE -1
+#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#define CONFIG_MXC_FEC
+#define CONFIG_FEC0_PHY_ADDR 6
+#define CONFIG_ETH_PRIME
+#define CONFIG_RMII
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_IPADDR 192.168.1.103
+#define CONFIG_SERVERIP 192.168.1.101
+#define CONFIG_NETMASK 255.255.255.0
+
+/*
+ * I2C Configs
+ */
+#ifdef CONFIG_CMD_I2C
+ #define CONFIG_HARD_I2C 1
+ #define CONFIG_I2C_MXC 1
+ #define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR
+ #define CONFIG_SYS_I2C_SPEED 100000
+ #define CONFIG_SYS_I2C_SLAVE 0x1f
+#endif
+
+/*
+ * SPI Configs
+ */
+#ifdef CONFIG_CMD_SF
+ #define CONFIG_FSL_SF 1
+ #define CONFIG_SPI_FLASH_IMX_SST 1
+ #define CONFIG_SPI_FLASH_CS 1
+ #define CONFIG_IMX_ECSPI
+ #define IMX_CSPI_VER_2_3 1
+ #define MAX_SPI_BYTES (64 * 4)
+#endif
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+ #define CONFIG_MMC
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_IMX_MMC
+ #define CONFIG_SYS_FSL_USDHC_NUM 2
+ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+ #define CONFIG_SYS_MMC_ENV_DEV 2
+ #define CONFIG_DOS_PARTITION 1
+ #define CONFIG_CMD_FAT 1
+ #define CONFIG_CMD_EXT2 1
+
+ /* detect whether SD1, 2, 3, or 4 is boot device */
+ #define CONFIG_DYNAMIC_MMC_DEVNO
+
+ /* Setup target delay in DDR mode for each SD port */
+ #define CONFIG_GET_DDR_TARGET_DELAY
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+ #define CONFIG_DWC_AHSATA
+ #define CONFIG_SYS_SATA_MAX_DEVICE 1
+ #define CONFIG_DWC_AHSATA_PORT_ID 0
+ #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+ #define CONFIG_LBA48
+ #define CONFIG_LIBATA
+#endif
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
+#define iomem_valid_addr(addr, size) \
+ (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+/* #define CONFIG_FSL_ENV_IN_MMC */
+/* #define CONFIG_FSL_ENV_IN_SATA */
+#define CONFIG_FSL_ENV_IN_SF
+
+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+ #define CONFIG_ENV_IS_IN_NAND 1
+ #define CONFIG_ENV_OFFSET 0x100000
+#elif defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SATA)
+ #define CONFIG_ENV_IS_IN_SATA 1
+ #define CONFIG_SATA_ENV_DEV 0
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+#endif /* __CONFIG_H */