diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2009-11-13 09:09:10 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 13:49:08 -0600 |
| commit | 783852e467f32a3a5568b542379e9fec3d26a173 (patch) | |
| tree | 6c9803f254ebdf5c97d021c1c97e7e0112d80338 | |
| parent | 355f4f85e90ce2e6d91883012c2993be7970c8b1 (diff) | |
| download | u-boot-imx-783852e467f32a3a5568b542379e9fec3d26a173.zip u-boot-imx-783852e467f32a3a5568b542379e9fec3d26a173.tar.gz u-boot-imx-783852e467f32a3a5568b542379e9fec3d26a173.tar.bz2 | |
ppc/85xx: Remove CONFIG_SYS_DDR_TLB_START
Now that we dynamically determine TLB CAM entries to use we dont need
CONFIG_SYS_DDR_TLB_START anymore.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | include/configs/MPC8572DS.h | 1 | ||||
| -rw-r--r-- | include/configs/P1_P2_RDB.h | 2 | ||||
| -rw-r--r-- | include/configs/P2020DS.h | 1 |
3 files changed, 0 insertions, 4 deletions
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 41e4a6e..78b7369 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -98,7 +98,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ -#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index ddfe7aa..15bfeef 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -149,8 +149,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 #define CONFIG_SYS_DDR_SBE 0x00FF0000 -#define CONFIG_SYS_DDR_TLB_START 9 - /* * Memory map * diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index df9ab34..f4509bd 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -101,7 +101,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ -#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR3 1 #undef CONFIG_FSL_DDR_INTERACTIVE |