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| author | Joe D'Abbraccio <ljd015@freescale.com> | 2008-03-24 13:00:59 -0400 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2008-03-25 19:16:48 -0500 |
| commit | 507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07 (patch) | |
| tree | 387333d74f0a89108de998422da7c5efb4c5ea91 | |
| parent | a7ba32d480a86db5db8dcd8ca66b21b4cadda923 (diff) | |
| download | u-boot-imx-507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07.zip u-boot-imx-507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07.tar.gz u-boot-imx-507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07.tar.bz2 | |
Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.
Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
| -rw-r--r-- | include/configs/MPC8349ITX.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 0e50186..6b8b74d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -156,7 +156,7 @@ #define CFG_MEMTEST_END 0x2000 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #ifdef CONFIG_HARD_I2C #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |