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| author | Anton staaf <robotboy@chromium.org> | 2011-11-10 11:56:51 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2011-11-12 15:39:29 -0600 |
| commit | 9b3d1873c8c829debe8e8ab487783577285530d3 (patch) | |
| tree | 50dd51408f141b8f249e59bdb0c8eea933363dcf | |
| parent | 5a762e2509a2d4b2e86168a2ffbc425087ecd75c (diff) | |
| download | u-boot-imx-9b3d1873c8c829debe8e8ab487783577285530d3.zip u-boot-imx-9b3d1873c8c829debe8e8ab487783577285530d3.tar.gz u-boot-imx-9b3d1873c8c829debe8e8ab487783577285530d3.tar.bz2 | |
Tegra2: mmc: Add data transfer completion timeout
Currently when no expected completion condition occures in the
mmc_send_cmd while loop that is waiting for a data transfer to
complete the MMC driver just hangs.
This patch adds an arbitrary 2 second timeout. If nothing we
recognize occures within 2 seconds some diagnostic information
is printed and we fail out.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| -rw-r--r-- | drivers/mmc/tegra2_mmc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index 159cef1..bbd0ccd 100644 --- a/drivers/mmc/tegra2_mmc.c +++ b/drivers/mmc/tegra2_mmc.c @@ -260,6 +260,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } if (data) { + unsigned long start = get_timer(0); + while (1) { mask = readl(&host->reg->norintsts); @@ -284,6 +286,18 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, /* Transfer Complete */ debug("r/w is done\n"); break; + } else if (get_timer(start) > 2000UL) { + writel(mask, &host->reg->norintsts); + printf("%s: MMC Timeout\n" + " Interrupt status 0x%08x\n" + " Interrupt status enable 0x%08x\n" + " Interrupt signal enable 0x%08x\n" + " Present status 0x%08x\n", + __func__, mask, + readl(&host->reg->norintstsen), + readl(&host->reg->norintsigen), + readl(&host->reg->prnsts)); + return -1; } } writel(mask, &host->reg->norintsts); |