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authorMinkyu Kang <mk7.kang@samsung.com>2010-11-02 14:09:18 +0900
committerMinkyu Kang <mk7.kang@samsung.com>2010-11-02 14:09:18 +0900
commit37a3bda0c9c8a2ffbf7e2a9e121177a3385a0626 (patch)
tree93439a245bc837bec3ec9e812b775ebed730c2fa
parentd9abba8254c3e6b9a1d5c2e52c2d8088bbeb520f (diff)
parent66fca016057b1c6b697552cc7220ebada9d4f82d (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
-rw-r--r--MAINTAINERS18
-rwxr-xr-xMAKEALL7
-rw-r--r--Makefile36
-rw-r--r--arch/arm/config.mk12
-rw-r--r--arch/arm/cpu/arm1136/mx31/generic.c7
-rw-r--r--arch/arm/cpu/arm1136/start.S171
-rw-r--r--arch/arm/cpu/arm1136/u-boot.lds15
-rw-r--r--arch/arm/cpu/arm926ejs/at91/clock.c55
-rw-r--r--arch/arm/cpu/arm926ejs/at91/timer.c85
-rw-r--r--arch/arm/cpu/arm926ejs/start.S162
-rw-r--r--arch/arm/cpu/arm926ejs/u-boot.lds26
-rw-r--r--arch/arm/cpu/armv7/mx5/Makefile (renamed from arch/arm/cpu/armv7/mx51/Makefile)0
-rw-r--r--arch/arm/cpu/armv7/mx5/clock.c (renamed from arch/arm/cpu/armv7/mx51/clock.c)42
-rw-r--r--arch/arm/cpu/armv7/mx5/iomux.c (renamed from arch/arm/cpu/armv7/mx51/iomux.c)2
-rw-r--r--arch/arm/cpu/armv7/mx5/lowlevel_init.S (renamed from arch/arm/cpu/armv7/mx51/lowlevel_init.S)14
-rw-r--r--arch/arm/cpu/armv7/mx5/soc.c (renamed from arch/arm/cpu/armv7/mx51/soc.c)28
-rw-r--r--arch/arm/cpu/armv7/mx5/speed.c (renamed from arch/arm/cpu/armv7/mx51/speed.c)0
-rw-r--r--arch/arm/cpu/armv7/mx5/timer.c (renamed from arch/arm/cpu/armv7/mx51/timer.c)8
-rw-r--r--arch/arm/cpu/armv7/mx5/u-boot.lds (renamed from arch/arm/cpu/armv7/mx51/u-boot.lds)0
-rw-r--r--arch/arm/cpu/armv7/start.S131
-rw-r--r--arch/arm/cpu/armv7/u-boot.lds7
-rw-r--r--arch/arm/cpu/pxa/cpu.c255
-rw-r--r--arch/arm/cpu/pxa/i2c.c69
-rw-r--r--arch/arm/cpu/pxa/pxafb.c365
-rw-r--r--arch/arm/cpu/pxa/start.S344
-rw-r--r--arch/arm/cpu/pxa/timer.c7
-rw-r--r--arch/arm/cpu/pxa/usb.c61
-rw-r--r--arch/arm/include/asm/arch-at91/hardware.h1
-rw-r--r--arch/arm/include/asm/arch-mx31/mx31.h1
-rw-r--r--arch/arm/include/asm/arch-mx5/asm-offsets.h (renamed from arch/arm/include/asm/arch-mx51/asm-offsets.h)0
-rw-r--r--arch/arm/include/asm/arch-mx5/clock.h (renamed from arch/arm/include/asm/arch-mx51/clock.h)0
-rw-r--r--arch/arm/include/asm/arch-mx5/crm_regs.h (renamed from arch/arm/include/asm/arch-mx51/crm_regs.h)0
-rw-r--r--arch/arm/include/asm/arch-mx5/imx-regs.h (renamed from arch/arm/include/asm/arch-mx51/imx-regs.h)0
-rw-r--r--arch/arm/include/asm/arch-mx5/iomux.h (renamed from arch/arm/include/asm/arch-mx51/iomux.h)8
-rw-r--r--arch/arm/include/asm/arch-mx5/mx5x_pins.h (renamed from arch/arm/include/asm/arch-mx51/mx51_pins.h)6
-rw-r--r--arch/arm/include/asm/arch-mx5/sys_proto.h (renamed from arch/arm/include/asm/arch-mx51/sys_proto.h)0
-rw-r--r--arch/arm/include/asm/arch-pxa/hardware.h61
-rw-r--r--arch/arm/include/asm/arch-pxa/macro.h20
-rw-r--r--arch/arm/include/asm/arch-pxa/pxa-regs.h2688
-rw-r--r--arch/arm/include/asm/config.h3
-rw-r--r--arch/arm/include/asm/global_data.h14
-rw-r--r--arch/arm/include/asm/u-boot-arm.h14
-rw-r--r--arch/arm/lib/board.c8
-rw-r--r--arch/arm/lib/cache.c2
-rw-r--r--arch/avr32/lib/board.c1
-rw-r--r--arch/m68k/lib/board.c1
-rw-r--r--arch/mips/lib/board.c1
-rw-r--r--arch/powerpc/cpu/mpc85xx/config.mk4
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c219
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c22
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.c31
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.h1
-rw-r--r--arch/powerpc/cpu/mpc85xx/tlb.c16
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot.lds52
-rw-r--r--arch/powerpc/cpu/mpc86xx/config.mk7
-rw-r--r--arch/powerpc/cpu/mpc86xx/u-boot.lds (renamed from board/xes/xpedite5170/u-boot.lds)26
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c17
-rw-r--r--arch/powerpc/cpu/mpc8xxx/fdt.c24
-rw-r--r--arch/powerpc/cpu/mpc8xxx/pci_cfg.c5
-rw-r--r--arch/powerpc/cpu/ppc4xx/cpu_init.c8
-rw-r--r--arch/powerpc/cpu/ppc4xx/interrupts.c7
-rw-r--r--arch/powerpc/cpu/ppc4xx/traps.c11
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h6
-rw-r--r--arch/powerpc/include/asm/fsl_enet.h33
-rw-r--r--board/BuS/eb_cpux9k2/config.mk1
-rw-r--r--board/BuS/eb_cpux9k2/cpux9k2.c7
-rw-r--r--board/LaCie/edminiv2/config.mk3
-rw-r--r--board/amcc/sequoia/sequoia.c6
-rw-r--r--board/atmel/at91rm9200ek/Makefile5
-rw-r--r--board/atmel/at91rm9200ek/at91rm9200ek.c60
-rw-r--r--board/atmel/at91rm9200ek/config.mk3
-rw-r--r--board/atmel/at91rm9200ek/led.c58
-rw-r--r--board/atmel/at91rm9200ek/mux.c38
-rw-r--r--board/balloon3/Makefile (renamed from board/a4m072/config.mk)42
-rw-r--r--board/balloon3/balloon3.c238
-rw-r--r--board/colibri_pxa270/colibri_pxa270.c33
-rw-r--r--board/cradle/cradle.c5
-rw-r--r--board/cradle/lowlevel_init.S4
-rw-r--r--board/csb226/csb226.c13
-rw-r--r--board/delta/delta.c37
-rw-r--r--board/delta/nand.c110
-rw-r--r--board/eNET/u-boot.lds8
-rw-r--r--board/freescale/corenet_ds/Makefile3
-rw-r--r--board/freescale/corenet_ds/corenet_ds.c15
-rw-r--r--board/freescale/corenet_ds/ddr.c131
-rw-r--r--board/freescale/corenet_ds/p4080ds_ddr.c356
-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c15
-rw-r--r--board/freescale/mpc837xemds/mpc837xemds.c8
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c4
-rw-r--r--board/freescale/mpc8610hpcd/u-boot.lds132
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c97
-rw-r--r--board/freescale/mpc8641hpcn/u-boot.lds133
-rw-r--r--board/freescale/mx51evk/mx51evk.c2
-rw-r--r--board/innokom/innokom.c14
-rw-r--r--board/jornada/Makefile (renamed from board/nc650/Makefile)18
-rw-r--r--board/jornada/jornada.c (renamed from board/atmel/at91rm9200ek/misc.c)42
-rw-r--r--board/jornada/setup.S210
-rw-r--r--board/jornada/u-boot.lds58
-rw-r--r--board/karo/tx25/config.mk2
-rw-r--r--board/logicpd/imx27lite/config.mk4
-rw-r--r--board/logicpd/imx31_litekit/config.mk2
-rw-r--r--board/logicpd/imx31_litekit/imx31_litekit.c10
-rw-r--r--board/nc650/flash.c542
-rw-r--r--board/nc650/nand.c110
-rw-r--r--board/nc650/nc650.c309
-rw-r--r--board/nc650/u-boot.lds126
-rw-r--r--board/nc650/u-boot.lds.debug125
-rw-r--r--board/palmld/Makefile (renamed from board/timll/devkit8000/config.mk)46
-rw-r--r--board/palmld/config.mk1
-rw-r--r--board/palmld/lowlevel_init.S (renamed from board/zipitz2/lowlevel_init.S)9
-rw-r--r--board/palmld/palmld.c69
-rw-r--r--board/palmld/u-boot.lds (renamed from board/vpac270/u-boot.lds)7
-rw-r--r--board/palmtc/Makefile49
-rw-r--r--board/palmtc/config.mk1
-rw-r--r--board/palmtc/lowlevel_init.S (renamed from board/vpac270/lowlevel_init.S)3
-rw-r--r--board/palmtc/palmtc.c (renamed from board/atmel/at91rm9200ek/partition.c)61
-rw-r--r--board/palmtc/u-boot.lds56
-rw-r--r--board/pxa255_idp/pxa_idp.c27
-rw-r--r--board/sbc8641d/sbc8641d.c103
-rw-r--r--board/sbc8641d/u-boot.lds132
-rw-r--r--board/tqc/tqm85xx/law.c4
-rw-r--r--board/tqc/tqm85xx/tlb.c10
-rw-r--r--board/tqc/tqm85xx/tqm85xx.c151
-rw-r--r--board/trizepsiv/conxs.c35
-rw-r--r--board/ttcontrol/vision2/vision2.c2
-rw-r--r--board/vpac270/Makefile17
-rw-r--r--board/vpac270/config.mk1
-rw-r--r--board/vpac270/vpac270.c92
-rw-r--r--board/wepep250/wepep250.c11
-rw-r--r--board/zipitz2/Makefile10
-rw-r--r--board/zipitz2/config.mk1
-rw-r--r--board/zipitz2/zipitz2.c57
-rw-r--r--board/zylonite/nand.c110
-rw-r--r--boards.cfg32
-rw-r--r--common/cmd_fpga.c50
-rw-r--r--common/fdt_support.c1
-rw-r--r--common/image.c83
-rw-r--r--common/serial.c2
-rw-r--r--doc/README.arm-relocation232
-rw-r--r--doc/README.fsl-ddr14
-rw-r--r--doc/README.scrapyard29
-rw-r--r--doc/README.ubi144
-rw-r--r--drivers/i2c/omap24xx_i2c.c209
-rw-r--r--drivers/mmc/pxa_mmc.c98
-rw-r--r--drivers/net/fec_mxc.c3
-rw-r--r--drivers/net/uli526x.c5
-rw-r--r--drivers/qe/uec.c10
-rw-r--r--drivers/qe/uec.h20
-rw-r--r--drivers/qe/uec_phy.c8
-rw-r--r--drivers/serial/serial_pxa.c94
-rw-r--r--drivers/usb/host/ehci-hcd.c1
-rw-r--r--drivers/usb/host/ehci-mxc.c2
-rw-r--r--drivers/usb/host/ehci.h14
-rw-r--r--fs/fat/fat.c2
-rw-r--r--include/configs/NC650.h451
-rw-r--r--include/configs/P2020DS.h5
-rw-r--r--include/configs/TQM85xx.h20
-rw-r--r--include/configs/a4m072.h6
-rw-r--r--include/configs/amcc-common.h15
-rw-r--r--include/configs/at91rm9200ek.h286
-rw-r--r--include/configs/balloon3.h274
-rw-r--r--include/configs/cerf250.h3
-rw-r--r--include/configs/colibri_pxa270.h3
-rw-r--r--include/configs/corenet_ds.h61
-rw-r--r--include/configs/cradle.h5
-rw-r--r--include/configs/csb226.h3
-rw-r--r--include/configs/delta.h4
-rw-r--r--include/configs/devkit8000.h5
-rw-r--r--include/configs/eb_cpux9k2.h23
-rw-r--r--include/configs/edminiv2.h5
-rw-r--r--include/configs/imx31_litekit.h7
-rw-r--r--include/configs/innokom.h3
-rw-r--r--include/configs/jornada.h155
-rw-r--r--include/configs/lubbock.h3
-rw-r--r--include/configs/lwmon5.h11
-rw-r--r--include/configs/mx51evk.h4
-rw-r--r--include/configs/palmld.h276
-rw-r--r--include/configs/palmtc.h248
-rw-r--r--include/configs/pleb2.h3
-rw-r--r--include/configs/pxa255_idp.h3
-rw-r--r--include/configs/qong.h32
-rw-r--r--include/configs/trizepsiv.h3
-rw-r--r--include/configs/tx25.h2
-rw-r--r--include/configs/vision2.h4
-rw-r--r--include/configs/vpac270.h138
-rw-r--r--include/configs/wepep250.h4
-rw-r--r--include/configs/xaeniax.h3
-rw-r--r--include/configs/xm250.h3
-rw-r--r--include/configs/xsengine.h3
-rw-r--r--include/configs/zipitz2.h10
-rw-r--r--include/configs/zylonite.h3
-rwxr-xr-xinclude/lattice.h1
-rw-r--r--include/post.h4
-rw-r--r--nand_spl/board/karo/tx25/u-boot.lds13
-rw-r--r--nand_spl/nand_boot.c3
-rw-r--r--nand_spl/nand_boot_fsl_nfc.c3
-rw-r--r--onenand_ipl/board/vpac270/Makefile5
-rw-r--r--post/drivers/memory.c68
-rw-r--r--post/tests.c4
199 files changed, 6712 insertions, 5978 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 5108c54..2f61776 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -102,7 +102,6 @@ Wolfgang Denk <wd@denx.de>
IVMS8_256 MPC860
LANTEC MPC850
LWMON MPC823
- NC650 MPC852
R360MPI MPC823
RMU MPC850
RRvision MPC823
@@ -573,6 +572,10 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
+Andreas Bießmann <andreas.devel@gmail.com>
+
+ at91rm9200ek at91rm9200
+
Cliff Brake <cliff.brake@gmail.com>
pxa255_idp xscale
@@ -598,6 +601,10 @@ Thomas Elste <info@elste.org>
modnet50 ARM720T (NET+50)
+Kristoffer Ericson <kristoffer.ericson@gmail.com>
+
+ jornada SA1110
+
Fabio Estevam <Fabio.Estevam@freescale.com>
mx31pdk i.MX31
@@ -805,6 +812,15 @@ Greg Ungerer <greg.ungerer@opengear.com>
cm4116 ks8695p
cm4148 ks8695p
+Marek Vasut <marek.vasut@gmail.com>
+
+ balloon3 xscale
+ colibri_pxa270 xscale
+ palmld xscale
+ palmtc xscale
+ vpac270 xscale
+ zipitz2 xscale
+
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
SFFSDR ARM926EJS
diff --git a/MAKEALL b/MAKEALL
index c1f3842..51312dd 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -468,12 +468,7 @@ LIST_at91=" \
## Xscale Systems
#########################################################################
-LIST_pxa="$(boards_by_cpu pxa)
- polaris \
- trizepsiv \
- vpac270_nor \
- vpac270_onenand \
-"
+LIST_pxa="$(boards_by_cpu pxa)"
LIST_ixp="$(boards_by_cpu ixp)
pdnb3 \
diff --git a/Makefile b/Makefile
index 30a564d..06c71a2 100644
--- a/Makefile
+++ b/Makefile
@@ -304,6 +304,21 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
#########################################################################
#########################################################################
+ifneq ($(CONFIG_BOARD_SIZE_LIMIT),)
+BOARD_SIZE_CHECK = \
+ @actual=`wc -c $@ | awk '{print $$1}'`; \
+ limit=$(CONFIG_BOARD_SIZE_LIMIT); \
+ if test $$actual -gt $$limit; then \
+ echo "$@ exceeds file size limit:"; \
+ echo " limit: $$limit bytes"; \
+ echo " actual: $$actual bytes"; \
+ echo " excess: $$((actual - limit)) bytes"; \
+ exit 1; \
+ fi
+else
+BOARD_SIZE_CHECK =
+endif
+
# Always append ALL so that arch config.mk's can add custom ones
ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND)
@@ -317,10 +332,12 @@ $(obj)u-boot.srec: $(obj)u-boot
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+ $(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr: $(obj)u-boot
$(CREATE_LDR_ENV)
$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
+ $(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr
$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary
@@ -341,7 +358,7 @@ $(obj)u-boot.imx: $(obj)u-boot.bin
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
- -a $(CONFIG_SYS_TEXT_BASE) -e $(TEXT_BASE) -d $< $@
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
@@ -1010,23 +1027,6 @@ scpu_config: unconfig
fi
@$(MKCONFIG) -n $@ -a pdnb3 arm ixp pdnb3 prodrive
-polaris_config \
-trizepsiv_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring polaris,$@)" ] ; then \
- echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv
-
-vpac270_nor_config \
-vpac270_onenand_config : unconfig
- @mkdir -p $(obj)include
- @if [ "$(findstring onenand,$@)" ] ; then \
- echo "#define CONFIG_ONENAND_U_BOOT" \
- >>$(obj)include/config.h ; \
- fi;
- @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270
-
#########################################################################
## ARM1136 Systems
#########################################################################
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 6923f6d..21c1e33 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -33,11 +33,6 @@ STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
-ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
-# needed for relocation
-PLATFORM_RELFLAGS += -fPIC
-endif
-
ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
endif
@@ -72,3 +67,10 @@ PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
endif
endif
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
+# needed for relocation
+ifndef CONFIG_NAND_SPL
+PLATFORM_LDFLAGS += -pie
+endif
+endif
diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index cbe8243..8bd23ee 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -93,17 +93,16 @@ void mx31_gpio_mux(unsigned long mode)
void mx31_set_pad(enum iomux_pins pin, u32 config)
{
- u32 field, l;
- void *reg;
+ u32 field, l, reg;
pin &= IOMUX_PADNUM_MASK;
reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
- l = __raw_readl(reg);
+ l = __REG(reg);
l &= ~(0x1ff << (field * 10));
l |= config << (field * 10);
- __raw_writel(l, reg);
+ __REG(reg) = l;
}
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 5008ac6..29ed065 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -89,48 +89,35 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
-
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
-
-.globl _bss_end
-_bss_end:
- .word _end
-
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
+.globl _datarel_start_ofs
+_datarel_start_ofs:
+ .word __datarel_start - _start
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
+.globl _datarelrolocal_start_ofs
+_datarelrolocal_start_ofs:
+ .word __datarelrolocal_start - _start
-.globl _got_start
-_got_start:
- .word __got_start
+.globl _datarellocal_start_ofs
+_datarellocal_start_ofs:
+ .word __datarellocal_start - _start
-.globl _got_end
-_got_end:
- .word __got_end
-#endif
+.globl _datarelro_start_ofs
+_datarelro_start_ofs:
+ .word __datarelro_start - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@@ -225,9 +212,8 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
@@ -239,36 +225,54 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r7, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r8, r1, #0xff
+ cmp r8, #23 /* relative fixup? */
+ beq fixrel
+ cmp r8, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ ble fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
- sub r0, r0, r3
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@@ -283,24 +287,34 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
-
-_nand_boot: .word nand_boot
+ ldr r0, _nand_boot_ofs
+ adr r1, _start
+ add pc, r0, r1
+_nand_boot_ofs
+ : .word nand_boot - _start
#else
jump_2_ram:
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add r0, r0, r1
+ add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
+
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
+
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
@@ -375,8 +389,11 @@ stack_setup:
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
+ adr r2, _start
+ ldr r0, _bss_start_ofs /* find start of bss segment */
+ add r0, r0, r2
+ ldr r1, _bss_end_ofs /* stop here */
+ add r1, r1, r2
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
@@ -386,15 +403,19 @@ clbss_l:str r2, [r0] /* clear loop... */
bne clbss_l
#endif
- ldr pc, _start_armboot
+ ldr r0, _start_armboot_ofs
+ adr r1, _start
+ add r0, r0, r1
+ ldr pc, r0
+_start_armboot_ofs:
#ifdef CONFIG_NAND_SPL
-_start_armboot: .word nand_boot
+ .word nand_boot - _start
#else
#ifdef CONFIG_ONENAND_IPL
-_start_armboot: .word start_oneboot
+ .word start_oneboot - _start
#else
-_start_armboot: .word start_armboot
+ .word start_armboot - _start
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_NAND_SPL */
@@ -487,7 +508,7 @@ cpu_init_crit:
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
#else
- ldr r2, _armboot_start
+ adr r2, _start
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#endif
@@ -524,8 +545,8 @@ cpu_init_crit:
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
#else
- ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
- sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
+ adr r13, _start @ setup our mode stack (enter in banked mode)
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
#endif
diff --git a/arch/arm/cpu/arm1136/u-boot.lds b/arch/arm/cpu/arm1136/u-boot.lds
index 1db4b49..31f43f0 100644
--- a/arch/arm/cpu/arm1136/u-boot.lds
+++ b/arch/arm/cpu/arm1136/u-boot.lds
@@ -59,11 +59,14 @@ SECTIONS
*(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
+ __rel_dyn_start = .;
+ .rel.dyn : { *(.rel.dyn) }
+ __rel_dyn_end = .;
+
+ __dynsym_start = .;
+ .dynsym : { *(.dynsym) }
- __got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
@@ -73,4 +76,10 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index ecf91f5..7a10a77 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -11,47 +11,46 @@
* (at your option) any later version.
*/
-#include <config.h>
+#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
-static unsigned long cpu_clk_rate_hz;
-static unsigned long main_clk_rate_hz;
-static unsigned long mck_rate_hz;
-static unsigned long plla_rate_hz;
-static unsigned long pllb_rate_hz;
-static u32 at91_pllb_usb_init;
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
unsigned long get_cpu_clk_rate(void)
{
- return cpu_clk_rate_hz;
+ return gd->cpu_clk_rate_hz;
}
unsigned long get_main_clk_rate(void)
{
- return main_clk_rate_hz;
+ return gd->main_clk_rate_hz;
}
unsigned long get_mck_clk_rate(void)
{
- return mck_rate_hz;
+ return gd->mck_rate_hz;
}
unsigned long get_plla_clk_rate(void)
{
- return plla_rate_hz;
+ return gd->plla_rate_hz;
}
unsigned long get_pllb_clk_rate(void)
{
- return pllb_rate_hz;
+ return gd->pllb_rate_hz;
}
u32 get_pllb_init(void)
{
- return at91_pllb_usb_init;
+ return gd->at91_pllb_usb_init;
}
static unsigned long at91_css_to_rate(unsigned long css)
@@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
case AT91_PMC_MCKR_CSS_SLOW:
return AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
- return main_clk_rate_hz;
+ return gd->main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
- return plla_rate_hz;
+ return gd->plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
- return pllb_rate_hz;
+ return gd->pllb_rate_hz;
}
return 0;
@@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock)
main_clock = tmp * (AT91_SLOW_CLOCK / 16);
}
#endif
- main_clk_rate_hz = main_clock;
+ gd->main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
- plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+ gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
@@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock)
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
- at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+ gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2;
- pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
+ gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
#endif
/*
@@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock)
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* plla divisor by 2 */
- plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+ gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
- mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = mck_rate_hz;
+ gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+ freq = gd->mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
/* mdiv */
- mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+ gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#elif defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+ gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
- mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+ gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
- mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+ gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
- cpu_clk_rate_hz = freq;
+ gd->cpu_clk_rate_hz = freq;
return 0;
}
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
index 8efc34b..82b8d7e 100644
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -30,55 +30,63 @@
#include <asm/arch/io.h>
#include <div64.h>
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
*/
-#define TIMER_LOAD_VAL 0xfffff
-static ulong timestamp;
-static ulong lastinc;
-static ulong timer_freq;
+#define TIMER_LOAD_VAL 0xfffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, timer_freq);
+ do_div(tick, gd->timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
- usec *= timer_freq;
+ usec *= gd->timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
-/* nothing really to do with interrupts, just starts up a counter. */
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
int timer_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
- /*
- * Enable PITC Clock
- * The clock is already enabled for system controller in boot
- */
+
+ /* Enable PITC Clock */
writel(1 << AT91_ID_SYS, &pmc->pcer);
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
- reset_timer_masked();
-
- timer_freq = get_mck_clk_rate() >> 4;
+ gd->timer_rate_hz = gd->mck_rate_hz / 16;
+ gd->tbu = gd->tbl = 0;
return 0;
}
/*
- * timer without interrupts
+ * Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
@@ -86,28 +94,11 @@ unsigned long long get_ticks(void)
ulong now = readl(&pit->piir);
- if (now >= lastinc) /* normal mode (non roll) */
- /* move stamp forward with absolut diff ticks */
- timestamp += (now - lastinc);
- else /* we have rollover of incrementer */
- timestamp += (0xFFFFFFFF - lastinc) + now;
- lastinc = now;
- return timestamp;
-}
-
-void reset_timer_masked(void)
-{
- /* reset time */
- at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
-
- /* capture current incrementer value time */
- lastinc = readl(&pit->piir);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->tbl)
+ gd->tbu++;
+ gd->tbl = now;
+ return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
@@ -119,24 +110,32 @@ void __udelay(unsigned long usec)
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
- /*NOP*/;
+ ;
}
+/*
+ * reset_timer() and get_timer(base) are a pair of functions that are used by
+ * some timeout/sleep mechanisms in u-boot.
+ *
+ * reset_timer() marks the current time as epoch and
+ * get_timer(base) works relative to that epoch.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
void reset_timer(void)
{
- reset_timer_masked();
+ gd->timer_reset_value = get_ticks();
}
ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
}
/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
+ * Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
- return timer_freq;
+ return gd->timer_rate_hz;
}
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 8cbe3e7..863de3b 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -10,6 +10,7 @@
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2010 Albert Aribaud <albert.aribaud@free.fr>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -118,22 +119,19 @@ _fiq:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-.globl _armboot_start
-_armboot_start:
- .word _start
-#endif
-
/*
* These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@@ -153,30 +151,6 @@ FIQ_STACK_START:
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
-
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
-
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
-
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
-
-.globl _got_start
-_got_start:
- .word __got_start
-
-.globl _got_end
-_got_end:
- .word __got_end
-
/*
* the actual reset code
*/
@@ -226,9 +200,8 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
@@ -240,36 +213,54 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE /* Text base */
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r7, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r8, r1, #0xff
+ cmp r8, #23 /* relative fixup? */
+ beq fixrel
+ cmp r8, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
- sub r0, r0, r3
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@@ -287,24 +278,33 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
+ ldr r0, _nand_boot_ofs
+ mov pc, r0
-_nand_boot: .word nand_boot
+_nand_boot_ofs:
+ .word nand_boot
#else
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add r0, r0, r1
+ add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
#endif
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
+
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
@@ -333,10 +333,8 @@ relocate: /* relocate U-Boot to RAM */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
+ ldr r3, _bss_start_ofs /* r3 <- _bss_start - _start */
+ add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
@@ -360,8 +358,11 @@ stack_setup:
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
+ adr r2, _start
+ ldr r0, _bss_start_ofs /* find start of bss segment */
+ add r0, r0, r2
+ ldr r1, _bss_end_ofs /* stop here */
+ add r1, r1, r2
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
@@ -374,13 +375,16 @@ clbss_l:str r2, [r0] /* clear loop... */
bl red_LED_on
#endif /* CONFIG_PRELOADER */
- ldr pc, _start_armboot
+ ldr r0, _start_armboot_ofs
+ adr r1, _start
+ add r0, r0, r1
+ ldr pc, r0
-_start_armboot:
+_start_armboot_ofs:
#ifdef CONFIG_NAND_SPL
- .word nand_boot
+ .word nand_boot - _start
#else
- .word start_armboot
+ .word start_armboot - _start
#endif /* CONFIG_NAND_SPL */
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
@@ -469,7 +473,7 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r2, _armboot_start
+ adr r2, _start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
@@ -507,7 +511,7 @@ cpu_init_crit:
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
- ldr r13, _armboot_start @ setup our mode stack
+ adr r13, _start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds b/arch/arm/cpu/arm926ejs/u-boot.lds
index 02eb8ca..72f45f8 100644
--- a/arch/arm/cpu/arm926ejs/u-boot.lds
+++ b/arch/arm/cpu/arm926ejs/u-boot.lds
@@ -41,21 +41,19 @@ SECTIONS
. = ALIGN(4);
.data : {
*(.data)
- __datarel_start = .;
- *(.data.rel)
- __datarelrolocal_start = .;
- *(.data.rel.ro.local)
- __datarellocal_start = .;
- *(.data.rel.local)
- __datarelro_start = .;
- *(.data.rel.ro)
}
- __got_start = .;
. = ALIGN(4);
- .got : { *(.got) }
- __got_end = .;
+ __rel_dyn_start = .;
+ .rel.dyn : { *(.rel.dyn) }
+ __rel_dyn_end = .;
+
+ __dynsym_start = .;
+ .dynsym : { *(.dynsym) }
+
+ . = ALIGN(4);
+
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
@@ -65,4 +63,10 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
diff --git a/arch/arm/cpu/armv7/mx51/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index 7cfaa2c..7cfaa2c 100644
--- a/arch/arm/cpu/armv7/mx51/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
diff --git a/arch/arm/cpu/armv7/mx51/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index a27227d..00f649c 100644
--- a/arch/arm/cpu/armv7/mx51/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void)
reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
return freq / (reg + 1);
}
@@ -84,14 +84,14 @@ static u32 get_periph_clk(void)
reg = __raw_readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
reg = __raw_readl(&mxc_ccm->cbcmr);
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
+ return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
default:
return 0;
}
@@ -146,15 +146,15 @@ static u32 get_uart_clk(void)
MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
case 0x0:
freq = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
case 0x1:
freq = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
case 0x2:
freq = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
break;
default:
return 66500000;
@@ -181,7 +181,7 @@ u32 get_lp_apm(void)
u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
if (((ccsr >> 9) & 1) == 0)
- ret_val = CONFIG_MX51_HCLK_FREQ;
+ ret_val = CONFIG_SYS_MX5_HCLK;
else
ret_val = ((32768 * 1024));
@@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void)
switch (clk_sel) {
case 0:
ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 1:
ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
case 2:
ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_MX51_HCLK_FREQ) /
+ CONFIG_SYS_MX5_HCLK) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
@@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return imx_get_cspiclk();
case MXC_FEC_CLK:
return decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_MX51_HCLK_FREQ);
+ CONFIG_SYS_MX5_HCLK);
default:
break;
}
@@ -269,16 +269,16 @@ u32 imx_get_fecclk(void)
/*
* Dump some core clockes.
*/
-int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u32 freq;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll1: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll2: %dMHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
- printf("mx51 pll3: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll1: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll2: %dMHz\n", freq / 1000000);
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ printf("pll3: %dMHz\n", freq / 1000000);
printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
@@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
/***************************************************/
U_BOOT_CMD(
- clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks,
- "display mx51 clocks\n",
+ clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
+ "display clocks\n",
""
);
diff --git a/arch/arm/cpu/armv7/mx51/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
index 62b2954..e8928d5 100644
--- a/arch/arm/cpu/armv7/mx51/iomux.c
+++ b/arch/arm/cpu/armv7/mx5/iomux.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
diff --git a/arch/arm/cpu/armv7/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 783c81f..e984870 100644
--- a/arch/arm/cpu/armv7/mx51/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -257,20 +257,6 @@ lowlevel_init:
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
-#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr /* save old spsr */
- mrs r0, cpsr /* read out the cpsr */
- bic r0, r0, #0x100 /* clear the A bit */
- msr spsr, r0 /* update spsr */
- add lr, pc, #0x8 /* update lr */
- movs pc, lr /* update cpsr */
- nop
- nop
- nop
- nop
- msr spsr, r1 /* restore old spsr */
-#endif
-
init_l2cc
init_aips
diff --git a/arch/arm/cpu/armv7/mx51/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index f22ebe9..7c7a565 100644
--- a/arch/arm/cpu/armv7/mx51/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -33,28 +33,33 @@
#include <fsl_esdhc.h>
#endif
+#if defined(CONFIG_MX51)
+#define CPU_TYPE 0x51000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
u32 get_cpu_rev(void)
{
- int reg;
- int system_rev;
+ int system_rev = CPU_TYPE;
+ int reg = __raw_readl(ROM_SI_REV);
- reg = __raw_readl(ROM_SI_REV);
switch (reg) {
case 0x02:
- system_rev = 0x51000 | CHIP_REV_1_1;
+ system_rev |= CHIP_REV_1_1;
break;
case 0x10:
if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
- system_rev = 0x51000 | CHIP_REV_2_5;
+ system_rev |= CHIP_REV_2_5;
else
- system_rev = 0x51000 | CHIP_REV_2_0;
+ system_rev |= CHIP_REV_2_0;
break;
case 0x20:
- system_rev = 0x51000 | CHIP_REV_3_0;
+ system_rev |= CHIP_REV_3_0;
break;
return system_rev;
default:
- system_rev = 0x51000 | CHIP_REV_1_0;
+ system_rev |= CHIP_REV_1_0;
break;
}
return system_rev;
@@ -67,9 +72,10 @@ int print_cpuinfo(void)
u32 cpurev;
cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
- (cpurev & 0xF0) >> 4,
- (cpurev & 0x0F) >> 4,
+ printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
+ (cpurev & 0xFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
return 0;
}
diff --git a/arch/arm/cpu/armv7/mx51/speed.c b/arch/arm/cpu/armv7/mx5/speed.c
index a444def..a444def 100644
--- a/arch/arm/cpu/armv7/mx51/speed.c
+++ b/arch/arm/cpu/armv7/mx5/speed.c
diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx5/timer.c
index 110edbf..3044fcf 100644
--- a/arch/arm/cpu/armv7/mx51/timer.c
+++ b/arch/arm/cpu/armv7/mx5/timer.c
@@ -75,18 +75,18 @@ void reset_timer(void)
void reset_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+ lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
}
ulong get_timer_masked(void)
{
ulong val = __raw_readl(&cur_gpt->counter);
- val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+ val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
if (val >= lastinc)
timestamp += (val - lastinc);
else
- timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
+ timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
- lastinc) + val;
lastinc = val;
return timestamp;
@@ -106,7 +106,7 @@ void set_timer(ulong t)
void __udelay(unsigned long usec)
{
unsigned long now, start, tmo;
- tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
+ tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
if (!tmo)
tmo = 1;
diff --git a/arch/arm/cpu/armv7/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx5/u-boot.lds
index 55d6599..55d6599 100644
--- a/arch/arm/cpu/armv7/mx51/u-boot.lds
+++ b/arch/arm/cpu/armv7/mx5/u-boot.lds
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 26f335a..64c86e9 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -78,13 +78,13 @@ _armboot_start:
/*
* These are defined in the board-specific linker script.
*/
-.globl _bss_start
-_bss_start:
- .word __bss_start
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
-.globl _bss_end
-_bss_end:
- .word _end
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@@ -104,29 +104,29 @@ FIQ_STACK_START:
IRQ_STACK_START_IN:
.word 0x0badc0de
-.globl _datarel_start
-_datarel_start:
- .word __datarel_start
+.globl _datarel_start_ofs
+_datarel_start_ofs:
+ .word __datarel_start - _start
-.globl _datarelrolocal_start
-_datarelrolocal_start:
- .word __datarelrolocal_start
+.globl _datarelrolocal_start_ofs
+_datarelrolocal_start_ofs:
+ .word __datarelrolocal_start - _start
-.globl _datarellocal_start
-_datarellocal_start:
- .word __datarellocal_start
+.globl _datarellocal_start_ofs
+_datarellocal_start_ofs:
+ .word __datarellocal_start - _start
-.globl _datarelro_start
-_datarelro_start:
- .word __datarelro_start
+.globl _datarelro_start_ofs
+_datarelro_start_ofs:
+ .word __datarelro_start - _start
-.globl _got_start
-_got_start:
- .word __got_start
+.globl _got_start_ofs
+_got_start_ofs:
+ .word __got_start - _start
-.globl _got_end
-_got_end:
- .word __got_end
+.globl _got_end_Ofs
+_got_end_ofs:
+ .word __got_end - _start
/*
* the actual reset code
@@ -198,9 +198,8 @@ stack_setup:
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
adr r0, _start
ldr r2, _TEXT_BASE
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
#ifndef CONFIG_PRELOADER
beq jump_2_ram
@@ -213,33 +212,51 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
- /* fix got entries */
- ldr r1, _TEXT_BASE
- mov r0, r7 /* reloc addr */
- ldr r2, _got_start /* addr in Flash */
- ldr r3, _got_end /* addr in Flash */
- sub r3, r3, r1
- add r3, r3, r0
- sub r2, r2, r1
- add r2, r2, r0
-
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r7, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
- ldr r4, [r2]
- sub r4, r4, r1
- add r4, r4, r0
- str r4, [r2]
- add r2, r2, #4
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r8, r1, #0xff
+ cmp r8, #23 /* relative fixup? */
+ beq fixrel
+ cmp r8, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
- bne fixloop
+ blo fixloop
clear_bss:
- ldr r0, _bss_start
- ldr r1, _bss_end
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
- sub r0, r0, r3
add r0, r0, r4
- sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@@ -255,18 +272,26 @@ clbss_l:str r2, [r0] /* clear loop... */
* initialization, now running from RAM.
*/
jump_2_ram:
- ldr r0, _TEXT_BASE
- ldr r2, _board_init_r
- sub r2, r2, r0
- add r2, r2, r7 /* position from board_init_r in RAM */
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add r0, r0, r1
+ add lr, r0, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
- mov lr, r2
mov pc, lr
-_board_init_r: .word board_init_r
+_board_init_r_ofs:
+ .word board_init_r - _start
+
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
+
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds
index d4fd3fc..88a0fec 100644
--- a/arch/arm/cpu/armv7/u-boot.lds
+++ b/arch/arm/cpu/armv7/u-boot.lds
@@ -53,6 +53,13 @@ SECTIONS
__datarelro_start = .;
*(.data.rel.ro)
}
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ .rel.dyn : { *(.rel.dyn) }
+ __rel_dyn_end = .;
+
+ __dynsym_start = .;
+ .dynsym : { *(.dynsym) }
__got_start = .;
. = ALIGN(4);
diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
index 800d120..3ea3458 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/cpu.c
@@ -30,10 +30,11 @@
* CPU specific code
*/
-#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
#include <command.h>
+#include <common.h>
#include <asm/arch/pxa-regs.h>
-#include <asm/system.h>
static void cache_flush(void);
@@ -71,17 +72,249 @@ void set_GPIO_mode(int gpio_mode)
{
int gpio = gpio_mode & GPIO_MD_MASK_NR;
int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
- int gafr;
+ int val;
+
+ /* This below changes direction setting of GPIO "gpio" */
+ val = readl(GPDR(gpio));
if (gpio_mode & GPIO_MD_MASK_DIR)
- {
- GPDR(gpio) |= GPIO_bit(gpio);
- }
+ val |= GPIO_bit(gpio);
else
- {
- GPDR(gpio) &= ~GPIO_bit(gpio);
- }
- gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
- GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
+ val &= ~GPIO_bit(gpio);
+
+ writel(val, GPDR(gpio));
+
+ /* This below updates only AF of GPIO "gpio" */
+ val = readl(GAFR(gpio));
+ val &= ~(0x3 << (((gpio) & 0xf) * 2));
+ val |= fn << (((gpio) & 0xf) * 2);
+ writel(val, GAFR(gpio));
}
#endif /* CONFIG_CPU_MONAHANS */
+
+void pxa_wait_ticks(int ticks)
+{
+ writel(0, OSCR);
+ while (readl(OSCR) < ticks)
+ asm volatile("":::"memory");
+}
+
+inline void writelrb(uint32_t val, uint32_t addr)
+{
+ writel(val, addr);
+ asm volatile("":::"memory");
+ readl(addr);
+ asm volatile("":::"memory");
+}
+
+void pxa_dram_init(void)
+{
+ uint32_t tmp;
+ int i;
+ /*
+ * 1) Initialize Asynchronous static memory controller
+ */
+
+ writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
+ writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
+ writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
+ /*
+ * 2) Initialize Card Interface
+ */
+
+ /* MECR: Memory Expansion Card Register */
+ writelrb(CONFIG_SYS_MECR_VAL, MECR);
+ /* MCMEM0: Card Interface slot 0 timing */
+ writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
+ /* MCMEM1: Card Interface slot 1 timing */
+ writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
+ /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+ writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
+ /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+ writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
+ /* MCIO0: Card Interface I/O Space Timing, slot 0 */
+ writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
+ /* MCIO1: Card Interface I/O Space Timing, slot 1 */
+ writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
+
+ /*
+ * 3) Configure Fly-By DMA register
+ */
+
+ writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
+
+ /*
+ * 4) Initialize Timing for Sync Memory (SDCLK0)
+ */
+
+ /*
+ * Before accessing MDREFR we need a valid DRI field, so we set
+ * this to power on defaults + DRI field.
+ */
+
+ /* Read current MDREFR config and zero out DRI */
+ tmp = readl(MDREFR) & ~0xfff;
+ /* Add user-specified DRI */
+ tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
+ /* Configure important bits */
+ tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
+ tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
+
+ /* Write MDREFR back */
+ writelrb(tmp, MDREFR);
+
+ /*
+ * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+ */
+
+ /* Initialize SXCNFG register. Assert the enable bits.
+ *
+ * Write SXMRS to cause an MRS command to all enabled banks of
+ * synchronous static memory. Note that SXLCR need not be written
+ * at this time.
+ */
+ writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
+
+ /*
+ * 6) Initialize SDRAM
+ */
+
+ writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
+ writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
+
+ /*
+ * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+ * but not enable each SDRAM partition pair.
+ */
+
+ writelrb(CONFIG_SYS_MDCNFG_VAL &
+ ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+ /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+ pxa_wait_ticks(0x300);
+
+ /*
+ * 8) Trigger a number (usually 8) refresh cycles by attempting
+ * non-burst read or write accesses to disabled SDRAM, as commonly
+ * specified in the power up sequence documented in SDRAM data
+ * sheets. The address(es) used for this purpose must not be
+ * cacheable.
+ */
+ for (i = 9; i >= 0; i--) {
+ writel(i, 0xa0000000);
+ asm volatile("":::"memory");
+ }
+ /*
+ * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+ */
+
+ tmp = CONFIG_SYS_MDCNFG_VAL &
+ (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
+ tmp |= readl(MDCNFG);
+ writelrb(tmp, MDCNFG);
+
+ /*
+ * 10) Write MDMRS.
+ */
+
+ writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
+
+ /*
+ * 11) Enable APD
+ */
+
+ if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
+ tmp = readl(MDREFR);
+ tmp |= MDREFR_APD;
+ writelrb(tmp, MDREFR);
+ }
+}
+
+void pxa_gpio_setup(void)
+{
+ writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
+ writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
+ writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
+#endif
+
+ writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
+ writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
+ writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
+#endif
+
+ writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
+ writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
+ writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
+#endif
+
+ writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
+ writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
+ writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
+ writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
+ writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
+ writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
+ writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
+#endif
+
+ writel(CONFIG_SYS_PSSR_VAL, PSSR);
+}
+
+void pxa_interrupt_setup(void)
+{
+ writel(0, ICLR);
+ writel(0, ICMR);
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+ writel(0, ICLR2);
+ writel(0, ICMR2);
+#endif
+}
+
+void pxa_clock_setup(void)
+{
+#ifndef CONFIG_CPU_MONAHANS
+ writel(CONFIG_SYS_CKEN, CKEN);
+ writel(CONFIG_SYS_CCCR, CCCR);
+ asm volatile("mcr p14, 0, %0, c6, c0, 0"::"r"(2));
+#else
+/* Set CKENA/CKENB/ACCR for MH */
+#endif
+
+ /* enable the 32Khz oscillator for RTC and PowerManager */
+ writel(OSCC_OON, OSCC);
+ while(!(readl(OSCC) & OSCC_OOK))
+ asm volatile("":::"memory");
+}
+
+void pxa_wakeup(void)
+{
+ uint32_t rcsr;
+
+ rcsr = readl(RCSR);
+ writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
+
+ /* Wakeup */
+ if (rcsr & RCSR_SMR) {
+ writel(PSSR_PH, PSSR);
+ pxa_dram_init();
+ icache_disable();
+ dcache_disable();
+ asm volatile("mov pc, %0"::"r"(readl(PSSR)));
+ }
+}
+
+int arch_cpu_init(void)
+{
+ pxa_gpio_setup();
+// pxa_wait_ticks(0x8000);
+ pxa_wakeup();
+ pxa_interrupt_setup();
+ pxa_clock_setup();
+ return 0;
+}
diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c
index 6b72ba1..7aa49ae 100644
--- a/arch/arm/cpu/pxa/i2c.c
+++ b/arch/arm/cpu/pxa/i2c.c
@@ -33,6 +33,7 @@
/* FIXME: this file is PXA255 specific! What about other XScales? */
#include <common.h>
+#include <asm/io.h>
#ifdef CONFIG_HARD_I2C
@@ -93,19 +94,21 @@ struct i2c_msg {
static void i2c_reset( void )
{
- ICR &= ~ICR_IUE; /* disable unit */
- ICR |= ICR_UR; /* reset the unit */
+ writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
+ writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */
udelay(100);
- ICR &= ~ICR_IUE; /* disable unit */
+ writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */
#ifdef CONFIG_CPU_MONAHANS
- CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+ /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
+ writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
#else /* CONFIG_CPU_MONAHANS */
- CKEN |= CKEN14_I2C; /* set the global I2C clock on */
+ /* set the global I2C clock on */
+ writel(readl(CKEN) | CKEN14_I2C, CKEN);
#endif
- ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
- ICR = I2C_ICR_INIT; /* set control register values */
- ISR = I2C_ISR_INIT; /* set clear interrupt bits */
- ICR |= ICR_IUE; /* enable unit */
+ writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */
+ writel(I2C_ICR_INIT, ICR); /* set control reg values */
+ writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */
+ writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */
udelay(100);
}
@@ -159,22 +162,26 @@ int i2c_transfer(struct i2c_msg *msg)
goto transfer_error_bus_busy;
/* start transmission */
- ICR &= ~ICR_START;
- ICR &= ~ICR_STOP;
- IDBR = msg->data;
- if (msg->condition == I2C_COND_START) ICR |= ICR_START;
- if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
- if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
- if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
- ICR &= ~ICR_ALDIE;
- ICR |= ICR_TB;
+ writel(readl(ICR) & ~ICR_START, ICR);
+ writel(readl(ICR) & ~ICR_STOP, ICR);
+ writel(msg->data, IDBR);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(ICR) | ICR_START, ICR);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(ICR) | ICR_STOP, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(ICR) | ICR_ACKNAK, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+ writel(readl(ICR) & ~ICR_ALDIE, ICR);
+ writel(readl(ICR) | ICR_TB, ICR);
/* transmit register empty? */
if (!i2c_isr_set_cleared(ISR_ITE,0))
goto transfer_error_transmit_timeout;
/* clear 'transmit empty' state */
- ISR |= ISR_ITE;
+ writel(readl(ISR) | ISR_ITE, ISR);
/* wait for ACK from slave */
if (msg->acknack == I2C_ACKNAK_WAITACK)
@@ -189,23 +196,27 @@ int i2c_transfer(struct i2c_msg *msg)
goto transfer_error_bus_busy;
/* start receive */
- ICR &= ~ICR_START;
- ICR &= ~ICR_STOP;
- if (msg->condition == I2C_COND_START) ICR |= ICR_START;
- if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
- if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
- if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
- ICR &= ~ICR_ALDIE;
- ICR |= ICR_TB;
+ writel(readl(ICR) & ~ICR_START, ICR);
+ writel(readl(ICR) & ~ICR_STOP, ICR);
+ if (msg->condition == I2C_COND_START)
+ writel(readl(ICR) | ICR_START, ICR);
+ if (msg->condition == I2C_COND_STOP)
+ writel(readl(ICR) | ICR_STOP, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDNAK)
+ writel(readl(ICR) | ICR_ACKNAK, ICR);
+ if (msg->acknack == I2C_ACKNAK_SENDACK)
+ writel(readl(ICR) & ~ICR_ACKNAK, ICR);
+ writel(readl(ICR) & ~ICR_ALDIE, ICR);
+ writel(readl(ICR) | ICR_TB, ICR);
/* receive register full? */
if (!i2c_isr_set_cleared(ISR_IRF,0))
goto transfer_error_receive_timeout;
- msg->data = IDBR;
+ msg->data = readl(IDBR);
/* clear 'receive empty' state */
- ISR |= ISR_IRF;
+ writel(readl(ISR) | ISR_IRF, ISR);
break;
diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index 0ee6a75..987fa06 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -35,6 +35,7 @@
#include <stdio_dev.h>
#include <lcd.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
/* #define DEBUG */
@@ -56,26 +57,26 @@
/* 640x480x16 @ 61 Hz */
vidinfo_t panel_info = {
- vl_col: 640,
- vl_row: 480,
- vl_width: 640,
- vl_height: 480,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 0,
- vl_clor: 0,
- vl_tft: 1,
- vl_hpw: 40,
- vl_blw: 56,
- vl_elw: 56,
- vl_vpw: 20,
- vl_bfw: 8,
- vl_efw: 8,
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_width = 640,
+ .vl_height = 480,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 0,
+ .vl_clor = 0,
+ .vl_tft = 1,
+ .vl_hpw = 40,
+ .vl_blw = 56,
+ .vl_elw = 56,
+ .vl_vpw = 20,
+ .vl_bfw = 8,
+ .vl_efw = 8,
};
#endif /* CONFIG_PXA_VIDEO */
@@ -90,26 +91,26 @@ vidinfo_t panel_info = {
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
- vl_col: 640,
- vl_row: 480,
- vl_width: 157,
- vl_height: 118,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 1,
- vl_clor: 1,
- vl_tft: 0,
- vl_hpw: 1,
- vl_blw: 3,
- vl_elw: 3,
- vl_vpw: 1,
- vl_bfw: 0,
- vl_efw: 0,
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_width = 157,
+ .vl_height = 118,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 0,
+ .vl_hpw = 1,
+ .vl_blw = 3,
+ .vl_elw = 3,
+ .vl_vpw = 1,
+ .vl_bfw = 0,
+ .vl_efw = 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
/*----------------------------------------------------------------------*/
@@ -123,26 +124,26 @@ vidinfo_t panel_info = {
# define REG_LCCR3 0x0340FF08
vidinfo_t panel_info = {
- vl_col: 640,
- vl_row: 480,
- vl_width: 157,
- vl_height: 118,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 1,
- vl_clor: 1,
- vl_tft: 1,
- vl_hpw: 32,
- vl_blw: 144,
- vl_elw: 32,
- vl_vpw: 2,
- vl_bfw: 13,
- vl_efw: 30,
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_width = 157,
+ .vl_height = 118,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 32,
+ .vl_blw = 144,
+ .vl_elw = 32,
+ .vl_vpw = 2,
+ .vl_bfw = 13,
+ .vl_efw = 30,
};
#endif /* CONFIG_VOIPAC_LCD */
@@ -156,26 +157,26 @@ vidinfo_t panel_info = {
#define REG_LCCR3 0x0340FF20
vidinfo_t panel_info = {
- vl_col: 320,
- vl_row: 240,
- vl_width: 167,
- vl_height: 109,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_HIGH,
- vl_hsp: CONFIG_SYS_HIGH,
- vl_vsp: CONFIG_SYS_HIGH,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 1,
- vl_splt: 0,
- vl_clor: 1,
- vl_tft: 0,
- vl_hpw: 1,
- vl_blw: 1,
- vl_elw: 1,
- vl_vpw: 7,
- vl_bfw: 0,
- vl_efw: 0,
+ .vl_col = 320,
+ .vl_row = 240,
+ .vl_width = 167,
+ .vl_height = 109,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 1,
+ .vl_splt = 0,
+ .vl_clor = 1,
+ .vl_tft = 0,
+ .vl_hpw = 1,
+ .vl_blw = 1,
+ .vl_elw = 1,
+ .vl_vpw = 7,
+ .vl_bfw = 0,
+ .vl_efw = 0,
};
#endif /* CONFIG_HITACHI_SX14 */
@@ -190,31 +191,132 @@ vidinfo_t panel_info = {
# define REG_LCCR3 0x03b00009
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_width: 240,
- vl_height: 320,
- vl_clkp: CONFIG_SYS_HIGH,
- vl_oep: CONFIG_SYS_LOW,
- vl_hsp: CONFIG_SYS_LOW,
- vl_vsp: CONFIG_SYS_LOW,
- vl_dp: CONFIG_SYS_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
- vl_splt: 1,
- vl_clor: 1,
- vl_tft: 1,
- vl_hpw: 4,
- vl_blw: 4,
- vl_elw: 8,
- vl_vpw: 4,
- vl_bfw: 4,
- vl_efw: 8,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_width = 240,
+ .vl_height = 320,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 4,
+ .vl_blw = 4,
+ .vl_elw = 8,
+ .vl_vpw = 4,
+ .vl_bfw = 4,
+ .vl_efw = 8,
};
#endif /* CONFIG_LMS283GF05 */
/*----------------------------------------------------------------------*/
+#ifdef CONFIG_ACX517AKN
+
+# define LCD_BPP LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f9
+# define REG_LCCR3 0x03700006
+
+vidinfo_t panel_info = {
+ .vl_col = 320,
+ .vl_row = 320,
+ .vl_width = 320,
+ .vl_height = 320,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 0x04,
+ .vl_blw = 0x1c,
+ .vl_elw = 0x08,
+ .vl_vpw = 0x01,
+ .vl_bfw = 0x07,
+ .vl_efw = 0x08,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_LQ038J7DH53
+
+# define LCD_BPP LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f9
+# define REG_LCCR3 0x03700004
+
+vidinfo_t panel_info = {
+ .vl_col = 320,
+ .vl_row = 480,
+ .vl_width = 320,
+ .vl_height = 480,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_LOW,
+ .vl_hsp = CONFIG_SYS_LOW,
+ .vl_vsp = CONFIG_SYS_LOW,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 1,
+ .vl_clor = 1,
+ .vl_tft = 1,
+ .vl_hpw = 0x04,
+ .vl_blw = 0x20,
+ .vl_elw = 0x01,
+ .vl_vpw = 0x01,
+ .vl_bfw = 0x04,
+ .vl_efw = 0x01,
+};
+#endif /* CONFIG_ACX517AKN */
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_LITTLETON_LCD
+# define LCD_BPP LCD_COLOR8
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0 0x003008f8
+# define REG_LCCR3 0x0300FF04
+
+vidinfo_t panel_info = {
+ .vl_col = 480,
+ .vl_row = 640,
+ .vl_width = 480,
+ .vl_height = 640,
+ .vl_clkp = CONFIG_SYS_HIGH,
+ .vl_oep = CONFIG_SYS_HIGH,
+ .vl_hsp = CONFIG_SYS_HIGH,
+ .vl_vsp = CONFIG_SYS_HIGH,
+ .vl_dp = CONFIG_SYS_HIGH,
+ .vl_bpix = LCD_BPP,
+ .vl_lbw = 0,
+ .vl_splt = 0,
+ .vl_clor = 0,
+ .vl_tft = 1,
+ .vl_hpw = 9,
+ .vl_blw = 8,
+ .vl_elw = 24,
+ .vl_vpw = 2,
+ .vl_bfw = 2,
+ .vl_efw = 4,
+};
+#endif /* CONFIG_LITTLETON_LCD */
+
+/*----------------------------------------------------------------------*/
+
#if LCD_BPP == LCD_COLOR8
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
#endif
@@ -377,12 +479,14 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug("Setting GPIO for 4 bit data\n");
/* bits 58-61 */
- GPDR1 |= (0xf << 26);
- GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
+ writel(readl(GPDR1) | (0xf << 26), GPDR1);
+ writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
+ GAFR1_U);
/* bits 74-77 */
- GPDR2 |= (0xf << 10);
- GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+ writel(readl(GPDR2) | (0xf << 10), GPDR2);
+ writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+ GAFR2_L);
}
/* 8 bit interface */
@@ -391,15 +495,17 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug("Setting GPIO for 8 bit data\n");
/* bits 58-65 */
- GPDR1 |= (0x3f << 26);
- GPDR2 |= (0x3);
+ writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+ writel(readl(GPDR2) | (0x3), GPDR2);
- GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
- GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
+ writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+ GAFR1_U);
+ writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
/* bits 74-77 */
- GPDR2 |= (0xf << 10);
- GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
+ writel(readl(GPDR2) | (0xf << 10), GPDR2);
+ writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
+ GAFR2_L);
}
/* 16 bit interface */
@@ -407,11 +513,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug("Setting GPIO for 16 bit data\n");
/* bits 58-77 */
- GPDR1 |= (0x3f << 26);
- GPDR2 |= 0x00003fff;
+ writel(readl(GPDR1) | (0x3f << 26), GPDR1);
+ writel(readl(GPDR2) | 0x00003fff, GPDR2);
- GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
- GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
+ writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
+ GAFR1_U);
+ writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
}
else
{
@@ -425,26 +532,26 @@ static void pxafb_enable_controller (vidinfo_t *vid)
debug("Enabling LCD controller\n");
/* Sequence from 11.7.10 */
- LCCR3 = vid->pxa.reg_lccr3;
- LCCR2 = vid->pxa.reg_lccr2;
- LCCR1 = vid->pxa.reg_lccr1;
- LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
- FDADR0 = vid->pxa.fdadr0;
- FDADR1 = vid->pxa.fdadr1;
- LCCR0 |= LCCR0_ENB;
+ writel(vid->pxa.reg_lccr3, LCCR3);
+ writel(vid->pxa.reg_lccr2, LCCR2);
+ writel(vid->pxa.reg_lccr1, LCCR1);
+ writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
+ writel(vid->pxa.fdadr0, FDADR0);
+ writel(vid->pxa.fdadr1, FDADR1);
+ writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_1_LCD;
+ writel(readl(CKENA) | CKENA_1_LCD, CKENA);
#else
- CKEN |= CKEN16_LCD;
+ writel(readl(CKEN) | CKEN16_LCD, CKEN);
#endif
- debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
- debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
- debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
- debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
- debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
- debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
+ debug("FDADR0 = 0x%08x\n", readl(FDADR0));
+ debug("FDADR1 = 0x%08x\n", readl(FDADR1));
+ debug("LCCR0 = 0x%08x\n", readl(LCCR0));
+ debug("LCCR1 = 0x%08x\n", readl(LCCR1));
+ debug("LCCR2 = 0x%08x\n", readl(LCCR2));
+ debug("LCCR3 = 0x%08x\n", readl(LCCR3));
}
static int pxafb_init (vidinfo_t *vid)
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 9c5023b..684e44e 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -31,6 +31,14 @@
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/macro.h>
+
+/* takes care the CP15 update has taken place */
+.macro CPWAIT reg
+mrc p15,0,\reg,c2,c0,0
+mov \reg,\reg
+sub pc,pc,#4
+.endm
.globl _start
_start: b reset
@@ -86,11 +94,9 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
-#endif
/*
* These are defined in the board-specific linker script.
@@ -115,7 +121,7 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif /* CONFIG_USE_IRQ */
-#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
+#ifndef CONFIG_PRELOADER
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@@ -159,12 +165,84 @@ reset:
msr cpsr,r0
/*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
+ * Enable MMU to use DCache as DRAM
*/
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
+ /* Domain access -- enable for all CPs */
+ ldr r0, =0x0000ffff
+ mcr p15, 0, r0, c3, c0, 0
+
+ /* Point TTBR to MMU table */
+ ldr r0, =mmu_table
+ adr r2, _start
+ orr r0, r2
+ mcr p15, 0, r0, c2, c0, 0
+
+/* !!! Hereby, check if the code is running from SRAM !!! */
+/* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
+ * is linked to 0x0 too, so this makes things easier. */
+ cmp r2, #0x5c000000
+
+ ldreq r1, [r0]
+ orreq r1, r2
+ streq r1, [r0]
+
+ /* Kick in MMU, ICache, DCache, BTB */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, #0x1b00
+ bic r0, #0x0087
+ orr r0, #0x1800
+ orr r0, #0x0005
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT r0
+
+ /* Unlock Icache, Dcache */
+ mcr p15, 0, r0, c9, c1, 1
+ mcr p15, 0, r0, c9, c2, 1
+
+ /* Flush Icache, Dcache, BTB */
+ mcr p15, 0, r0, c7, c7, 0
+
+ /* Unlock I-TLB, D-TLB */
+ mcr p15, 0, r0, c10, c4, 1
+ mcr p15, 0, r0, c10, c8, 1
+
+ /* Flush TLB */
+ mcr p15, 0, r0, c8, c7, 0
+ /* Allocate 4096 bytes of Dcache as RAM */
+
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+
+ mov r4, #0x00
+ mov r5, #0x00
+ mov r2, #0x01
+ mcr p15, 0, r0, c9, c2, 0
+ CPWAIT r0
+
+ /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
+ mov r0, #128
+ mov r1, #0xa0000000
+alloc:
+ mcr p15, 0, r1, c7, c2, 5
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ strd r4, [r1], #8
+ subs r0, #0x01
+ bne alloc
+ /* Drain pending loads and stores */
+ mcr p15, 0, r0, c7, c10, 4
+ mov r2, #0x00
+ mcr p15, 0, r2, c9, c2, 0
+ CPWAIT r0
+
+ /* Jump to 0x0 ( + offset) if running from SRAM */
+ adr r0, zerojmp
+ bic r0, #0x5c000000
+ mov pc, r0
+zerojmp:
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
@@ -201,11 +279,13 @@ stack_setup:
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+ stmfd sp!, {r0-r12}
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
+ stmia r6!, {r3-r5, r7-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
+ ldmfd sp!, {r0-r12}
#ifndef CONFIG_PRELOADER
/* fix got entries */
@@ -274,218 +354,28 @@ _board_init_r: .word board_init_r
/****************************************************************************/
/* */
-/* the actual reset code */
+/* the actual reset code for OneNAND IPL */
/* */
/****************************************************************************/
+#ifndef CONFIG_PXA27X
+#error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
+#endif
+
reset:
- mrs r0,cpsr /* set the CPU to SVC32 mode */
- bic r0,r0,#0x1f /* (superviser mode, M=10011) */
+ /* Set CPU to SVC32 mode */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from RAM!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit /* we do sys-critical inits */
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate: /* relocate U-Boot to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
-#ifndef CONFIG_PRELOADER
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
-#endif
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
+ /* Point stack at the end of SRAM and leave 32 words for abort-stack */
+ ldr sp, =0x5c03ff80
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
-#ifdef CONFIG_PRELOADER
- sub sp, r0, #128 /* leave 32 words for abort-stack */
-#else
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
-#ifdef CONFIG_USE_IRQ
- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif /* CONFIG_USE_IRQ */
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-#endif
+ /* Start OneNAND IPL */
+ ldr pc, =start_oneboot
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-#ifndef CONFIG_PRELOADER
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- blo clbss_l
-#endif
-
- ldr pc, _start_armboot
-
-#ifdef CONFIG_ONENAND_IPL
-_start_armboot: .word start_oneboot
-#else
-_start_armboot: .word start_armboot
-#endif
-#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
-
-/****************************************************************************/
-/* */
-/* CPU_init_critical registers */
-/* */
-/* - setup important registers */
-/* - setup memory timing */
-/* */
-/****************************************************************************/
-/* mk@tbd: Fix this! */
-#undef RCSR
-#undef ICMR
-#undef OSMR3
-#undef OSCR
-#undef OWER
-#undef OIER
-#undef CCCR
-
-/* Interrupt-Controller base address */
-IC_BASE: .word 0x40d00000
-#define ICMR 0x04
-
-/* Reset-Controller */
-RST_BASE: .word 0x40f00030
-#define RCSR 0x00
-
-/* Operating System Timer */
-OSTIMER_BASE: .word 0x40a00000
-#define OSMR3 0x0C
-#define OSCR 0x10
-#define OWER 0x18
-#define OIER 0x1C
-
-/* Clock Manager Registers */
-#ifdef CONFIG_CPU_MONAHANS
-# ifndef CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
-# error "You have to define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO!!"
-# endif /* !CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO */
-# ifndef CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
-# define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
-# endif /* !CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO */
-#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_SYS_CPUSPEED
-CC_BASE: .word 0x41300000
-#define CCCR 0x00
-cpuspeed: .word CONFIG_SYS_CPUSPEED
-#else /* !CONFIG_SYS_CPUSPEED */
-#error "You have to define CONFIG_SYS_CPUSPEED!!"
-#endif /* CONFIG_SYS_CPUSPEED */
-#endif /* CONFIG_CPU_MONAHANS */
-
- /* takes care the CP15 update has taken place */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-cpu_init_crit:
-
- /* mask all IRQs */
-#ifndef CONFIG_CPU_MONAHANS
- ldr r0, IC_BASE
- mov r1, #0x00
- str r1, [r0, #ICMR]
-#else /* CONFIG_CPU_MONAHANS */
- /* Step 1 - Enable CP6 permission */
- mrc p15, 0, r1, c15, c1, 0 @ read CPAR
- orr r1, r1, #0x40
- mcr p15, 0, r1, c15, c1, 0
- CPWAIT r1
-
- /* Step 2 - Mask ICMR & ICMR2 */
- mov r1, #0
- mcr p6, 0, r1, c1, c0, 0 @ ICMR
- mcr p6, 0, r1, c7, c0, 0 @ ICMR2
-
- /* turn off all clocks but the ones we will definitly require */
- ldr r1, =CKENA
- ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
- str r2, [r1]
- ldr r1, =CKENB
- ldr r2, =(CKENB_6_IRQ)
- str r2, [r1]
-#endif /* !CONFIG_CPU_MONAHANS */
-
- /* set clock speed */
-#ifdef CONFIG_CPU_MONAHANS
- ldr r0, =ACCR
- ldr r1, =(((CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
- str r1, [r0]
-#else /* !CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_SYS_CPUSPEED
- ldr r0, CC_BASE
- ldr r1, cpuspeed
- str r1, [r0, #CCCR]
- mov r0, #2
- mcr p14, 0, r0, c6, c0, 0
-
-setspeed_done:
-
-#endif /* CONFIG_SYS_CPUSPEED */
-#endif /* CONFIG_CPU_MONAHANS */
-
- /*
- * before relocating, we have to setup RAM timing
- * because memory timing is board-dependend, you will
- * find a lowlevel_init.S in your board directory.
- */
- mov ip, lr
- bl lowlevel_init
- mov lr, ip
-
- /* Memory interfaces are working. Disable MMU and enable I-cache. */
- /* mk: hmm, this is not in the monahans docs, leave it now but
- * check here if it doesn't work :-) */
-
- ldr r0, =0x2001 /* enable access to all coproc. */
- mcr p15, 0, r0, c15, c1, 0
- CPWAIT r0
-
- mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
- CPWAIT r0
-
- mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
- CPWAIT r0
-
- mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
- CPWAIT r0
-
- /* Enable the Icache */
-/*
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #0x1800
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT
-*/
- mov pc, lr
+#endif /* #if !defined(CONFIG_ONENAND_IPL) */
#ifndef CONFIG_PRELOADER
/****************************************************************************/
@@ -676,6 +566,12 @@ fiq:
/* perform a watchdog timeout for a soft reset. */
/* */
/****************************************************************************/
+/* Operating System Timer */
+OSTIMER_BASE: .word 0x40a00000
+#define OSMR3 0x0C
+#define OSCR 0x10
+#define OWER 0x18
+#define OIER 0x1C
.align 5
.globl reset_cpu
@@ -703,3 +599,25 @@ reset_cpu:
reset_endless:
b reset_endless
+
+#ifndef CONFIG_PRELOADER
+.section .mmudata, "a"
+ .align 14
+ .globl mmu_table
+mmu_table:
+ /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
+ .set __base, 0
+ .rept 0xa00
+ .word (__base << 20) | 0xc12
+ .set __base, __base + 1
+ .endr
+
+ /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
+ .word (0xa00 << 20) | 0x1c1e
+
+ .set __base, 0xa01
+ .rept 0x1000 - 0xa01
+ .word (__base << 20) | 0xc12
+ .set __base, __base + 1
+ .endr
+#endif
diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c
index 8d0f826..ec950c7 100644
--- a/arch/arm/cpu/pxa/timer.c
+++ b/arch/arm/cpu/pxa/timer.c
@@ -26,8 +26,9 @@
* MA 02111-1307 USA
*/
-#include <common.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <common.h>
#include <div64.h>
#ifdef CONFIG_USE_IRQ
@@ -86,7 +87,7 @@ void __udelay (unsigned long usec)
void reset_timer_masked (void)
{
- OSCR = 0;
+ writel(0, OSCR);
}
ulong get_timer_masked (void)
@@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec)
*/
unsigned long long get_ticks(void)
{
- return OSCR;
+ return readl(OSCR);
}
/*
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
index bd718a6..0311d5e 100644
--- a/arch/arm/cpu/pxa/usb.c
+++ b/arch/arm/cpu/pxa/usb.c
@@ -27,86 +27,79 @@
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
#include <usb.h>
int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
- CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC);
+ writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
#if defined(CONFIG_PXA27X)
/* Enable USB host clock. */
- CKEN |= CKEN10_USBHOST;
+ writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
#if defined(CONFIG_CPU_MONAHANS)
/* Configure Port 2 for Host (USB Client Registers) */
- UP2OCR = 0x3000c;
+ writel(0x3000c, UP2OCR);
#endif
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
wait_ms(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCHR |= UHCHR_FSBIR;
- while (UHCHR & UHCHR_FSBIR)
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
udelay(1);
#if defined(CONFIG_CPU_MONAHANS)
- UHCHR &= ~UHCHR_SSEP0;
+ writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
- UHCHR &= ~UHCHR_SSEP2;
+ writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
- UHCHR &= ~UHCHR_SSEP1;
- UHCHR &= ~UHCHR_SSE;
+ writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
return 0;
}
int usb_cpu_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS);
udelay(10);
#if defined(CONFIG_CPU_MONAHANS)
- UHCHR |= UHCHR_SSEP0;
+ writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_PXA27X)
- UHCHR |= UHCHR_SSEP2;
+ writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
- UHCHR |= UHCHR_SSEP1;
- UHCHR |= UHCHR_SSE;
-
- return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
- UHCHR |= UHCHR_FHR;
- udelay(11);
- UHCHR &= ~UHCHR_FHR;
-
- UHCCOMS |= 1;
- udelay(10);
+ writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
#if defined(CONFIG_CPU_MONAHANS)
- UHCHR |= UHCHR_SSEP0;
+ /* Disable USB host clock. */
+ writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
+ udelay(100);
#endif
#if defined(CONFIG_PXA27X)
- UHCHR |= UHCHR_SSEP2;
+ /* Disable USB host clock. */
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
- UHCHR |= UHCHR_SSEP1;
- UHCHR |= UHCHR_SSE;
return 0;
}
+int usb_cpu_init_fail(void)
+{
+ return usb_cpu_stop();
+}
+
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
index 9f732a7..f5f80e0 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/include/asm/arch-at91/hardware.h
@@ -18,6 +18,7 @@
#if defined(CONFIG_AT91RM9200)
#include <asm/arch-at91/at91rm9200.h>
+#define AT91_PMC_UHP AT91RM9200_PMC_UHP
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#include <asm/arch/at91sam9260.h>
#define AT91_BASE_MCI AT91SAM9260_BASE_MCI
diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h
index 5a5aa11..a755212 100644
--- a/arch/arm/include/asm/arch-mx31/mx31.h
+++ b/arch/arm/include/asm/arch-mx31/mx31.h
@@ -27,6 +27,7 @@
extern u32 mx31_get_ipg_clk(void);
#define imx_get_uartclk mx31_get_ipg_clk
extern void mx31_gpio_mux(unsigned long mode);
+extern void mx31_set_pad(enum iomux_pins pin, u32 config);
void mx31_uart1_hw_init(void);
void mx31_spi2_hw_init(void);
diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h
index afd2728..afd2728 100644
--- a/arch/arm/include/asm/arch-mx51/asm-offsets.h
+++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h
diff --git a/arch/arm/include/asm/arch-mx51/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 1f8a537..1f8a537 100644
--- a/arch/arm/include/asm/arch-mx51/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
diff --git a/arch/arm/include/asm/arch-mx51/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 14aa231..14aa231 100644
--- a/arch/arm/include/asm/arch-mx51/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 3ddda40..3ddda40 100644
--- a/arch/arm/include/asm/arch-mx51/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
diff --git a/arch/arm/include/asm/arch-mx51/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
index a41c387..0d91a24 100644
--- a/arch/arm/include/asm/arch-mx51/iomux.h
+++ b/arch/arm/include/asm/arch-mx5/iomux.h
@@ -20,13 +20,13 @@
* MA 02111-1307 USA
*/
-#ifndef __MACH_MX51_IOMUX_H__
-#define __MACH_MX51_IOMUX_H__
+#ifndef __MACH_MX5_IOMUX_H__
+#define __MACH_MX5_IOMUX_H__
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
typedef unsigned int iomux_pin_name_t;
@@ -190,4 +190,4 @@ void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif /* __MACH_MX51_IOMUX_H__ */
+#endif /* __MACH_MX5_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
index b44ff25..a564fce 100644
--- a/arch/arm/include/asm/arch-mx51/mx51_pins.h
+++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
@@ -20,8 +20,8 @@
* MA 02111-1307 USA
*/
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
+#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
+#define __ASM_ARCH_MX5_MX5X_PINS_H__
#ifndef __ASSEMBLY__
@@ -415,4 +415,4 @@ enum iomux_pins {
};
#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
+#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index f687503..f687503 100644
--- a/arch/arm/include/asm/arch-mx51/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h
index c8c479a..44b800f 100644
--- a/arch/arm/include/asm/arch-pxa/hardware.h
+++ b/arch/arm/include/asm/arch-pxa/hardware.h
@@ -21,6 +21,19 @@
#include <linux/config.h>
#include <asm/mach-types.h>
+/*
+ * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
+ * PXA300/310/320 all have distinct register mappings in some cases, that's why
+ * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
+ * drivers and compatibility glue with old source then.
+ */
+#ifndef CONFIG_CPU_MONAHANS
+#if defined(CONFIG_CPU_PXA300) || \
+ defined(CONFIG_CPU_PXA310) || \
+ defined(CONFIG_CPU_PXA320)
+#define CONFIG_CPU_MONAHANS
+#endif
+#endif
/*
* These are statically mapped PCMCIA IO space for designs using it as a
@@ -51,54 +64,6 @@
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-
-#ifndef UBOOT_REG_FIX
-#ifndef __ASSEMBLY__
-
-#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
-#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
-
-/*
- * This __REG() version gives the same results as the one above, except
- * that we are fooling gcc somehow so it generates far better and smaller
- * assembly code for access to contigous registers. It's a shame that gcc
- * doesn't guess this by itself.
- */
-#include <asm/types.h>
-typedef struct { volatile u32 offset[4096]; } __regbase;
-# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
-# define __REG(x) __REGP(io_p2v(x))
-#endif
-
-/* Let's kick gcc's ass again... */
-# define __REG2(x,y) \
- ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
- : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
-
-# define __PREG(x) (io_v2p((u32)&(x)))
-
-#else
-
-# define __REG(x) io_p2v(x)
-# define __PREG(x) io_v2p(x)
-
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-# define io_p2v(PhAdd) (PhAdd)
-# define __REG(x) (*((volatile u32 *)io_p2v(x)))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-# define __REG(x) (x)
-# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */
-# define __REG_2(x) (x)
-# define __REG_3(x) (x)
-# endif
-# endif
-#endif /* UBOOT_REG_FIX */
-
#include "pxa-regs.h"
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
index 035a57e..85958dd 100644
--- a/arch/arm/include/asm/arch-pxa/macro.h
+++ b/arch/arm/include/asm/arch-pxa/macro.h
@@ -102,7 +102,11 @@
/*
* This macro sets up the Memory controller of the PXA2xx CPU
*
- * Clobbered regs: r3, r4, r5
+ * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
+ * and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
+ * use this regs for other purpose inside this macro.
+ *
+ * Clobbered regs: r3, r4, r5, r6, r7
*/
.macro pxa_mem_setup
/* This comes handy when setting MDREFR */
@@ -157,7 +161,7 @@
bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
ldr r4, =CONFIG_SYS_MDREFR_VAL
- mov r6, r4
+ mov r7, r4
lsl r4, #20
lsr r4, #20 /* Get a valid DRI field */
@@ -187,12 +191,12 @@
* 6) Initialize SDRAM
*/
- bic r6, #MDREFR_SLFRSH
- str r6, [r3, #MDREFR_OFFSET]
+ bic r7, #MDREFR_SLFRSH
+ str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
- orr r6, #MDREFR_E1PIN
- str r6, [r3, #MDREFR_OFFSET]
+ orr r7, #MDREFR_E1PIN
+ str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
/*
@@ -250,8 +254,8 @@
*/
ldr r4, [r3, #MDREFR_OFFSET]
- and r6, r6, #MDREFR_APD
- orr r4, r4, r6
+ and r7, r7, #MDREFR_APD
+ orr r4, r4, r7
str r4, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
.endm
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index d442fb0..65a387f 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -93,42 +93,42 @@ typedef void (*ExcpHndlr) (void) ;
/*
* DMA Controller
*/
-#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
-#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
-#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
-#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
-#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
-#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
-#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
-#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
-#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
-#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
-#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
-#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
-#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
-#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
-#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
-#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
-#ifdef CONFIG_CPU_MONAHANS
-#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */
-#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */
-#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */
-#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */
-#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */
-#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */
-#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */
-#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */
-#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */
-#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */
-#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */
-#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */
-#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */
-#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */
-#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */
-#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */
-#endif /* CONFIG_CPU_MONAHANS */
-
-#define DCSR(x) __REG2(0x40000000, (x) << 2)
+#define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
+#define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
+#define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
+#define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
+#define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
+#define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
+#define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */
+#define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */
+#define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */
+#define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */
+#define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */
+#define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */
+#define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */
+#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */
+#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */
+#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */
+#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */
+#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */
+#define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */
+#define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */
+#define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */
+#define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */
+#define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */
+#define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */
+#define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */
+#define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */
+#define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */
+#define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */
+#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */
+#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */
+#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+#define DCSR(x) (0x40000000 | ((x) << 2))
#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
@@ -150,52 +150,52 @@ typedef void (*ExcpHndlr) (void) ;
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
-#define DINT __REG(0x400000f0) /* DMA Interrupt Register */
-
-#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
-#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
-#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
-#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
-#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
-#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
-#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
-#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
-#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
-#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
-#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
-#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
-#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
-#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
-#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
-#define DRCMR15 __REG(0x4000013c) /* Reserved */
-#define DRCMR16 __REG(0x40000140) /* Reserved */
-#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
-#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
-#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
-#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
-#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
-#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
-#define DRCMR23 __REG(0x4000015c) /* Reserved */
-#define DRCMR24 __REG(0x40000160) /* Reserved */
-#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
-#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
-#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
-#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
-#define DRCMR29 __REG(0x40000174) /* Reserved */
-#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
-#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
-#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
-#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
-#define DRCMR34 __REG(0x40000188) /* Reserved */
-#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
-#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
-#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
-#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
-#define DRCMR39 __REG(0x4000019C) /* Reserved */
-
-#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
-#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
-#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
+#define DINT 0x400000f0 /* DMA Interrupt Register */
+
+#define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15 0x4000013c /* Reserved */
+#define DRCMR16 0x40000140 /* Reserved */
+#define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23 0x4000015c /* Reserved */
+#define DRCMR24 0x40000160 /* Reserved */
+#define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29 0x40000174 /* Reserved */
+#define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34 0x40000188 /* Reserved */
+#define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39 0x4000019C /* Reserved */
+
+#define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */
#define DRCMRRXSADR DRCMR2
#define DRCMRTXSADR DRCMR3
@@ -220,75 +220,75 @@ typedef void (*ExcpHndlr) (void) ;
#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
#define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
-#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
-#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
-#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
-#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
-#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
-#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
-#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
-#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
-#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
-#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
-#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
-#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
-#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
-#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
-#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
-#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
-#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
-#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
-#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
-#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
-#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
-#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
-#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
-#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
-#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
-#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
-#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
-#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
-#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
-#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
-#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
-#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
-#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
-#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
-#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
-#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
-#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
-#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
-#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
-#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
-#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
-#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
-#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
-#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
-#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
-#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
-#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
-#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
-#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
-#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
-#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
-#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
-#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
-#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
-#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
-#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
-#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
-#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
-#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
-#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
-#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
-#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
-#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
-#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
-
-#define DDADR(x) __REG2(0x40000200, (x) << 4)
-#define DSADR(x) __REG2(0x40000204, (x) << 4)
-#define DTADR(x) __REG2(0x40000208, (x) << 4)
-#define DCMD(x) __REG2(0x4000020c, (x) << 4)
+#define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */
+#define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */
+#define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */
+#define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */
+#define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */
+#define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */
+#define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */
+#define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */
+#define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */
+#define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */
+#define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */
+#define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */
+#define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */
+#define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */
+#define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */
+#define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */
+#define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */
+#define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */
+#define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */
+#define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */
+#define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */
+#define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */
+#define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */
+#define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */
+#define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */
+#define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */
+#define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */
+#define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */
+#define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */
+#define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */
+#define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */
+#define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */
+#define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */
+#define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */
+#define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */
+#define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */
+#define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */
+#define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */
+#define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */
+#define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */
+#define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */
+#define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */
+#define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */
+#define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */
+#define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */
+#define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */
+#define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */
+#define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x) (0x40000200 | ((x) << 4))
+#define DSADR(x) (0x40000204 | ((x) << 4))
+#define DTADR(x) (0x40000208 | ((x) << 4))
+#define DCMD(x) (0x4000020c | ((x) << 4))
#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
#define DDADR_STOP (1 << 0) /* Stop (read / write) */
@@ -313,56 +313,57 @@ typedef void (*ExcpHndlr) (void) ;
#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
+/******************************************************************************/
/*
* UARTs
*/
/* Full Function UART (FFUART) */
#define FFUART FFRBR
-#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
-#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
-#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
-#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
-#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
-#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
-#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
-#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
-#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
-#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
-#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
-#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
+#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
+#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
+#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
+#define FFFCR 0x40100008 /* FIFO Control Register (write only) */
+#define FFLCR 0x4010000C /* Line Control Register (read/write) */
+#define FFMCR 0x40100010 /* Modem Control Register (read/write) */
+#define FFLSR 0x40100014 /* Line Status Register (read only) */
+#define FFMSR 0x40100018 /* Modem Status Register (read only) */
+#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
+#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
+#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Bluetooth UART (BTUART) */
#define BTUART BTRBR
-#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
-#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
-#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
-#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
-#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
-#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
-#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
-#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
-#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
-#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
-#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
-#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
+#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
+#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
+#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
+#define BTFCR 0x40200008 /* FIFO Control Register (write only) */
+#define BTLCR 0x4020000C /* Line Control Register (read/write) */
+#define BTMCR 0x40200010 /* Modem Control Register (read/write) */
+#define BTLSR 0x40200014 /* Line Status Register (read only) */
+#define BTMSR 0x40200018 /* Modem Status Register (read only) */
+#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
+#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
+#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Standard UART (STUART) */
#define STUART STRBR
-#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
-#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
-#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
-#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
-#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
-#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
-#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
-#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
-#define STMSR __REG(0x40700018) /* Reserved */
-#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
-#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
-#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
+#define STRBR 0x40700000 /* Receive Buffer Register (read only) */
+#define STTHR 0x40700000 /* Transmit Holding Register (write only) */
+#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
+#define STIIR 0x40700008 /* Interrupt ID Register (read only) */
+#define STFCR 0x40700008 /* FIFO Control Register (write only) */
+#define STLCR 0x4070000C /* Line Control Register (read/write) */
+#define STMCR 0x40700010 /* Modem Control Register (read/write) */
+#define STLSR 0x40700014 /* Line Status Register (read only) */
+#define STMSR 0x40700018 /* Reserved */
+#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
+#define STISR 0x40700020 /* Infrared Selection Register (read/write) */
+#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE (1 << 6) /* UART Unit Enable */
@@ -408,7 +409,7 @@ typedef void (*ExcpHndlr) (void) ;
#define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */
-#define MCR_LOOP (1 << 4) */
+#define MCR_LOOP (1 << 4) /* */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */
@@ -423,6 +424,7 @@ typedef void (*ExcpHndlr) (void) ;
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
+/******************************************************************************/
/*
* IrSR (Infrared Selection Register)
*/
@@ -456,17 +458,25 @@ typedef void (*ExcpHndlr) (void) ;
/*
* I2C registers
*/
-#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
-#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
-#define ICR __REG(0x40301690) /* I2C Control Register - ICR */
-#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
-#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
-
-#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
-#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
-#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
-#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
-#define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */
+#define IBMR 0x40301680 /* I2C Bus Monitor Register - IBMR */
+#define IDBR 0x40301688 /* I2C Data Buffer Register - IDBR */
+#define ICR 0x40301690 /* I2C Control Register - ICR */
+#define ISR 0x40301698 /* I2C Status Register - ISR */
+#define ISAR 0x403016A0 /* I2C Slave Address Register - ISAR */
+
+#ifdef CONFIG_CPU_MONAHANS
+#define PWRIBMR 0x40f500C0 /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR 0x40f500C4 /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR 0x40f500C8 /* Power I2C Control Register - ICR */
+#define PWRISR 0x40f500CC /* Power I2C Status Register - ISR */
+#define PWRISAR 0x40f500D0 /* Power I2C Slave Address Register-ISAR */
+#else
+#define PWRIBMR 0x40f00180 /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR 0x40f00188 /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR 0x40f00190 /* Power I2C Control Register - ICR */
+#define PWRISR 0x40f00198 /* Power I2C Status Register - ISR */
+#define PWRISAR 0x40f001A0 /* Power I2C Slave Address Register-ISAR */
+#endif
/* ----- Control register bits ---------------------------------------- */
@@ -507,28 +517,27 @@ typedef void (*ExcpHndlr) (void) ;
/* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
* short defines because there is too much chance of namespace collision
*/
-/*#define SACR0 __REG(0x40400000) / Global Control Register */
-/*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */
-/*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
-/*#define SAIMR __REG(0x40400014) / Serial Audio Interrupt Mask Register */
-/*#define SAICR __REG(0x40400018) / Serial Audio Interrupt Clear Register */
-/*#define SADIV __REG(0x40400060) / Audio Clock Divider Register. */
-/*#define SADR __REG(0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */
-
+#define SACR0 0x40400000 /* Global Control Register */
+#define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */
+#define SAICR 0x40400018 /* Serial Audio Interrupt Clear Register */
+#define SADIV 0x40400060 /* Audio Clock Divider Register. */
+#define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */
/*
* AC97 Controller registers
*/
-#define POCR __REG(0x40500000) /* PCM Out Control Register */
+#define POCR 0x40500000 /* PCM Out Control Register */
#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define PICR __REG(0x40500004) /* PCM In Control Register */
+#define PICR 0x40500004 /* PCM In Control Register */
#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define MCCR __REG(0x40500008) /* Mic In Control Register */
+#define MCCR 0x40500008 /* Mic In Control Register */
#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
-#define GCR __REG(0x4050000C) /* Global Control Register */
+#define GCR 0x4050000C /* Global Control Register */
#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
@@ -540,16 +549,16 @@ typedef void (*ExcpHndlr) (void) ;
#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
-#define POSR __REG(0x40500010) /* PCM Out Status Register */
+#define POSR 0x40500010 /* PCM Out Status Register */
#define POSR_FIFOE (1 << 4) /* FIFO error */
-#define PISR __REG(0x40500014) /* PCM In Status Register */
+#define PISR 0x40500014 /* PCM In Status Register */
#define PISR_FIFOE (1 << 4) /* FIFO error */
-#define MCSR __REG(0x40500018) /* Mic In Status Register */
+#define MCSR 0x40500018 /* Mic In Status Register */
#define MCSR_FIFOE (1 << 4) /* FIFO error */
-#define GSR __REG(0x4050001C) /* Global Status Register */
+#define GSR 0x4050001C /* Global Status Register */
#define GSR_CDONE (1 << 19) /* Command Done */
#define GSR_SDONE (1 << 18) /* Status Done */
#define GSR_RDCS (1 << 15) /* Read Completion Status */
@@ -567,38 +576,38 @@ typedef void (*ExcpHndlr) (void) ;
#define GSR_MIINT (1 << 1) /* Modem In Interrupt */
#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
-#define CAR __REG(0x40500020) /* CODEC Access Register */
+#define CAR 0x40500020 /* CODEC Access Register */
#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
-#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
-#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
+#define PCDR 0x40500040 /* PCM FIFO Data Register */
+#define MCDR 0x40500060 /* Mic-in FIFO Data Register */
-#define MOCR __REG(0x40500100) /* Modem Out Control Register */
+#define MOCR 0x40500100 /* Modem Out Control Register */
#define MOCR_FEIE (1 << 3) /* FIFO Error */
-#define MICR __REG(0x40500108) /* Modem In Control Register */
+#define MICR 0x40500108 /* Modem In Control Register */
#define MICR_FEIE (1 << 3) /* FIFO Error */
-#define MOSR __REG(0x40500110) /* Modem Out Status Register */
+#define MOSR 0x40500110 /* Modem Out Status Register */
#define MOSR_FIFOE (1 << 4) /* FIFO error */
-#define MISR __REG(0x40500118) /* Modem In Status Register */
+#define MISR 0x40500118 /* Modem In Status Register */
#define MISR_FIFOE (1 << 4) /* FIFO error */
-#define MODR __REG(0x40500140) /* Modem FIFO Data Register */
+#define MODR 0x40500140 /* Modem FIFO Data Register */
-#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
-#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
-#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
-#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
+#define PAC_REG_BASE 0x40500200 /* Primary Audio Codec */
+#define SAC_REG_BASE 0x40500300 /* Secondary Audio Codec */
+#define PMC_REG_BASE 0x40500400 /* Primary Modem Codec */
+#define SMC_REG_BASE 0x40500500 /* Secondary Modem Codec */
/*
* USB Device Controller
*/
-#ifdef CONFIG_PXA27X
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define UDCCR __REG(0x40600000) /* UDC Control Register */
+#define UDCCR 0x40600000 /* UDC Control Register */
#define UDCCR_UDE (1 << 0) /* UDC enable */
#define UDCCR_UDA (1 << 1) /* UDC active */
#define UDCCR_RSM (1 << 2) /* Device resume */
@@ -623,7 +632,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */
#define UDCCR_AAISN_S 5
-#define UDCCS0 __REG(0x40600100) /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */
#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
#define UDCCS0_IPR (1 << 1) /* IN packet ready */
#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
@@ -634,9 +643,9 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCS0_SA (1 << 7) /* Setup active */
/* Bulk IN - Endpoint 1,6,11 */
-#define UDCCS1 __REG(0x40600104) /* UDC Endpoint 1 (IN) Control/Status Register */
-#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
-#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
+#define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */
#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
@@ -647,9 +656,9 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
/* Bulk OUT - Endpoint 2,7,12 */
-#define UDCCS2 __REG(0x40600108) /* UDC Endpoint 2 (OUT) Control/Status Register */
-#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
-#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
+#define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */
#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
@@ -660,9 +669,9 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
/* Isochronous IN - Endpoint 3,8,13 */
-#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
-#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
-#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
+#define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */
#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
@@ -671,9 +680,9 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
/* Isochronous OUT - Endpoint 4,9,14 */
-#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
-#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
-#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
+#define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */
#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
@@ -683,9 +692,9 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
/* Interrupt IN - Endpoint 5,10,15 */
-#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
-#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
-#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+#define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */
#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
@@ -695,32 +704,32 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCS_INT_FST (1 << 5) /* Force stall */
#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
-#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
-#define UFNRL __REG(0x40600014) /* UDC Frame Number Register Low */
-#define UBCR2 __REG(0x40600208) /* UDC Byte Count Reg 2 */
-#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
-#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
-#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
-#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
-#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
-#define UDDR0 __REG(0x40600300) /* UDC Endpoint 0 Data Register */
-#define UDDR1 __REG(0x40600304) /* UDC Endpoint 1 Data Register */
-#define UDDR2 __REG(0x40600308) /* UDC Endpoint 2 Data Register */
-#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
-#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
-#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
-#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
-#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
-#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
-#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
-#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
-#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
-#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
-#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
-#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
-#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
-
-#define UICR0 __REG(0x40600004) /* UDC Interrupt Control Register 0 */
+#define UFNRH 0x40600060 /* UDC Frame Number Register High */
+#define UFNRL 0x40600014 /* UDC Frame Number Register Low */
+#define UBCR2 0x40600208 /* UDC Byte Count Reg 2 */
+#define UBCR4 0x4060006c /* UDC Byte Count Reg 4 */
+#define UBCR7 0x40600070 /* UDC Byte Count Reg 7 */
+#define UBCR9 0x40600074 /* UDC Byte Count Reg 9 */
+#define UBCR12 0x40600078 /* UDC Byte Count Reg 12 */
+#define UBCR14 0x4060007c /* UDC Byte Count Reg 14 */
+#define UDDR0 0x40600300 /* UDC Endpoint 0 Data Register */
+#define UDDR1 0x40600304 /* UDC Endpoint 1 Data Register */
+#define UDDR2 0x40600308 /* UDC Endpoint 2 Data Register */
+#define UDDR3 0x40600200 /* UDC Endpoint 3 Data Register */
+#define UDDR4 0x40600400 /* UDC Endpoint 4 Data Register */
+#define UDDR5 0x406000A0 /* UDC Endpoint 5 Data Register */
+#define UDDR6 0x40600600 /* UDC Endpoint 6 Data Register */
+#define UDDR7 0x40600680 /* UDC Endpoint 7 Data Register */
+#define UDDR8 0x40600700 /* UDC Endpoint 8 Data Register */
+#define UDDR9 0x40600900 /* UDC Endpoint 9 Data Register */
+#define UDDR10 0x406000C0 /* UDC Endpoint 10 Data Register */
+#define UDDR11 0x40600B00 /* UDC Endpoint 11 Data Register */
+#define UDDR12 0x40600B80 /* UDC Endpoint 12 Data Register */
+#define UDDR13 0x40600C00 /* UDC Endpoint 13 Data Register */
+#define UDDR14 0x40600E00 /* UDC Endpoint 14 Data Register */
+#define UDDR15 0x406000E0 /* UDC Endpoint 15 Data Register */
+
+#define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */
#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
@@ -731,7 +740,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
-#define UICR1 __REG(0x40600008) /* UDC Interrupt Control Register 1 */
+#define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */
#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
@@ -742,7 +751,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
-#define USIR0 __REG(0x4060000C) /* UDC Status Interrupt Register 0 */
+#define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */
#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
#define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */
@@ -753,7 +762,7 @@ typedef void (*ExcpHndlr) (void) ;
#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
-#define USIR1 __REG(0x40600010) /* UDC Status Interrupt Register 1 */
+#define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */
#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
@@ -765,8 +774,8 @@ typedef void (*ExcpHndlr) (void) ;
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
-#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
-#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
+#define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */
+#define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
@@ -777,8 +786,8 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
-#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
-#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */
+#define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
@@ -787,8 +796,8 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
-#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
-#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCFNR 0x40600014 /* UDC Frame Number Register */
+#define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */
@@ -804,7 +813,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */
#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
-#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
@@ -815,29 +824,29 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
-#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
-#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
-#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
-#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
-#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
-#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
-#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
-#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
-#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
-#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
-#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
-#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
-#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
-#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
-#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
-#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
-#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
-#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
-#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
-#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
-#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
-#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
-#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+#define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
@@ -852,81 +861,81 @@ typedef void (*ExcpHndlr) (void) ;
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
-#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
-#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
-#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
-#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
-#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
-#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
-#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
-#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
-#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
-#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
-#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
-#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
-#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
-#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
-#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
-#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
-#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
-#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
-#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
-#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
-#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
-#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
-#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
-#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
+#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */
+#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */
+#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */
+#define UDCBCRC 0x4060020C /* Byte Count Register - EPC */
+#define UDCBCRD 0x40600210 /* Byte Count Register - EPD */
+#define UDCBCRE 0x40600214 /* Byte Count Register - EPE */
+#define UDCBCRF 0x40600218 /* Byte Count Register - EPF */
+#define UDCBCRG 0x4060021C /* Byte Count Register - EPG */
+#define UDCBCRH 0x40600220 /* Byte Count Register - EPH */
+#define UDCBCRI 0x40600224 /* Byte Count Register - EPI */
+#define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */
+#define UDCBCRK 0x4060022C /* Byte Count Register - EPK */
+#define UDCBCRL 0x40600230 /* Byte Count Register - EPL */
+#define UDCBCRM 0x40600234 /* Byte Count Register - EPM */
+#define UDCBCRN 0x40600238 /* Byte Count Register - EPN */
+#define UDCBCRP 0x4060023C /* Byte Count Register - EPP */
+#define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */
+#define UDCBCRR 0x40600244 /* Byte Count Register - EPR */
+#define UDCBCRS 0x40600248 /* Byte Count Register - EPS */
+#define UDCBCRT 0x4060024C /* Byte Count Register - EPT */
+#define UDCBCRU 0x40600250 /* Byte Count Register - EPU */
+#define UDCBCRV 0x40600254 /* Byte Count Register - EPV */
+#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */
+#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */
#define UDCDN(x) __REG2(0x40600300, (x)<<2)
-#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
-#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
-#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
-#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
-#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
-#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
-#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
-#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
-#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
-#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
-#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
-#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
-#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
-#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
-#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
-#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
-#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
-#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
-#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
-#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
-#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
-#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
-#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
-#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
+#define UDCDR0 0x40600300 /* Data Register - EP0 */
+#define UDCDRA 0x40600304 /* Data Register - EPA */
+#define UDCDRB 0x40600308 /* Data Register - EPB */
+#define UDCDRC 0x4060030C /* Data Register - EPC */
+#define UDCDRD 0x40600310 /* Data Register - EPD */
+#define UDCDRE 0x40600314 /* Data Register - EPE */
+#define UDCDRF 0x40600318 /* Data Register - EPF */
+#define UDCDRG 0x4060031C /* Data Register - EPG */
+#define UDCDRH 0x40600320 /* Data Register - EPH */
+#define UDCDRI 0x40600324 /* Data Register - EPI */
+#define UDCDRJ 0x40600328 /* Data Register - EPJ */
+#define UDCDRK 0x4060032C /* Data Register - EPK */
+#define UDCDRL 0x40600330 /* Data Register - EPL */
+#define UDCDRM 0x40600334 /* Data Register - EPM */
+#define UDCDRN 0x40600338 /* Data Register - EPN */
+#define UDCDRP 0x4060033C /* Data Register - EPP */
+#define UDCDRQ 0x40600340 /* Data Register - EPQ */
+#define UDCDRR 0x40600344 /* Data Register - EPR */
+#define UDCDRS 0x40600348 /* Data Register - EPS */
+#define UDCDRT 0x4060034C /* Data Register - EPT */
+#define UDCDRU 0x40600350 /* Data Register - EPU */
+#define UDCDRV 0x40600354 /* Data Register - EPV */
+#define UDCDRW 0x40600358 /* Data Register - EPW */
+#define UDCDRX 0x4060035C /* Data Register - EPX */
#define UDCCN(x) __REG2(0x40600400, (x)<<2)
-#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
-#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
-#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
-#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
-#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
-#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
-#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
-#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
-#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
-#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
-#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
-#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
-#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
-#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
-#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
-#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
-#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
-#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
-#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
-#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
-#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
-#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
-#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
+#define UDCCRA 0x40600404 /* Configuration register EPA */
+#define UDCCRB 0x40600408 /* Configuration register EPB */
+#define UDCCRC 0x4060040C /* Configuration register EPC */
+#define UDCCRD 0x40600410 /* Configuration register EPD */
+#define UDCCRE 0x40600414 /* Configuration register EPE */
+#define UDCCRF 0x40600418 /* Configuration register EPF */
+#define UDCCRG 0x4060041C /* Configuration register EPG */
+#define UDCCRH 0x40600420 /* Configuration register EPH */
+#define UDCCRI 0x40600424 /* Configuration register EPI */
+#define UDCCRJ 0x40600428 /* Configuration register EPJ */
+#define UDCCRK 0x4060042C /* Configuration register EPK */
+#define UDCCRL 0x40600430 /* Configuration register EPL */
+#define UDCCRM 0x40600434 /* Configuration register EPM */
+#define UDCCRN 0x40600438 /* Configuration register EPN */
+#define UDCCRP 0x4060043C /* Configuration register EPP */
+#define UDCCRQ 0x40600440 /* Configuration register EPQ */
+#define UDCCRR 0x40600444 /* Configuration register EPR */
+#define UDCCRS 0x40600448 /* Configuration register EPS */
+#define UDCCRT 0x4060044C /* Configuration register EPT */
+#define UDCCRU 0x40600450 /* Configuration register EPU */
+#define UDCCRV 0x40600454 /* Configuration register EPV */
+#define UDCCRW 0x40600458 /* Configuration register EPW */
+#define UDCCRX 0x4060045C /* Configuration register EPX */
#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
#define UDCCONR_CN_S (25)
@@ -959,38 +968,39 @@ typedef void (*ExcpHndlr) (void) ;
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+/******************************************************************************/
/*
* USB Host Controller
*/
#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
-#define UHCREV __REG(0x4C000000)
-#define UHCHCON __REG(0x4C000004)
-#define UHCCOMS __REG(0x4C000008)
-#define UHCINTS __REG(0x4C00000C)
-#define UHCINTE __REG(0x4C000010)
-#define UHCINTD __REG(0x4C000014)
-#define UHCHCCA __REG(0x4C000018)
-#define UHCPCED __REG(0x4C00001C)
-#define UHCCHED __REG(0x4C000020)
-#define UHCCCED __REG(0x4C000024)
-#define UHCBHED __REG(0x4C000028)
-#define UHCBCED __REG(0x4C00002C)
-#define UHCDHEAD __REG(0x4C000030)
-#define UHCFMI __REG(0x4C000034)
-#define UHCFMR __REG(0x4C000038)
-#define UHCFMN __REG(0x4C00003C)
-#define UHCPERS __REG(0x4C000040)
-#define UHCLST __REG(0x4C000044)
-#define UHCRHDA __REG(0x4C000048)
-#define UHCRHDB __REG(0x4C00004C)
-#define UHCRHS __REG(0x4C000050)
-#define UHCRHPS1 __REG(0x4C000054)
-#define UHCRHPS2 __REG(0x4C000058)
-#define UHCRHPS3 __REG(0x4C00005C)
-#define UHCSTAT __REG(0x4C000060)
-#define UHCHR __REG(0x4C000064)
-#define UHCHIE __REG(0x4C000068)
-#define UHCHIT __REG(0x4C00006C)
+#define UHCREV 0x4C000000
+#define UHCHCON 0x4C000004
+#define UHCCOMS 0x4C000008
+#define UHCINTS 0x4C00000C
+#define UHCINTE 0x4C000010
+#define UHCINTD 0x4C000014
+#define UHCHCCA 0x4C000018
+#define UHCPCED 0x4C00001C
+#define UHCCHED 0x4C000020
+#define UHCCCED 0x4C000024
+#define UHCBHED 0x4C000028
+#define UHCBCED 0x4C00002C
+#define UHCDHEAD 0x4C000030
+#define UHCFMI 0x4C000034
+#define UHCFMR 0x4C000038
+#define UHCFMN 0x4C00003C
+#define UHCPERS 0x4C000040
+#define UHCLST 0x4C000044
+#define UHCRHDA 0x4C000048
+#define UHCRHDB 0x4C00004C
+#define UHCRHS 0x4C000050
+#define UHCRHPS1 0x4C000054
+#define UHCRHPS2 0x4C000058
+#define UHCRHPS3 0x4C00005C
+#define UHCSTAT 0x4C000060
+#define UHCHR 0x4C000064
+#define UHCHIE 0x4C000068
+#define UHCHIT 0x4C00006C
#define UHCHR_FSBIR (1<<0)
#define UHCHR_FHR (1<<1)
@@ -1011,9 +1021,7 @@ typedef void (*ExcpHndlr) (void) ;
#define UHCHIE_HBAIE (1<<8)
#define UHCHIE_RWIE (1<<7)
-#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
-#define UP2OCR __REG(0x40600020)
-#endif
+#define UP2OCR 0x40600020
#define UP2OCR_HXOE (1<<17)
#define UP2OCR_HXS (1<<16)
@@ -1029,36 +1037,37 @@ typedef void (*ExcpHndlr) (void) ;
#define UP2OCR_CPVPE (1<<1)
#define UP2OCR_CPVEN (1<<0)
-#endif
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+/******************************************************************************/
/*
* Fast Infrared Communication Port
*/
-#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
-#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
-#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
-#define ICDR __REG(0x4080000c) /* ICP Data Register */
-#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
-#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
+#define ICCR0 0x40800000 /* ICP Control Register 0 */
+#define ICCR1 0x40800004 /* ICP Control Register 1 */
+#define ICCR2 0x40800008 /* ICP Control Register 2 */
+#define ICDR 0x4080000c /* ICP Data Register */
+#define ICSR0 0x40800014 /* ICP Status Register 0 */
+#define ICSR1 0x40800018 /* ICP Status Register 1 */
/*
* Real Time Clock
*/
-#define RCNR __REG(0x40900000) /* RTC Count Register */
-#define RTAR __REG(0x40900004) /* RTC Alarm Register */
-#define RTSR __REG(0x40900008) /* RTC Status Register */
-#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
-#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
-#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
-#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
-#define RDCR __REG(0x40900010) /* RTC Day Count Register. */
-#define RYCR __REG(0x40900014) /* RTC Year Count Register. */
-#define SWCR __REG(0x40900028) /* Stopwatch Count Register */
-#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
+#define RCNR 0x40900000 /* RTC Count Register */
+#define RTAR 0x40900004 /* RTC Alarm Register */
+#define RTSR 0x40900008 /* RTC Status Register */
+#define RTTR 0x4090000C /* RTC Timer Trim Register */
+#define RDAR1 0x40900018 /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2 0x40900020 /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1 0x4090001C /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2 0x40900024 /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1 0x4090002C /* Stopwatch Alarm Register 1 */
+#define SWAR2 0x40900030 /* Stopwatch Alarm Register 2 */
+#define PIAR 0x40900038 /* Periodic Interrupt Alarm Register */
+#define RDCR 0x40900010 /* RTC Day Count Register. */
+#define RYCR 0x40900014 /* RTC Year Count Register. */
+#define SWCR 0x40900028 /* Stopwatch Count Register */
+#define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */
#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
@@ -1068,48 +1077,48 @@ typedef void (*ExcpHndlr) (void) ;
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
#define RTSR_AL (1 << 0) /* RTC alarm detected */
+/******************************************************************************/
/*
* OS Timer & Match Registers
*/
-#define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */
-#define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */
-#define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */
-#define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */
-#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
-#define OSSR __REG(0x40A00014) /* OS Timer Status Register */
-#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
-#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
+#define OSMR0 0x40A00000 /* OS Timer Match Register 0 */
+#define OSMR1 0x40A00004 /* OS Timer Match Register 1 */
+#define OSMR2 0x40A00008 /* OS Timer Match Register 2 */
+#define OSMR3 0x40A0000C /* OS Timer Match Register 3 */
+#define OSCR 0x40A00010 /* OS Timer Counter Register */
+#define OSSR 0x40A00014 /* OS Timer Status Register */
+#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */
+#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */
-#ifdef CONFIG_CPU_MONAHANS
-#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */
-#define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */
-#define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */
-#define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */
-#define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */
-#define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */
-#define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */
-#define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */
-
-#define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */
-#define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */
-#define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */
-#define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */
-#define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */
-#define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */
-#define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */
-#define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */
-
-#define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */
-#define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */
-#define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */
-#define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */
-#define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */
-#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */
-#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
-#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
-
-#define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */
-#endif /* CONFIG_CPU_MONAHANS */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */
+#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */
+#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */
+#define OSCR7 0x40A0004C /* OS Timer Counter Register 7 */
+#define OSCR8 0x40A00050 /* OS Timer Counter Register 8 */
+#define OSCR9 0x40A00054 /* OS Timer Counter Register 9 */
+#define OSCR10 0x40A00058 /* OS Timer Counter Register 10 */
+#define OSCR11 0x40A0005C /* OS Timer Counter Register 11 */
+
+#define OSMR4 0x40A00080 /* OS Timer Match Register 4 */
+#define OSMR5 0x40A00084 /* OS Timer Match Register 5 */
+#define OSMR6 0x40A00088 /* OS Timer Match Register 6 */
+#define OSMR7 0x40A0008C /* OS Timer Match Register 7 */
+#define OSMR8 0x40A00090 /* OS Timer Match Register 8 */
+#define OSMR9 0x40A00094 /* OS Timer Match Register 9 */
+#define OSMR10 0x40A00098 /* OS Timer Match Register 10 */
+#define OSMR11 0x40A0009C /* OS Timer Match Register 11 */
+
+#define OMCR4 0x40A000C0 /* OS Match Control Register 4 */
+#define OMCR5 0x40A000C4 /* OS Match Control Register 5 */
+#define OMCR6 0x40A000C8 /* OS Match Control Register 6 */
+#define OMCR7 0x40A000CC /* OS Match Control Register 7 */
+#define OMCR8 0x40A000D0 /* OS Match Control Register 8 */
+#define OMCR9 0x40A000D4 /* OS Match Control Register 9 */
+#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */
+#define OMCR11 0x40A000DC /* OS Match Control Register 11 */
+
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
#define OSSR_M3 (1 << 3) /* Match status channel 3 */
@@ -1125,321 +1134,696 @@ typedef void (*ExcpHndlr) (void) ;
#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
+#define OSCR_CLK_FREQ 3250
+
+/******************************************************************************/
/*
- * Pulse Width Modulator
+ * Core Clock
*/
-#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
-#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
-#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
-#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
-#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
-#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
+#if defined(CONFIG_CPU_MONAHANS)
+#define ACCR 0x41340000 /* Application Subsystem Clock Configuration Register */
+#define ACSR 0x41340004 /* Application Subsystem Clock Status Register */
+#define AICSR 0x41340008 /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA 0x4134000C /* A Clock Enable Register */
+#define CKENB 0x41340010 /* B Clock Enable Register */
+#define AC97_DIV 0x41340014 /* AC97 clock divisor value register */
+
+#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
+#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
+#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
+#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
+#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
+#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
+#define ACCR_XPDIS (1 << 31)
+#define ACCR_SPDIS (1 << 30)
+#define ACCR_13MEND1 (1 << 27)
+#define ACCR_D0CS (1 << 26)
+#define ACCR_13MEND2 (1 << 21)
+#define ACCR_PCCE (1 << 11)
+
+#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
+#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
+#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
+#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
+#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
+#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
+#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
+#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
+#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
+#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
+#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
+#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
+#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
+#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
+#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
+#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
+#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
+#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
+#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
+#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
+
+#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
+#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
+#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
+#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
+
+#else /* if defined CONFIG_CPU_MONAHANS */
+
+#define CCCR 0x41300000 /* Core Clock Configuration Register */
+#define CKEN 0x41300004 /* Clock Enable Register */
+#define OSCC 0x41300008 /* Oscillator Configuration Register */
+#define CCSR 0x4130000C /* Core Clock Status Register */
+
+#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC (1 << 22) /* Memory Controler */
+#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
+#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
+#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
+#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
+#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
+
+#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#if !defined(CONFIG_PXA27X)
+#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
+#endif
+#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
+#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
+#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
+#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
+#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
+#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
+#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
+#if defined(CONFIG_PXA27X)
+#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
+#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
+#endif
+#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
+#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
+#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
+#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
+#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
+#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
+#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
+#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
+
+#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
+
+#if !defined(CONFIG_PXA27X)
+#define CCCR_L09 (0x1F)
+#define CCCR_L27 (0x1)
+#define CCCR_L32 (0x2)
+#define CCCR_L36 (0x3)
+#define CCCR_L40 (0x4)
+#define CCCR_L45 (0x5)
+
+#define CCCR_M1 (0x1 << 5)
+#define CCCR_M2 (0x2 << 5)
+#define CCCR_M4 (0x3 << 5)
-#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
-#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
-#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
+#define CCCR_N10 (0x2 << 7)
+#define CCCR_N15 (0x3 << 7)
+#define CCCR_N20 (0x4 << 7)
+#define CCCR_N25 (0x5 << 7)
+#define CCCR_N30 (0x6 << 7)
+#endif
-#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
-#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
-#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
+#endif /* CONFIG_CPU_MONAHANS */
+/******************************************************************************/
/*
- * Interrupt Controller
+ * Pulse Width Modulator
*/
-#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
-#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
-#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
-#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
-#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
-#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
+#define PWM_CTRL0 0x40B00000 /* PWM 0 Control Register */
+#define PWM_PWDUTY0 0x40B00004 /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0 0x40B00008 /* PWM 0 Period Control Register */
-#ifdef CONFIG_CPU_MONAHANS
-#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
-/* Missing: 32 Interrupt priority registers
- * These are the same as beneath for PXA27x: maybe can be merged if
- * GPIO Stuff is same too.
+#define PWM_CTRL1 0x40C00000 /* PWM 1 Control Register */
+#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */
+#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */
+#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+/*
+ * Interrupt Controller
*/
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-/* Missing: 2 Interrupt priority registers */
-#endif /* CONFIG_CPU_MONAHANS */
+#define ICIP 0x40D00000 /* Interrupt Controller IRQ Pending Register */
+#define ICMR 0x40D00004 /* Interrupt Controller Mask Register */
+#define ICLR 0x40D00008 /* Interrupt Controller Level Register */
+#define ICFP 0x40D0000C /* Interrupt Controller FIQ Pending Register */
+#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */
+#define ICCR 0x40D00014 /* Interrupt Controller Control Register */
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */
+#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */
+#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */
+#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
/*
* General Purpose I/O
*/
-#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
-#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
-#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
+#define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */
-#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
-#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
-#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
+#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */
-#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
-#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
-#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
+#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */
-#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
-#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
-#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
+#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */
-#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
-#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
-#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */
-#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
-#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */
-#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
-#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
-#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
+#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */
+#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */
+#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
#ifdef CONFIG_CPU_MONAHANS
-#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
-#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
-#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
-#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
-#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
-#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
-
-#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
-#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
-#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
-#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
-
-#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
-#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
-#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
-#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
-
-#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
-#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
-#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
-#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
-
-#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
-#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
-#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
-#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
-
-#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
-#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
-#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
-#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
-
-#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
-#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3)
-
-/* Multi-funktion Pin Registers, uncomplete, only:
- * - GPIO
- * - Data Flash DF_* pins defined.
+#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3)
+#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3)
+#endif
+
+#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3))
+#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3))
+#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3))
+#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3))
+#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3))
+#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3))
+#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3))
+#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2))
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
+#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
+#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
+#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
+#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
+#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
+#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
+#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \
+ ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
+#else
+#define GPLR(x) _GPLR(x)
+#define GPDR(x) _GPDR(x)
+#define GPSR(x) _GPSR(x)
+#define GPCR(x) _GPCR(x)
+#define GRER(x) _GRER(x)
+#define GFER(x) _GFER(x)
+#define GEDR(x) _GEDR(x)
+#define GAFR(x) _GAFR(x)
+#endif
+
+#define GPIO_bit(x) (1 << ((x) & 0x1f))
+
+/******************************************************************************/
+/*
+ * Multi-function Pin Registers:
*/
-#define GPIO0 __REG(0x40e10124)
-#define GPIO1 __REG(0x40e10128)
-#define GPIO2 __REG(0x40e1012c)
-#define GPIO3 __REG(0x40e10130)
-#define GPIO4 __REG(0x40e10134)
-#define nXCVREN __REG(0x40e10138)
-
-#define DF_CLE_NOE __REG(0x40e10204)
-#define DF_ALE_WE1 __REG(0x40e10208)
-
-#define DF_SCLK_E __REG(0x40e10210)
-#define nBE0 __REG(0x40e10214)
-#define nBE1 __REG(0x40e10218)
-#define DF_ALE_WE2 __REG(0x40e1021c)
-#define DF_INT_RnB __REG(0x40e10220)
-#define DF_nCS0 __REG(0x40e10224)
-#define DF_nCS1 __REG(0x40e10228)
-#define DF_nWE __REG(0x40e1022c)
-#define DF_nRE __REG(0x40e10230)
-#define nLUA __REG(0x40e10234)
-#define nLLA __REG(0x40e10238)
-#define DF_ADDR0 __REG(0x40e1023c)
-#define DF_ADDR1 __REG(0x40e10240)
-#define DF_ADDR2 __REG(0x40e10244)
-#define DF_ADDR3 __REG(0x40e10248)
-#define DF_IO0 __REG(0x40e1024c)
-#define DF_IO8 __REG(0x40e10250)
-#define DF_IO1 __REG(0x40e10254)
-#define DF_IO9 __REG(0x40e10258)
-#define DF_IO2 __REG(0x40e1025c)
-#define DF_IO10 __REG(0x40e10260)
-#define DF_IO3 __REG(0x40e10264)
-#define DF_IO11 __REG(0x40e10268)
-#define DF_IO4 __REG(0x40e1026c)
-#define DF_IO12 __REG(0x40e10270)
-#define DF_IO5 __REG(0x40e10274)
-#define DF_IO13 __REG(0x40e10278)
-#define DF_IO6 __REG(0x40e1027c)
-#define DF_IO14 __REG(0x40e10280)
-#define DF_IO7 __REG(0x40e10284)
-#define DF_IO15 __REG(0x40e10288)
-
-#define GPIO5 __REG(0x40e1028c)
-#define GPIO6 __REG(0x40e10290)
-#define GPIO7 __REG(0x40e10294)
-#define GPIO8 __REG(0x40e10298)
-#define GPIO9 __REG(0x40e1029c)
-
-#define GPIO11 __REG(0x40e102a0)
-#define GPIO12 __REG(0x40e102a4)
-#define GPIO13 __REG(0x40e102a8)
-#define GPIO14 __REG(0x40e102ac)
-#define GPIO15 __REG(0x40e102b0)
-#define GPIO16 __REG(0x40e102b4)
-#define GPIO17 __REG(0x40e102b8)
-#define GPIO18 __REG(0x40e102bc)
-#define GPIO19 __REG(0x40e102c0)
-#define GPIO20 __REG(0x40e102c4)
-#define GPIO21 __REG(0x40e102c8)
-#define GPIO22 __REG(0x40e102cc)
-#define GPIO23 __REG(0x40e102d0)
-#define GPIO24 __REG(0x40e102d4)
-#define GPIO25 __REG(0x40e102d8)
-#define GPIO26 __REG(0x40e102dc)
-
-#define GPIO27 __REG(0x40e10400)
-#define GPIO28 __REG(0x40e10404)
-#define GPIO29 __REG(0x40e10408)
-#define GPIO30 __REG(0x40e1040c)
-#define GPIO31 __REG(0x40e10410)
-#define GPIO32 __REG(0x40e10414)
-#define GPIO33 __REG(0x40e10418)
-#define GPIO34 __REG(0x40e1041c)
-#define GPIO35 __REG(0x40e10420)
-#define GPIO36 __REG(0x40e10424)
-#define GPIO37 __REG(0x40e10428)
-#define GPIO38 __REG(0x40e1042c)
-#define GPIO39 __REG(0x40e10430)
-#define GPIO40 __REG(0x40e10434)
-#define GPIO41 __REG(0x40e10438)
-#define GPIO42 __REG(0x40e1043c)
-#define GPIO43 __REG(0x40e10440)
-#define GPIO44 __REG(0x40e10444)
-#define GPIO45 __REG(0x40e10448)
-#define GPIO46 __REG(0x40e1044c)
-#define GPIO47 __REG(0x40e10450)
-#define GPIO48 __REG(0x40e10454)
-
-#define GPIO10 __REG(0x40e10458)
-
-#define GPIO49 __REG(0x40e1045c)
-#define GPIO50 __REG(0x40e10460)
-#define GPIO51 __REG(0x40e10464)
-#define GPIO52 __REG(0x40e10468)
-#define GPIO53 __REG(0x40e1046c)
-#define GPIO54 __REG(0x40e10470)
-#define GPIO55 __REG(0x40e10474)
-#define GPIO56 __REG(0x40e10478)
-#define GPIO57 __REG(0x40e1047c)
-#define GPIO58 __REG(0x40e10480)
-#define GPIO59 __REG(0x40e10484)
-#define GPIO60 __REG(0x40e10488)
-#define GPIO61 __REG(0x40e1048c)
-#define GPIO62 __REG(0x40e10490)
-
-#define GPIO6_2 __REG(0x40e10494)
-#define GPIO7_2 __REG(0x40e10498)
-#define GPIO8_2 __REG(0x40e1049c)
-#define GPIO9_2 __REG(0x40e104a0)
-#define GPIO10_2 __REG(0x40e104a4)
-#define GPIO11_2 __REG(0x40e104a8)
-#define GPIO12_2 __REG(0x40e104ac)
-#define GPIO13_2 __REG(0x40e104b0)
-
-#define GPIO63 __REG(0x40e104b4)
-#define GPIO64 __REG(0x40e104b8)
-#define GPIO65 __REG(0x40e104bc)
-#define GPIO66 __REG(0x40e104c0)
-#define GPIO67 __REG(0x40e104c4)
-#define GPIO68 __REG(0x40e104c8)
-#define GPIO69 __REG(0x40e104cc)
-#define GPIO70 __REG(0x40e104d0)
-#define GPIO71 __REG(0x40e104d4)
-#define GPIO72 __REG(0x40e104d8)
-#define GPIO73 __REG(0x40e104dc)
-
-#define GPIO14_2 __REG(0x40e104e0)
-#define GPIO15_2 __REG(0x40e104e4)
-#define GPIO16_2 __REG(0x40e104e8)
-#define GPIO17_2 __REG(0x40e104ec)
-
-#define GPIO74 __REG(0x40e104f0)
-#define GPIO75 __REG(0x40e104f4)
-#define GPIO76 __REG(0x40e104f8)
-#define GPIO77 __REG(0x40e104fc)
-#define GPIO78 __REG(0x40e10500)
-#define GPIO79 __REG(0x40e10504)
-#define GPIO80 __REG(0x40e10508)
-#define GPIO81 __REG(0x40e1050c)
-#define GPIO82 __REG(0x40e10510)
-#define GPIO83 __REG(0x40e10514)
-#define GPIO84 __REG(0x40e10518)
-#define GPIO85 __REG(0x40e1051c)
-#define GPIO86 __REG(0x40e10520)
-#define GPIO87 __REG(0x40e10524)
-#define GPIO88 __REG(0x40e10528)
-#define GPIO89 __REG(0x40e1052c)
-#define GPIO90 __REG(0x40e10530)
-#define GPIO91 __REG(0x40e10534)
-#define GPIO92 __REG(0x40e10538)
-#define GPIO93 __REG(0x40e1053c)
-#define GPIO94 __REG(0x40e10540)
-#define GPIO95 __REG(0x40e10544)
-#define GPIO96 __REG(0x40e10548)
-#define GPIO97 __REG(0x40e1054c)
-#define GPIO98 __REG(0x40e10550)
-
-#define GPIO99 __REG(0x40e10600)
-#define GPIO100 __REG(0x40e10604)
-#define GPIO101 __REG(0x40e10608)
-#define GPIO102 __REG(0x40e1060c)
-#define GPIO103 __REG(0x40e10610)
-#define GPIO104 __REG(0x40e10614)
-#define GPIO105 __REG(0x40e10618)
-#define GPIO106 __REG(0x40e1061c)
-#define GPIO107 __REG(0x40e10620)
-#define GPIO108 __REG(0x40e10624)
-#define GPIO109 __REG(0x40e10628)
-#define GPIO110 __REG(0x40e1062c)
-#define GPIO111 __REG(0x40e10630)
-#define GPIO112 __REG(0x40e10634)
-
-#define GPIO113 __REG(0x40e10638)
-#define GPIO114 __REG(0x40e1063c)
-#define GPIO115 __REG(0x40e10640)
-#define GPIO116 __REG(0x40e10644)
-#define GPIO117 __REG(0x40e10648)
-#define GPIO118 __REG(0x40e1064c)
-#define GPIO119 __REG(0x40e10650)
-#define GPIO120 __REG(0x40e10654)
-#define GPIO121 __REG(0x40e10658)
-#define GPIO122 __REG(0x40e1065c)
-#define GPIO123 __REG(0x40e10660)
-#define GPIO124 __REG(0x40e10664)
-#define GPIO125 __REG(0x40e10668)
-#define GPIO126 __REG(0x40e1066c)
-#define GPIO127 __REG(0x40e10670)
-
-#define GPIO0_2 __REG(0x40e10674)
-#define GPIO1_2 __REG(0x40e10678)
-#define GPIO2_2 __REG(0x40e1067c)
-#define GPIO3_2 __REG(0x40e10680)
-#define GPIO4_2 __REG(0x40e10684)
-#define GPIO5_2 __REG(0x40e10688)
+/* PXA320 */
+#if defined(CONFIG_CPU_PXA320)
+#define DF_IO0 0x40e1024c
+#define DF_IO1 0x40e10254
+#define DF_IO2 0x40e1025c
+#define DF_IO3 0x40e10264
+#define DF_IO4 0x40e1026c
+#define DF_IO5 0x40e10274
+#define DF_IO6 0x40e1027c
+#define DF_IO7 0x40e10284
+#define DF_IO8 0x40e10250
+#define DF_IO9 0x40e10258
+#define DF_IO10 0x40e10260
+#define DF_IO11 0x40e10268
+#define DF_IO12 0x40e10270
+#define DF_IO13 0x40e10278
+#define DF_IO14 0x40e10280
+#define DF_IO15 0x40e10288
+#define DF_CLE_nOE 0x40e10204
+#define DF_ALE_nWE1 0x40e10208
+#define DF_ALE_nWE2 0x40e1021c
+#define DF_SCLK_E 0x40e10210
+#define DF_nCS0 0x40e10224
+#define DF_nCS1 0x40e10228
+#define nBE0 0x40e10214
+#define nBE1 0x40e10218
+#define nLUA 0x40e10234
+#define nLLA 0x40e10238
+#define DF_ADDR0 0x40e1023c
+#define DF_ADDR1 0x40e10240
+#define DF_ADDR2 0x40e10244
+#define DF_ADDR3 0x40e10248
+#define DF_INT_RnB 0x40e10220
+#define DF_nCS0 0x40e10224
+#define DF_nCS1 0x40e10228
+#define DF_nWE 0x40e1022c
+#define DF_nRE 0x40e10230
+
+#define nXCVREN 0x40e10138
+
+#define GPIO0 0x40e10124
+#define GPIO1 0x40e10128
+#define GPIO2 0x40e1012c
+#define GPIO3 0x40e10130
+#define GPIO4 0x40e10134
+#define GPIO5 0x40e1028c
+#define GPIO6 0x40e10290
+#define GPIO7 0x40e10294
+#define GPIO8 0x40e10298
+#define GPIO9 0x40e1029c
+#define GPIO10 0x40e10458
+#define GPIO11 0x40e102a0
+#define GPIO12 0x40e102a4
+#define GPIO13 0x40e102a8
+#define GPIO14 0x40e102ac
+#define GPIO15 0x40e102b0
+#define GPIO16 0x40e102b4
+#define GPIO17 0x40e102b8
+#define GPIO18 0x40e102bc
+#define GPIO19 0x40e102c0
+#define GPIO20 0x40e102c4
+#define GPIO21 0x40e102c8
+#define GPIO22 0x40e102cc
+#define GPIO23 0x40e102d0
+#define GPIO24 0x40e102d4
+#define GPIO25 0x40e102d8
+#define GPIO26 0x40e102dc
+
+#define GPIO27 0x40e10400
+#define GPIO28 0x40e10404
+#define GPIO29 0x40e10408
+#define GPIO30 0x40e1040c
+#define GPIO31 0x40e10410
+#define GPIO32 0x40e10414
+#define GPIO33 0x40e10418
+#define GPIO34 0x40e1041c
+#define GPIO35 0x40e10420
+#define GPIO36 0x40e10424
+#define GPIO37 0x40e10428
+#define GPIO38 0x40e1042c
+#define GPIO39 0x40e10430
+#define GPIO40 0x40e10434
+#define GPIO41 0x40e10438
+#define GPIO42 0x40e1043c
+#define GPIO43 0x40e10440
+#define GPIO44 0x40e10444
+#define GPIO45 0x40e10448
+#define GPIO46 0x40e1044c
+#define GPIO47 0x40e10450
+#define GPIO48 0x40e10454
+#define GPIO49 0x40e1045c
+#define GPIO50 0x40e10460
+#define GPIO51 0x40e10464
+#define GPIO52 0x40e10468
+#define GPIO53 0x40e1046c
+#define GPIO54 0x40e10470
+#define GPIO55 0x40e10474
+#define GPIO56 0x40e10478
+#define GPIO57 0x40e1047c
+#define GPIO58 0x40e10480
+#define GPIO59 0x40e10484
+#define GPIO60 0x40e10488
+#define GPIO61 0x40e1048c
+#define GPIO62 0x40e10490
+
+#define GPIO6_2 0x40e10494
+#define GPIO7_2 0x40e10498
+#define GPIO8_2 0x40e1049c
+#define GPIO9_2 0x40e104a0
+#define GPIO10_2 0x40e104a4
+#define GPIO11_2 0x40e104a8
+#define GPIO12_2 0x40e104ac
+#define GPIO13_2 0x40e104b0
+
+#define GPIO63 0x40e104b4
+#define GPIO64 0x40e104b8
+#define GPIO65 0x40e104bc
+#define GPIO66 0x40e104c0
+#define GPIO67 0x40e104c4
+#define GPIO68 0x40e104c8
+#define GPIO69 0x40e104cc
+#define GPIO70 0x40e104d0
+#define GPIO71 0x40e104d4
+#define GPIO72 0x40e104d8
+#define GPIO73 0x40e104dc
+
+#define GPIO14_2 0x40e104e0
+#define GPIO15_2 0x40e104e4
+#define GPIO16_2 0x40e104e8
+#define GPIO17_2 0x40e104ec
+
+#define GPIO74 0x40e104f0
+#define GPIO75 0x40e104f4
+#define GPIO76 0x40e104f8
+#define GPIO77 0x40e104fc
+#define GPIO78 0x40e10500
+#define GPIO79 0x40e10504
+#define GPIO80 0x40e10508
+#define GPIO81 0x40e1050c
+#define GPIO82 0x40e10510
+#define GPIO83 0x40e10514
+#define GPIO84 0x40e10518
+#define GPIO85 0x40e1051c
+#define GPIO86 0x40e10520
+#define GPIO87 0x40e10524
+#define GPIO88 0x40e10528
+#define GPIO89 0x40e1052c
+#define GPIO90 0x40e10530
+#define GPIO91 0x40e10534
+#define GPIO92 0x40e10538
+#define GPIO93 0x40e1053c
+#define GPIO94 0x40e10540
+#define GPIO95 0x40e10544
+#define GPIO96 0x40e10548
+#define GPIO97 0x40e1054c
+#define GPIO98 0x40e10550
+
+#define GPIO99 0x40e10600
+#define GPIO100 0x40e10604
+#define GPIO101 0x40e10608
+#define GPIO102 0x40e1060c
+#define GPIO103 0x40e10610
+#define GPIO104 0x40e10614
+#define GPIO105 0x40e10618
+#define GPIO106 0x40e1061c
+#define GPIO107 0x40e10620
+#define GPIO108 0x40e10624
+#define GPIO109 0x40e10628
+#define GPIO110 0x40e1062c
+#define GPIO111 0x40e10630
+#define GPIO112 0x40e10634
+
+#define GPIO113 0x40e10638
+#define GPIO114 0x40e1063c
+#define GPIO115 0x40e10640
+#define GPIO116 0x40e10644
+#define GPIO117 0x40e10648
+#define GPIO118 0x40e1064c
+#define GPIO119 0x40e10650
+#define GPIO120 0x40e10654
+#define GPIO121 0x40e10658
+#define GPIO122 0x40e1065c
+#define GPIO123 0x40e10660
+#define GPIO124 0x40e10664
+#define GPIO125 0x40e10668
+#define GPIO126 0x40e1066c
+#define GPIO127 0x40e10670
+
+#define GPIO0_2 0x40e10674
+#define GPIO1_2 0x40e10678
+#define GPIO2_2 0x40e1067c
+#define GPIO3_2 0x40e10680
+#define GPIO4_2 0x40e10684
+#define GPIO5_2 0x40e10688
+
+/* PXA300 and PXA310 */
+#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
+#define DF_IO0 0x40e10220
+#define DF_IO1 0x40e10228
+#define DF_IO2 0x40e10230
+#define DF_IO3 0x40e10238
+#define DF_IO4 0x40e10258
+#define DF_IO5 0x40e10260
+#define DF_IO7 0x40e10270
+#define DF_IO6 0x40e10268
+#define DF_IO8 0x40e10224
+#define DF_IO9 0x40e1022c
+#define DF_IO10 0x40e10234
+#define DF_IO11 0x40e1023c
+#define DF_IO12 0x40e1025c
+#define DF_IO13 0x40e10264
+#define DF_IO14 0x40e1026c
+#define DF_IO15 0x40e10274
+#define DF_CLE_NOE 0x40e10240
+#define DF_ALE_nWE 0x40e1020c
+#define DF_SCLK_E 0x40e10250
+#define nCS0 0x40e100c4
+#define nCS1 0x40e100c0
+#define nBE0 0x40e10204
+#define nBE1 0x40e10208
+#define nLUA 0x40e10244
+#define nLLA 0x40e10254
+#define DF_ADDR0 0x40e10210
+#define DF_ADDR1 0x40e10214
+#define DF_ADDR2 0x40e10218
+#define DF_ADDR3 0x40e1021c
+#define DF_INT_RnB 0x40e100c8
+#define DF_nCS0 0x40e10248
+#define DF_nCS1 0x40e10278
+#define DF_nWE 0x40e100cc
+#define DF_nRE 0x40e10200
+
+#define GPIO0 0x40e100b4
+#define GPIO1 0x40e100b8
+#define GPIO2 0x40e100bc
+#define GPIO3 0x40e1027c
+#define GPIO4 0x40e10280
+
+#define GPIO5 0x40e10284
+#define GPIO6 0x40e10288
+#define GPIO7 0x40e1028c
+#define GPIO8 0x40e10290
+#define GPIO9 0x40e10294
+#define GPIO10 0x40e10298
+#define GPIO11 0x40e1029c
+#define GPIO12 0x40e102a0
+#define GPIO13 0x40e102a4
+#define GPIO14 0x40e102a8
+#define GPIO15 0x40e102ac
+#define GPIO16 0x40e102b0
+#define GPIO17 0x40e102b4
+#define GPIO18 0x40e102b8
+#define GPIO19 0x40e102bc
+#define GPIO20 0x40e102c0
+#define GPIO21 0x40e102c4
+#define GPIO22 0x40e102c8
+#define GPIO23 0x40e102cc
+#define GPIO24 0x40e102d0
+#define GPIO25 0x40e102d4
+#define GPIO26 0x40e102d8
+
+#define GPIO27 0x40e10400
+#define GPIO28 0x40e10404
+#define GPIO29 0x40e10408
+#define ULPI_STP 0x40e1040c
+#define ULPI_NXT 0x40e10410
+#define ULPI_DIR 0x40e10414
+#define GPIO30 0x40e10418
+#define GPIO31 0x40e1041c
+#define GPIO32 0x40e10420
+#define GPIO33 0x40e10424
+#define GPIO34 0x40e10428
+#define GPIO35 0x40e1042c
+#define GPIO36 0x40e10430
+#define GPIO37 0x40e10434
+#define GPIO38 0x40e10438
+#define GPIO39 0x40e1043c
+#define GPIO40 0x40e10440
+#define GPIO41 0x40e10444
+#define GPIO42 0x40e10448
+#define GPIO43 0x40e1044c
+#define GPIO44 0x40e10450
+#define GPIO45 0x40e10454
+#define GPIO46 0x40e10458
+#define GPIO47 0x40e1045c
+#define GPIO48 0x40e10460
+
+#define GPIO49 0x40e10464
+#define GPIO50 0x40e10468
+#define GPIO51 0x40e1046c
+#define GPIO52 0x40e10470
+#define GPIO53 0x40e10474
+#define GPIO54 0x40e10478
+#define GPIO55 0x40e1047c
+#define GPIO56 0x40e10480
+#define GPIO57 0x40e10484
+#define GPIO58 0x40e10488
+#define GPIO59 0x40e1048c
+#define GPIO60 0x40e10490
+#define GPIO61 0x40e10494
+#define GPIO62 0x40e10498
+#define GPIO63 0x40e1049c
+#define GPIO64 0x40e104a0
+#define GPIO65 0x40e104a4
+#define GPIO66 0x40e104a8
+#define GPIO67 0x40e104ac
+#define GPIO68 0x40e104b0
+#define GPIO69 0x40e104b4
+#define GPIO70 0x40e104b8
+#define GPIO71 0x40e104bc
+#define GPIO72 0x40e104c0
+#define GPIO73 0x40e104c4
+#define GPIO74 0x40e104c8
+#define GPIO75 0x40e104cc
+#define GPIO76 0x40e104d0
+#define GPIO77 0x40e104d4
+#define GPIO78 0x40e104d8
+#define GPIO79 0x40e104dc
+#define GPIO80 0x40e104e0
+#define GPIO81 0x40e104e4
+#define GPIO82 0x40e104e8
+#define GPIO83 0x40e104ec
+#define GPIO84 0x40e104f0
+#define GPIO85 0x40e104f4
+#define GPIO86 0x40e104f8
+#define GPIO87 0x40e104fc
+#define GPIO88 0x40e10500
+#define GPIO89 0x40e10504
+#define GPIO90 0x40e10508
+#define GPIO91 0x40e1050c
+#define GPIO92 0x40e10510
+#define GPIO93 0x40e10514
+#define GPIO94 0x40e10518
+#define GPIO95 0x40e1051c
+#define GPIO96 0x40e10520
+#define GPIO97 0x40e10524
+#define GPIO98 0x40e10528
+
+#define GPIO99 0x40e10600
+#define GPIO100 0x40e10604
+#define GPIO101 0x40e10608
+#define GPIO102 0x40e1060c
+#define GPIO103 0x40e10610
+#define GPIO104 0x40e10614
+#define GPIO105 0x40e10618
+#define GPIO106 0x40e1061c
+#define GPIO107 0x40e10620
+#define GPIO108 0x40e10624
+#define GPIO109 0x40e10628
+#define GPIO110 0x40e1062c
+#define GPIO111 0x40e10630
+#define GPIO112 0x40e10634
+
+#define GPIO113 0x40e10638
+#define GPIO114 0x40e1063c
+#define GPIO115 0x40e10640
+#define GPIO116 0x40e10644
+#define GPIO117 0x40e10648
+#define GPIO118 0x40e1064c
+#define GPIO119 0x40e10650
+#define GPIO120 0x40e10654
+#define GPIO121 0x40e10658
+#define GPIO122 0x40e1065c
+#define GPIO123 0x40e10660
+#define GPIO124 0x40e10664
+#define GPIO125 0x40e10668
+#define GPIO126 0x40e1066c
+#define GPIO127 0x40e10670
+
+#define GPIO0_2 0x40e10674
+#define GPIO1_2 0x40e10678
+#define GPIO2_2 0x40e102dc
+#define GPIO3_2 0x40e102e0
+#define GPIO4_2 0x40e102e4
+#define GPIO5_2 0x40e102e8
+#define GPIO6_2 0x40e102ec
+
+#ifndef CONFIG_CPU_PXA300 /* PXA310 only */
+#define GPIO7_2 0x40e1052c
+#define GPIO8_2 0x40e10530
+#define GPIO9_2 0x40e10534
+#define GPIO10_2 0x40e10538
+#endif
+#endif
+#ifdef CONFIG_CPU_MONAHANS
/* MFPR Bit Definitions, see 4-10, Vol. 1 */
#define PULL_SEL 0x8000
#define PULLUP_EN 0x4000
@@ -1470,62 +1854,8 @@ typedef void (*ExcpHndlr) (void) ;
#define AF_SEL_6 0x6 /* Alternate function 6 */
#define AF_SEL_7 0x7 /* Alternate function 7 */
-
-#else /* CONFIG_CPU_MONAHANS */
-
-#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
-#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
-#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
-#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
-#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
-#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
#endif /* CONFIG_CPU_MONAHANS */
-/* More handy macros. The argument is a literal GPIO number. */
-
-#define GPIO_bit(x) (1 << ((x) & 0x1f))
-
-#ifdef CONFIG_PXA27X
-
-/* Interrupt Controller */
-
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-
-#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
-#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
-#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
-#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
-#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
-#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
-#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
-#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
- ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
-#else
-
-#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
-#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
-#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
-#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
-#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
-#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
-#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
-#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-
-#endif
-
/* GPIO alternate function assignments */
#define GPIO1_RST 1 /* reset */
@@ -1732,63 +2062,63 @@ typedef void (*ExcpHndlr) (void) ;
*/
#ifdef CONFIG_CPU_MONAHANS
-#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */
-#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */
-#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */
-#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */
-#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */
-#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */
-#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */
-#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */
-#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */
-#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */
-#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */
-#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */
-#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */
-#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */
-
-#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
-#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
-#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
-#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
-#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
-#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
-#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
-#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
-#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
-#define PCMD(x) __REG(0x40F50110 + x*4)
-#define PCMD0 __REG(0x40F50110 + 0 * 4)
-#define PCMD1 __REG(0x40F50110 + 1 * 4)
-#define PCMD2 __REG(0x40F50110 + 2 * 4)
-#define PCMD3 __REG(0x40F50110 + 3 * 4)
-#define PCMD4 __REG(0x40F50110 + 4 * 4)
-#define PCMD5 __REG(0x40F50110 + 5 * 4)
-#define PCMD6 __REG(0x40F50110 + 6 * 4)
-#define PCMD7 __REG(0x40F50110 + 7 * 4)
-#define PCMD8 __REG(0x40F50110 + 8 * 4)
-#define PCMD9 __REG(0x40F50110 + 9 * 4)
-#define PCMD10 __REG(0x40F50110 + 10 * 4)
-#define PCMD11 __REG(0x40F50110 + 11 * 4)
-#define PCMD12 __REG(0x40F50110 + 12 * 4)
-#define PCMD13 __REG(0x40F50110 + 13 * 4)
-#define PCMD14 __REG(0x40F50110 + 14 * 4)
-#define PCMD15 __REG(0x40F50110 + 15 * 4)
-#define PCMD16 __REG(0x40F50110 + 16 * 4)
-#define PCMD17 __REG(0x40F50110 + 17 * 4)
-#define PCMD18 __REG(0x40F50110 + 18 * 4)
-#define PCMD19 __REG(0x40F50110 + 19 * 4)
-#define PCMD20 __REG(0x40F50110 + 20 * 4)
-#define PCMD21 __REG(0x40F50110 + 21 * 4)
-#define PCMD22 __REG(0x40F50110 + 22 * 4)
-#define PCMD23 __REG(0x40F50110 + 23 * 4)
-#define PCMD24 __REG(0x40F50110 + 24 * 4)
-#define PCMD25 __REG(0x40F50110 + 25 * 4)
-#define PCMD26 __REG(0x40F50110 + 26 * 4)
-#define PCMD27 __REG(0x40F50110 + 27 * 4)
-#define PCMD28 __REG(0x40F50110 + 28 * 4)
-#define PCMD29 __REG(0x40F50110 + 29 * 4)
-#define PCMD30 __REG(0x40F50110 + 30 * 4)
-#define PCMD31 __REG(0x40F50110 + 31 * 4)
+#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */
+#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */
+#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */
+#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */
+#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */
+#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */
+#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */
+#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */
+#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */
+#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */
+#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */
+#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */
+#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */
+#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */
+
+#define PMCR 0x40F50000 /* Power Manager Control Register */
+#define PSR 0x40F50004 /* Power Manager S2 Status Register */
+#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */
+#define PCFR 0x40F5000C /* Power Manager General Configuration Register */
+#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */
+#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */
+#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */
+#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */
+#define PCMD(x) (0x40F50110 + x*4)
+#define PCMD0 (0x40F50110 + 0 * 4)
+#define PCMD1 (0x40F50110 + 1 * 4)
+#define PCMD2 (0x40F50110 + 2 * 4)
+#define PCMD3 (0x40F50110 + 3 * 4)
+#define PCMD4 (0x40F50110 + 4 * 4)
+#define PCMD5 (0x40F50110 + 5 * 4)
+#define PCMD6 (0x40F50110 + 6 * 4)
+#define PCMD7 (0x40F50110 + 7 * 4)
+#define PCMD8 (0x40F50110 + 8 * 4)
+#define PCMD9 (0x40F50110 + 9 * 4)
+#define PCMD10 (0x40F50110 + 10 * 4)
+#define PCMD11 (0x40F50110 + 11 * 4)
+#define PCMD12 (0x40F50110 + 12 * 4)
+#define PCMD13 (0x40F50110 + 13 * 4)
+#define PCMD14 (0x40F50110 + 14 * 4)
+#define PCMD15 (0x40F50110 + 15 * 4)
+#define PCMD16 (0x40F50110 + 16 * 4)
+#define PCMD17 (0x40F50110 + 17 * 4)
+#define PCMD18 (0x40F50110 + 18 * 4)
+#define PCMD19 (0x40F50110 + 19 * 4)
+#define PCMD20 (0x40F50110 + 20 * 4)
+#define PCMD21 (0x40F50110 + 21 * 4)
+#define PCMD22 (0x40F50110 + 22 * 4)
+#define PCMD23 (0x40F50110 + 23 * 4)
+#define PCMD24 (0x40F50110 + 24 * 4)
+#define PCMD25 (0x40F50110 + 25 * 4)
+#define PCMD26 (0x40F50110 + 26 * 4)
+#define PCMD27 (0x40F50110 + 27 * 4)
+#define PCMD28 (0x40F50110 + 28 * 4)
+#define PCMD29 (0x40F50110 + 29 * 4)
+#define PCMD30 (0x40F50110 + 30 * 4)
+#define PCMD31 (0x40F50110 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
@@ -1798,64 +2128,64 @@ typedef void (*ExcpHndlr) (void) ;
#define PVCR_FVC (0x1 << 28)
#define PVCR_VCSA (0x1<<14)
#define PVCR_CommandDelay (0xf80)
-#define PVCR_ReadPointer (0x01f00000)
+#define PVCR_ReadPointer 0x01f00000
#define PVCR_SlaveAddress (0x7f)
#else /* ifdef CONFIG_CPU_MONAHANS */
-#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
-#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
-#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
-#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
-#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
-#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
-
-#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
-#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
-#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
-#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
-#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
-#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
-#define PCMD(x) __REG(0x40F00080 + x*4)
-#define PCMD0 __REG(0x40F00080 + 0 * 4)
-#define PCMD1 __REG(0x40F00080 + 1 * 4)
-#define PCMD2 __REG(0x40F00080 + 2 * 4)
-#define PCMD3 __REG(0x40F00080 + 3 * 4)
-#define PCMD4 __REG(0x40F00080 + 4 * 4)
-#define PCMD5 __REG(0x40F00080 + 5 * 4)
-#define PCMD6 __REG(0x40F00080 + 6 * 4)
-#define PCMD7 __REG(0x40F00080 + 7 * 4)
-#define PCMD8 __REG(0x40F00080 + 8 * 4)
-#define PCMD9 __REG(0x40F00080 + 9 * 4)
-#define PCMD10 __REG(0x40F00080 + 10 * 4)
-#define PCMD11 __REG(0x40F00080 + 11 * 4)
-#define PCMD12 __REG(0x40F00080 + 12 * 4)
-#define PCMD13 __REG(0x40F00080 + 13 * 4)
-#define PCMD14 __REG(0x40F00080 + 14 * 4)
-#define PCMD15 __REG(0x40F00080 + 15 * 4)
-#define PCMD16 __REG(0x40F00080 + 16 * 4)
-#define PCMD17 __REG(0x40F00080 + 17 * 4)
-#define PCMD18 __REG(0x40F00080 + 18 * 4)
-#define PCMD19 __REG(0x40F00080 + 19 * 4)
-#define PCMD20 __REG(0x40F00080 + 20 * 4)
-#define PCMD21 __REG(0x40F00080 + 21 * 4)
-#define PCMD22 __REG(0x40F00080 + 22 * 4)
-#define PCMD23 __REG(0x40F00080 + 23 * 4)
-#define PCMD24 __REG(0x40F00080 + 24 * 4)
-#define PCMD25 __REG(0x40F00080 + 25 * 4)
-#define PCMD26 __REG(0x40F00080 + 26 * 4)
-#define PCMD27 __REG(0x40F00080 + 27 * 4)
-#define PCMD28 __REG(0x40F00080 + 28 * 4)
-#define PCMD29 __REG(0x40F00080 + 29 * 4)
-#define PCMD30 __REG(0x40F00080 + 30 * 4)
-#define PCMD31 __REG(0x40F00080 + 31 * 4)
+#define PMCR 0x40F00000 /* Power Manager Control Register */
+#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */
+#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */
+#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */
+#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR 0x40F0001C /* Power Manager General Configuration Register */
+#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR 0x40F00030 /* Reset Controller Status Register */
+
+#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */
+#define PSTR 0x40F00038 /* Power Manager Standby Config Register */
+#define PSNR 0x40F0003C /* Power Manager Sense Config Register */
+#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */
+#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */
+#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */
+#define PCMD(x) (0x40F00080 + x*4)
+#define PCMD0 (0x40F00080 + 0 * 4)
+#define PCMD1 (0x40F00080 + 1 * 4)
+#define PCMD2 (0x40F00080 + 2 * 4)
+#define PCMD3 (0x40F00080 + 3 * 4)
+#define PCMD4 (0x40F00080 + 4 * 4)
+#define PCMD5 (0x40F00080 + 5 * 4)
+#define PCMD6 (0x40F00080 + 6 * 4)
+#define PCMD7 (0x40F00080 + 7 * 4)
+#define PCMD8 (0x40F00080 + 8 * 4)
+#define PCMD9 (0x40F00080 + 9 * 4)
+#define PCMD10 (0x40F00080 + 10 * 4)
+#define PCMD11 (0x40F00080 + 11 * 4)
+#define PCMD12 (0x40F00080 + 12 * 4)
+#define PCMD13 (0x40F00080 + 13 * 4)
+#define PCMD14 (0x40F00080 + 14 * 4)
+#define PCMD15 (0x40F00080 + 15 * 4)
+#define PCMD16 (0x40F00080 + 16 * 4)
+#define PCMD17 (0x40F00080 + 17 * 4)
+#define PCMD18 (0x40F00080 + 18 * 4)
+#define PCMD19 (0x40F00080 + 19 * 4)
+#define PCMD20 (0x40F00080 + 20 * 4)
+#define PCMD21 (0x40F00080 + 21 * 4)
+#define PCMD22 (0x40F00080 + 22 * 4)
+#define PCMD23 (0x40F00080 + 23 * 4)
+#define PCMD24 (0x40F00080 + 24 * 4)
+#define PCMD25 (0x40F00080 + 25 * 4)
+#define PCMD26 (0x40F00080 + 26 * 4)
+#define PCMD27 (0x40F00080 + 27 * 4)
+#define PCMD28 (0x40F00080 + 28 * 4)
+#define PCMD29 (0x40F00080 + 29 * 4)
+#define PCMD30 (0x40F00080 + 30 * 4)
+#define PCMD31 (0x40F00080 + 31 * 4)
#define PCMD_MBC (1<<12)
#define PCMD_DCE (1<<11)
@@ -1891,183 +2221,58 @@ typedef void (*ExcpHndlr) (void) ;
/*
* SSP Serial Port Registers
*/
-#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */
-#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */
-#define SSSR __REG(0x41000008) /* SSP Status Register */
-#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */
-#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+#define SSCR0 0x41000000 /* SSP Control Register 0 */
+#define SSCR1 0x41000004 /* SSP Control Register 1 */
+#define SSSR 0x41000008 /* SSP Status Register */
+#define SSITR 0x4100000C /* SSP Interrupt Test Register */
+#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
/*
* MultiMediaCard (MMC) controller
*/
-#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
-#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
-#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
-#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
-#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
-#define MMC_RESTO __REG(0x41100014) /* Expected response time out */
-#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
-#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
-#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
-#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
-#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
-#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
-#define MMC_CMD __REG(0x41100030) /* Index of current command */
-#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
-#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
-#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
-#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
-#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
-
-/*
- * Core Clock
- */
-
-#if defined(CONFIG_CPU_MONAHANS)
-#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
-#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
-#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
-#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
-#define CKENB __REG(0x41340010) /* B Clock Enable Register */
-#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
-
-#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
-#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
-#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
-#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
-#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
-#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
-#define ACCR_XPDIS (1 << 31)
-#define ACCR_SPDIS (1 << 30)
-#define ACCR_13MEND1 (1 << 27)
-#define ACCR_D0CS (1 << 26)
-#define ACCR_13MEND2 (1 << 21)
-#define ACCR_PCCE (1 << 11)
-
-#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
-#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
-#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
-#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
-#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
-#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
-#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
-#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
-#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
-#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
-#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
-#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
-#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
-#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
-#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
-#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
-#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
-#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
-#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
-#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
-#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
-#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
-#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
-#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
-#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
-#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
-#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
-#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
-
-#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
-#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
-#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
-#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
-#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
-#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
-
-#else /* if defined CONFIG_CPU_MONAHANS */
-
-#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
-#define CKEN __REG(0x41300004) /* Clock Enable Register */
-#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
-
-#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#if !defined(CONFIG_PXA27X)
-#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
-#endif
-#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
-
-#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
-#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
-#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
-#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
-#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
-#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
-#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
-#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
-#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
-#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
-#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
-#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
-#if defined(CONFIG_PXA27X)
-#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
-#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
-#endif
-#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
-#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
-#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
-#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
-#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
-#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
-#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
-#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
-
-#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
-
-#if !defined(CONFIG_PXA27X)
-#define CCCR_L09 (0x1F)
-#define CCCR_L27 (0x1)
-#define CCCR_L32 (0x2)
-#define CCCR_L36 (0x3)
-#define CCCR_L40 (0x4)
-#define CCCR_L45 (0x5)
-
-#define CCCR_M1 (0x1 << 5)
-#define CCCR_M2 (0x2 << 5)
-#define CCCR_M4 (0x3 << 5)
-
-#define CCCR_N10 (0x2 << 7)
-#define CCCR_N15 (0x3 << 7)
-#define CCCR_N20 (0x4 << 7)
-#define CCCR_N25 (0x5 << 7)
-#define CCCR_N30 (0x6 << 7)
-#endif
+#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */
+#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */
+#define MMC_CLKRT 0x41100008 /* MMC clock rate */
+#define MMC_SPI 0x4110000c /* SPI mode control bits */
+#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */
+#define MMC_RESTO 0x41100014 /* Expected response time out */
+#define MMC_RDTO 0x41100018 /* Expected data read time out */
+#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */
+#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */
+#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK 0x41100028 /* Interrupt Mask */
+#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */
+#define MMC_CMD 0x41100030 /* Index of current command */
+#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */
+#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */
+#define MMC_RES 0x4110003c /* Response FIFO (read only) */
+#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */
+#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */
-#endif /* CONFIG_CPU_MONAHANS */
/*
* LCD
*/
-#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
-#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
-#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
-#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
-#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
-#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
-#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
-#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
-#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
-#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
-#define TMEDCR __REG(0x44000044) /* TMED Control Register */
-
-#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
-#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
-#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
-#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
-#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
-#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
-#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
-#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
+#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */
+#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */
+#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */
+#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */
+#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
+#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
+#define LCSR0 0x44000038 /* LCD Controller Status Register */
+#define LCSR1 0x44000034 /* LCD Controller Status Register */
+#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */
+#define TMEDCR 0x44000044 /* TMED Control Register */
+
+#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */
+#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */
+#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */
+#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */
#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
#define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
@@ -2135,22 +2340,12 @@ typedef void (*ExcpHndlr) (void) ;
/* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_BFW))
-#if 0
-#define LCCR3_PCD (0xff) /* Pixel clock divisor */
-#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
-#define LCCR3_ACB_S 8
-#endif
-
#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
#define LCCR3_API_S 16
#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
#define LCCR3_PCP (1 << 22) /* pixel clock polarity */
#define LCCR3_OEP (1 << 23) /* output enable polarity */
-#if 0
-#define LCCR3_BPP (7 << 24) /* bits per pixel */
-#define LCCR3_BPP_S 24
-#endif
#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
#define LCCR3_PDFOR_0 (0 << 30)
@@ -2231,46 +2426,49 @@ typedef void (*ExcpHndlr) (void) ;
*/
#ifdef CONFIG_CPU_MONAHANS
+
+/* PXA3xx */
+
/* Static Memory Controller Registers */
-#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */
-#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */
-#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */
-#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */
-#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */
-#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */
-#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */
-#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */
-#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */
-#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */
-#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */
-#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */
-#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */
+#define MSC0 0x4A000008 /* Static Memory Control Register 0 */
+#define MSC1 0x4A00000C /* Static Memory Control Register 1 */
+#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */
+#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
+#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */
+#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */
+#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */
+#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */
+#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */
+#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */
+#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */
+#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
+#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
/* Dynamic Memory Controller Registers */
-#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */
-#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */
-#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */
-#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */
-#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */
-#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
-#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */
-#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */
-#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */
-#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */
-#define EMPI __REG_2(0x48100090) /* EMPI Control Register */
-#define RCOMP __REG_2(0x48100100)
-#define PAD_MA __REG_2(0x48100110)
-#define PAD_MDMSB __REG_2(0x48100114)
-#define PAD_MDLSB __REG_2(0x48100118)
-#define PAD_DMEM __REG_2(0x4810011c)
-#define PAD_SDCLK __REG_2(0x48100120)
-#define PAD_SDCS __REG_2(0x48100124)
-#define PAD_SMEM __REG_2(0x48100128)
-#define PAD_SCLK __REG_2(0x4810012C)
-#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */
+#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */
+#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
+#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */
+#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */
+#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */
+#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */
+#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
+#define EMPI 0x48100090 /* EMPI Control Register */
+#define RCOMP 0x48100100
+#define PAD_MA 0x48100110
+#define PAD_MDMSB 0x48100114
+#define PAD_MDLSB 0x48100118
+#define PAD_DMEM 0x4810011c
+#define PAD_SDCLK 0x48100120
+#define PAD_SDCS 0x48100124
+#define PAD_SMEM 0x48100128
+#define PAD_SCLK 0x4810012C
+#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */
/* Some frequently used bits */
#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
@@ -2298,19 +2496,19 @@ typedef void (*ExcpHndlr) (void) ;
/* Data Flash Controller Registers */
-#define NDCR __REG(0x43100000) /* Data Flash Control register */
-#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
-/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
-#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
-/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
-#define NDSR __REG(0x43100014) /* Data Controller Status Register */
-#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */
-#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */
-#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */
-#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */
-#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */
-#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */
-#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */
+#define NDCR 0x43100000 /* Data Flash Control register */
+#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR 0x43100014 /* Data Controller Status Register */
+#define NDPCR 0x43100018 /* Data Controller Page Count Register */
+#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */
+#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */
+#define NDDB 0x43100040 /* Data Controller Data Buffer */
+#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */
+#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */
+#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */
#define NDCR_SPARE_EN (0x1<<31)
#define NDCR_ECC_EN (0x1<<30)
@@ -2386,7 +2584,9 @@ typedef void (*ExcpHndlr) (void) ;
#else /* CONFIG_CPU_MONAHANS */
-#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
+/* PXA2xx */
+
+#define MEMC_BASE 0x48000000 /* Base of Memory Controller */
#define MDCNFG_OFFSET 0x0
#define MDREFR_OFFSET 0x4
#define MSC0_OFFSET 0x8
@@ -2405,29 +2605,30 @@ typedef void (*ExcpHndlr) (void) ;
#define MCIO1_OFFSET 0x3C
#define MDMRS_OFFSET 0x40
-#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
+#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */
#define MDCNFG_DE0 0x00000001
#define MDCNFG_DE1 0x00000002
#define MDCNFG_DE2 0x00010000
#define MDCNFG_DE3 0x00020000
#define MDCNFG_DWID0 0x00000004
-#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
-#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
-#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
-#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
-#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
-#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
-#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */
+#define MSC0 0x48000008 /* Static Memory Control Register 0 */
+#define MSC1 0x4800000C /* Static Memory Control Register 1 */
+#define MSC2 0x48000010 /* Static Memory Control Register 2 */
+#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */
+#define FLYCNFG 0x48000020
+#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */
+#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */
#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */
@@ -2448,7 +2649,7 @@ typedef void (*ExcpHndlr) (void) ;
#if defined(CONFIG_PXA27X)
-#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
+#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */
#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
@@ -2460,80 +2661,41 @@ typedef void (*ExcpHndlr) (void) ;
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
-#endif /* CONFIG_CPU_MONAHANS */
-
-/* Interrupt Controller */
-
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-
-/* General Purpose I/O */
-
-#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
-#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
-#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
-#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
-#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
-#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */
-#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
-#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
-#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
-
-/* Core Clock */
-
-#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
-
-#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC (1 << 22) /* Memory Controler */
-#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
-#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
-#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
-#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
-#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
-#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
-#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
-
-/* Memory controller */
-
-#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */
+#endif /* CONFIG_PXA27X */
/* LCD registers */
-#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
-#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
-#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
-#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
-#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
-#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
-#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
-#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
-#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
-#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
-#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
-#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
-#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
-#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
-#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
-#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
-#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
-#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
-#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
-#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
-#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
-#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
-#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
-
-#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
-#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
-#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
-#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
-#define CCR __REG(0x44000090) /* Cursor Control Register */
-
-#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
-#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
+#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */
+#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */
+#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */
+#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */
+#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */
+#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */
+#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */
+#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */
+#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */
+#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */
+#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */
+#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */
+#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */
+#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */
+#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */
+
+#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */
+#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */
+#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */
+#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */
+#define CCR 0x44000090 /* Cursor Control Register */
+
+#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */
+#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */
#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */
#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */
@@ -2572,16 +2734,16 @@ typedef void (*ExcpHndlr) (void) ;
/* Keypad controller */
-#define KPC __REG(0x41500000) /* Keypad Interface Control register */
-#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
-#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
-#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */
-#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
-#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
-#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
-#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
-#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
-#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
+#define KPC 0x41500000 /* Keypad Interface Control register */
+#define KPDK 0x41500008 /* Keypad Interface Direct Key register */
+#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */
+#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */
+#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */
+#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */
#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
@@ -2623,15 +2785,15 @@ typedef void (*ExcpHndlr) (void) ;
#define KPASMKPx_SO (0x1 << 31)
#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR __REG(0x40F00034)
-#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
-#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
-#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
-#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4 __REG(0x40A00080) /* */
-#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
-#define OMCR4 __REG(0x40A000C0) /* */
+#define PSLR 0x40F00034
+#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */
+#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */
+#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */
+#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4 0x40A00080 /* */
+#define OSCR4 0x40A00040 /* OS Timer Counter Register */
+#define OMCR4 0x40A000C0 /* */
#endif /* CONFIG_PXA27X */
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index d8e33fc..4124f0a 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -21,10 +21,9 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* Relocation to SDRAM works on all ARM boards */
#define CONFIG_RELOC_FIXUP_WORKS
-#endif
+
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 6152f34..6dae432 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -47,6 +47,20 @@ typedef struct global_data {
#ifdef CONFIG_FSL_ESDHC
unsigned long sdhc_clk;
#endif
+#ifdef CONFIG_AT91FAMILY
+ /* "static data" needed by at91's clock.c */
+ unsigned long cpu_clk_rate_hz;
+ unsigned long main_clk_rate_hz;
+ unsigned long mck_rate_hz;
+ unsigned long plla_rate_hz;
+ unsigned long pllb_rate_hz;
+ unsigned long at91_pllb_usb_init;
+ /* "static data" needed by at91's timer.c */
+ unsigned long timer_rate_hz;
+ unsigned long tbl;
+ unsigned long tbu;
+ unsigned long long timer_reset_value;
+#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index faf800a..4ac4f61 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -30,18 +30,18 @@
#define _U_BOOT_ARM_H_ 1
/* for the following variables, see start.S */
-extern ulong _bss_start; /* code + data end == BSS start */
-extern ulong _bss_end; /* BSS end */
+extern ulong _bss_start_ofs; /* BSS start relative to _start */
+extern ulong _bss_end_ofs; /* BSS end relative to _start */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
-extern ulong _armboot_start; /* code start */
+extern ulong _armboot_start_ofs; /* code start */
#else
extern ulong _TEXT_BASE; /* code start */
-extern ulong _datarel_start;
-extern ulong _datarelrolocal_start;
-extern ulong _datarellocal_start;
-extern ulong _datarelro_start;
+extern ulong _datarel_start_ofs;
+extern ulong _datarelrolocal_start_ofs;
+extern ulong _datarellocal_start_ofs;
+extern ulong _datarelro_start_ofs;
extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
#endif
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 108e6c4..ffe261b 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -147,7 +147,7 @@ static int display_banner (void)
#else
_armboot_start,
#endif
- _bss_start, _bss_end);
+ _bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
#ifdef CONFIG_MODEM_SUPPORT
debug ("Modem Support enabled\n");
#endif
@@ -508,7 +508,7 @@ void board_init_f (ulong bootflag)
memset ((void*)gd, 0, sizeof (gd_t));
- gd->mon_len = _bss_end - _TEXT_BASE;
+ gd->mon_len = _bss_end_ofs;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
@@ -670,6 +670,7 @@ static char *failed = "*** failed ***\n";
*
************************************************************************
*/
+
void board_init_r (gd_t *id, ulong dest_addr)
{
char *s;
@@ -693,7 +694,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
- monitor_flash_len = _bss_start - _TEXT_BASE;
+ monitor_flash_len = _bss_start_ofs;
debug ("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
@@ -895,6 +896,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
/* NOTREACHED - no way out of command loop except booting */
}
+
#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
void hang (void)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 55b633e..5715168 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -38,7 +38,7 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2)
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
#endif
-#ifdef CONFIG_ARMCORTEXA8
+#ifdef CONFIG_ARMV7
void v7_flush_cache_all(void);
v7_flush_cache_all();
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index e6b81cc..96ccc7f 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -257,7 +257,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
extern char * env_name_spec;
#endif
char *s;
- cmd_tbl_t *cmdtp;
bd_t *bd;
gd = new_gd;
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
index eba2435..4541e24 100644
--- a/arch/m68k/lib/board.c
+++ b/arch/m68k/lib/board.c
@@ -393,7 +393,6 @@ board_init_f (ulong bootflag)
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
- cmd_tbl_t *cmdtp;
char *s;
bd_t *bd;
extern void malloc_bin_reloc (void);
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index 0044b19..4a22f7b 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -276,7 +276,6 @@ void board_init_f(ulong bootflag)
void board_init_r (gd_t *id, ulong dest_addr)
{
- cmd_tbl_t *cmdtp;
#ifndef CONFIG_SYS_NO_FLASH
ulong size;
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk
index f07d920..ce4376b 100644
--- a/arch/powerpc/cpu/mpc85xx/config.mk
+++ b/arch/powerpc/cpu/mpc85xx/config.mk
@@ -25,6 +25,10 @@ PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
+# Enable gc-sections to enable generation of smaller images.
+PLATFORM_LDFLAGS += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
# see "[PATCH,rs6000] make -mno-spe work as expected" on
# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3f80700..fc5d951 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,6 +34,9 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <post.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -282,3 +285,219 @@ void mpc85xx_reginfo(void)
print_laws();
print_lbc_regs();
}
+
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+
+/* Board-specific functions defined in each board's ddr.c */
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num);
+void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
+ phys_addr_t *rpn);
+unsigned int
+ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
+
+static void dump_spd_ddr_reg(void)
+{
+ int i, j, k, m;
+ u8 *p_8;
+ u32 *p_32;
+ ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
+ generic_spd_eeprom_t
+ spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
+
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ fsl_ddr_get_spd(spd[i], i);
+
+ puts("SPD data of all dimms (zero vaule is omitted)...\n");
+ puts("Byte (hex) ");
+ k = 1;
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
+ printf("Dimm%d ", k++);
+ }
+ puts("\n");
+ for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
+ m = 0;
+ printf("%3d (0x%02x) ", k, k);
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+ p_8 = (u8 *) &spd[i][j];
+ if (p_8[k]) {
+ printf("0x%02x ", p_8[k]);
+ m++;
+ } else
+ puts(" ");
+ }
+ }
+ if (m)
+ puts("\n");
+ else
+ puts("\r");
+ }
+
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ switch (i) {
+ case 0:
+ ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+ break;
+#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
+ case 1:
+ ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+ break;
+#endif
+ default:
+ printf("%s unexpected controller number = %u\n",
+ __func__, i);
+ return;
+ }
+ }
+ printf("DDR registers dump for all controllers "
+ "(zero vaule is omitted)...\n");
+ puts("Offset (hex) ");
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
+ printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
+ puts("\n");
+ for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
+ m = 0;
+ printf("%6d (0x%04x)", k * 4, k * 4);
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ p_32 = (u32 *) ddr[i];
+ if (p_32[k]) {
+ printf(" 0x%08x", p_32[k]);
+ m++;
+ } else
+ puts(" ");
+ }
+ if (m)
+ puts("\n");
+ else
+ puts("\r");
+ }
+ puts("\n");
+}
+
+/* invalid the TLBs for DDR and setup new ones to cover p_addr */
+static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
+{
+ u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned long epn;
+ u32 tsize, valid, ptr;
+ phys_addr_t rpn = 0;
+ int ddr_esel;
+
+ ptr = vstart;
+
+ while (ptr < (vstart + size)) {
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+ disable_tlb(ddr_esel);
+ }
+ ptr += TSIZE_TO_BYTES(tsize);
+ }
+
+ /* Setup new tlb to cover the physical address */
+ setup_ddr_tlbs_phys(p_addr, size>>20);
+
+ ptr = vstart;
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
+ } else {
+ printf("TLB error in function %s\n", __func__);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * slide the testing window up to test another area
+ * for 32_bit system, the maximum testable memory is limited to
+ * CONFIG_MAX_MEM_MAPPED
+ */
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ phys_addr_t test_cap, p_addr;
+ phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+
+#if !defined(CONFIG_PHYS_64BIT) || \
+ !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
+ (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+ test_cap = p_size;
+#else
+ test_cap = gd->ram_size;
+#endif
+ p_addr = (*vstart) + (*size) + (*phys_offset);
+ if (p_addr < test_cap - 1) {
+ p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
+ if (reset_tlb(p_addr, p_size, phys_offset) == -1)
+ return -1;
+ *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ *size = (u32) p_size;
+ printf("Testing 0x%08llx - 0x%08llx\n",
+ (u64)(*vstart) + (*phys_offset),
+ (u64)(*vstart) + (*phys_offset) + (*size) - 1);
+ } else
+ return 1;
+
+ return 0;
+}
+
+/* initialization for testing area */
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
+
+ *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
+ *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
+ *phys_offset = 0;
+
+#if !defined(CONFIG_PHYS_64BIT) || \
+ !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
+ (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
+ if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+ puts("Cannot test more than ");
+ print_size(CONFIG_MAX_MEM_MAPPED,
+ " without proper 36BIT support.\n");
+ }
+#endif
+ printf("Testing 0x%08llx - 0x%08llx\n",
+ (u64)(*vstart) + (*phys_offset),
+ (u64)(*vstart) + (*phys_offset) + (*size) - 1);
+
+ return 0;
+}
+
+/* invalid TLBs for DDR and remap as normal after testing */
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ unsigned long epn;
+ u32 tsize, valid, ptr;
+ phys_addr_t rpn = 0;
+ int ddr_esel;
+
+ /* disable the TLBs for this testing */
+ ptr = *vstart;
+
+ while (ptr < (*vstart) + (*size)) {
+ ddr_esel = find_tlb_idx((void *)ptr, 1);
+ if (ddr_esel != -1) {
+ read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
+ disable_tlb(ddr_esel);
+ }
+ ptr += TSIZE_TO_BYTES(tsize);
+ }
+
+ puts("Remap DDR ");
+ setup_ddr_tlbs(gd->ram_size>>20);
+ puts("\n");
+
+ return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+ dump_spd_ddr_reg();
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 4540364..53e0596 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -48,6 +48,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
ulong spin_tbl_addr = get_spin_phys_addr();
u32 bootpg = determine_mp_bootpg();
u32 id = get_my_id();
+ const char *enable_method;
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
@@ -63,10 +64,25 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
fdt_setprop_string(blob, off, "status",
"disabled");
}
+
+ if (hold_cores_in_reset(0)) {
+#ifdef CONFIG_FSL_CORENET
+ /* Cores held in reset, use BRR to release */
+ enable_method = "fsl,brr-holdoff";
+#else
+ /* Cores held in reset, use EEBPCR to release */
+ enable_method = "fsl,eebpcr-holdoff";
+#endif
+ } else {
+ /* Cores out of reset and in a spin-loop */
+ enable_method = "spin-table";
+
+ fdt_setprop(blob, off, "cpu-release-addr",
+ &val, sizeof(val));
+ }
+
fdt_setprop_string(blob, off, "enable-method",
- "spin-table");
- fdt_setprop(blob, off, "cpu-release-addr",
- &val, sizeof(val));
+ enable_method);
} else {
printf ("cpu NULL\n");
}
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 603baef..a019b1b 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -36,6 +36,27 @@ u32 get_my_id()
return mfspr(SPRN_PIR);
}
+/*
+ * Determine if U-Boot should keep secondary cores in reset, or let them out
+ * of reset and hold them in a spinloop
+ */
+int hold_cores_in_reset(int verbose)
+{
+ const char *s = getenv("mp_holdoff");
+
+ /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
+ if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
+ if (verbose) {
+ puts("Secondary cores are being held in reset.\n");
+ puts("See 'mp_holdoff' environment variable\n");
+ }
+
+ return 1;
+ }
+
+ return 0;
+}
+
int cpu_reset(int nr)
{
volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
@@ -51,6 +72,9 @@ int cpu_status(int nr)
{
u32 *table, id = get_my_id();
+ if (hold_cores_in_reset(1))
+ return 0;
+
if (nr == id) {
table = (u32 *)get_spin_virt_addr();
printf("table base @ 0x%p\n", table);
@@ -133,6 +157,9 @@ int cpu_release(int nr, int argc, char * const argv[])
u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
+ if (hold_cores_in_reset(1))
+ return 0;
+
if (nr == get_my_id()) {
printf("Invalid to release the boot core.\n\n");
return 1;
@@ -353,6 +380,10 @@ void setup_mp(void)
ulong fixup = (ulong)&__secondary_start_page;
u32 bootpg = determine_mp_bootpg();
+ /* Some OSes expect secondary cores to be held in reset */
+ if (hold_cores_in_reset(0))
+ return;
+
/* Store the bootpg's SDRAM address for use by secondary CPU cores */
__bootpg_addr = bootpg;
diff --git a/arch/powerpc/cpu/mpc85xx/mp.h b/arch/powerpc/cpu/mpc85xx/mp.h
index 3422cc1..87bac37 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.h
+++ b/arch/powerpc/cpu/mpc85xx/mp.h
@@ -6,6 +6,7 @@
ulong get_spin_phys_addr(void);
ulong get_spin_virt_addr(void);
u32 get_my_id(void);
+int hold_cores_in_reset(int verbose);
#define BOOT_ENTRY_ADDR_UPPER 0
#define BOOT_ENTRY_ADDR_LOWER 1
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index f2833a5..e3a71ae 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -245,7 +245,8 @@ void init_addr_map(void)
}
#endif
-unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+unsigned int
+setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
int i;
unsigned int tlb_size;
@@ -275,21 +276,24 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
tlb_size = (camsize - 10) / 2;
- set_tlb(1, ram_tlb_address, ram_tlb_address,
+ set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
memsize -= 1ULL << camsize;
ram_tlb_address += 1UL << camsize;
+ p_addr += 1UL << camsize;
}
if (memsize)
print_size(memsize, " left unmapped\n");
-
- /*
- * Confirm that the requested amount of memory was mapped.
- */
return memsize_in_meg;
}
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+ return
+ setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
+}
#endif /* !CONFIG_NAND_SPL */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index c88b1f3..85042c5 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -25,8 +25,7 @@
#endif
OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
PHDRS
{
text PT_LOAD;
@@ -38,42 +37,16 @@ SECTIONS
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- *(.text)
- *(.got1)
+ *(.text*)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
} :text
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@@ -81,23 +54,19 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
@@ -126,7 +95,7 @@ SECTIONS
.resetvec RESET_VECTOR_ADDRESS :
{
- *(.resetvec)
+ KEEP(*(.resetvec))
} :text = 0xffff
. = RESET_VECTOR_ADDRESS + 0x4;
@@ -145,9 +114,8 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
} :bss
diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk
index ca2f837..bce0fb3 100644
--- a/arch/powerpc/cpu/mpc86xx/config.mk
+++ b/arch/powerpc/cpu/mpc86xx/config.mk
@@ -25,3 +25,10 @@ PLATFORM_RELFLAGS += -fPIC -meabi
PLATFORM_CPPFLAGS += -ffixed-r2 -mstring
PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
+
+# Enable gc-sections to enable generation of smaller images.
+PLATFORM_LDFLAGS += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
+# Use default linker script. Board port can override in board/*/config.mk
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc86xx/u-boot.lds
diff --git a/board/xes/xpedite5170/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds
index 4cea3b3..4bfcb90 100644
--- a/board/xes/xpedite5170/u-boot.lds
+++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds
@@ -60,19 +60,14 @@ SECTIONS
lib/crc32.o (.text)
arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
- *(.text)
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
- *(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
@@ -80,23 +75,19 @@ SECTIONS
PROVIDE (erotext = .);
.reloc :
{
- *(.got)
+ KEEP(*(.got))
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
@@ -121,9 +112,8 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) :
{
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
. = ALIGN(4);
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index e82082e..3fec100 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1184,6 +1184,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
unsigned int sr_it;
unsigned int zq_en;
unsigned int wrlvl_en;
+ int cs_en = 1;
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@@ -1250,16 +1251,23 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
* and each controller uses rank interleaving within
* itself. Therefore the starting and ending address
* on each controller is twice the amount present on
- * each controller.
+ * each controller. If any CS is not included in the
+ * interleaving, the memory on that CS is not accssible
+ * and the total memory size is reduced. The CS is also
+ * disabled.
*/
unsigned long long ctlr_density = 0;
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1:
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
ctlr_density = dimm_params[0].rank_density * 2;
+ if (i > 1)
+ cs_en = 0;
break;
case FSL_DDR_CS2_CS3:
ctlr_density = dimm_params[0].rank_density;
+ if (i > 0)
+ cs_en = 0;
break;
case FSL_DDR_CS0_CS1_CS2_CS3:
/*
@@ -1379,8 +1387,11 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
);
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
- set_csn_config(dimm_number, i, ddr, popts, dimm_params);
- set_csn_config_2(i, ddr);
+ if (cs_en) {
+ set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+ set_csn_config_2(i, ddr);
+ } else
+ printf("CS%d is disabled.\n", i);
}
set_ddr_eor(ddr, popts);
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 88c47d1..54e60bb 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -27,6 +27,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/mp.h>
+#include <asm/fsl_enet.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -215,3 +216,26 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
fdt_del_node_and_alias(blob, "crypto");
}
#endif
+
+int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
+{
+ static const char *fsl_phy_enet_if_str[] = {
+ [MII] = "mii",
+ [RMII] = "rmii",
+ [GMII] = "gmii",
+ [RGMII] = "rgmii",
+ [RGMII_ID] = "rgmii-id",
+ [RGMII_RXID] = "rgmii-rxid",
+ [SGMII] = "sgmii",
+ [TBI] = "tbi",
+ [RTBI] = "rtbi",
+ [XAUI] = "xgmii",
+ [FSL_ETH_IF_NONE] = "",
+ };
+
+ if (phyc > ARRAY_SIZE(fsl_phy_enet_if_str))
+ return fdt_setprop_string(blob, offset, "phy-connection-type", "");
+
+ return fdt_setprop_string(blob, offset, "phy-connection-type",
+ fsl_phy_enet_if_str[phyc]);
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
index 186936f..53236a3 100644
--- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
+++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
@@ -138,7 +138,10 @@ static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCIE_1] = {
.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
- (1 << 7) | (1 << 0xe) | (1 << 0xf),
+ (1 << 7) | (1 << 0xf),
+ },
+ [LAW_TRGT_IF_PCIE_2] = {
+ .cfg = (1 << 3) | (1 << 0xe) | (1 << 0xf),
},
};
#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 2a727b1..bf208ad 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -342,7 +342,7 @@ cpu_init_f (void)
#endif
#if defined(CONFIG_WATCHDOG)
- val = mfspr(tcr);
+ val = mfspr(SPRN_TCR);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
@@ -354,11 +354,11 @@ cpu_init_f (void)
val &= ~0x30000000; /* clear WRC bits */
val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
#endif
- mtspr(tcr, val);
+ mtspr(SPRN_TCR, val);
- val = mfspr(tsr);
+ val = mfspr(SPRN_TSR);
val |= 0x80000000; /* enable watchdog timer */
- mtspr(tsr, val);
+ mtspr(SPRN_TSR, val);
reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c
index c2d4973..d0bca92 100644
--- a/arch/powerpc/cpu/ppc4xx/interrupts.c
+++ b/arch/powerpc/cpu/ppc4xx/interrupts.c
@@ -67,13 +67,6 @@ static __inline__ void set_pit(unsigned long val)
asm volatile("mtpit %0" : : "r" (val));
}
-
-static __inline__ void set_tcr(unsigned long val)
-{
- asm volatile("mttcr %0" : : "r" (val));
-}
-
-
static __inline__ void set_evpr(unsigned long val)
{
asm volatile("mtevpr %0" : : "r" (val));
diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c
index b5562ad..9baa7a1 100644
--- a/arch/powerpc/cpu/ppc4xx/traps.c
+++ b/arch/powerpc/cpu/ppc4xx/traps.c
@@ -46,15 +46,6 @@ extern unsigned long search_exception_table(unsigned long);
*/
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
-static __inline__ void set_tsr(unsigned long val)
-{
-#if defined(CONFIG_440)
- asm volatile("mtspr 0x150, %0" : : "r" (val));
-#else
- asm volatile("mttsr %0" : : "r" (val));
-#endif
-}
-
static __inline__ unsigned long get_esr(void)
{
unsigned long val;
@@ -364,7 +355,7 @@ DecrementerPITException(struct pt_regs *regs)
/*
* Reset PIT interrupt
*/
- set_tsr(0x08000000);
+ mtspr(SPRN_TSR, 0x08000000);
/*
* Call timer_interrupt routine in interrupts.c
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index d576eb8..17d4b31 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -213,4 +213,10 @@ typedef struct memctl_options_s {
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
+
+typedef struct fixed_ddr_parm{
+ int min_freq;
+ int max_freq;
+ fsl_ddr_cfg_regs_t *ddr_settings;
+} fixed_ddr_parm_t;
#endif
diff --git a/arch/powerpc/include/asm/fsl_enet.h b/arch/powerpc/include/asm/fsl_enet.h
new file mode 100644
index 0000000..4fb2857
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_enet.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_FSL_ENET_H
+#define __ASM_PPC_FSL_ENET_H
+
+enum fsl_phy_enet_if {
+ MII,
+ RMII,
+ GMII,
+ RGMII,
+ RGMII_ID,
+ RGMII_RXID,
+ RGMII_TXID,
+ SGMII,
+ TBI,
+ RTBI,
+ XAUI,
+ FSL_ETH_IF_NONE,
+};
+
+int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc);
+
+#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/board/BuS/eb_cpux9k2/config.mk b/board/BuS/eb_cpux9k2/config.mk
deleted file mode 100644
index e554a45..0000000
--- a/board/BuS/eb_cpux9k2/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
index bbceaf3..fe62a0f 100644
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -66,7 +66,7 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
@@ -134,9 +134,8 @@ void reset_phy(void)
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size =
- get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk
index d07642f..2ffd125 100644
--- a/board/LaCie/edminiv2/config.mk
+++ b/board/LaCie/edminiv2/config.mk
@@ -24,4 +24,5 @@
# MA 02110-1301 USA
#
-CONFIG_SYS_TEXT_BASE = 0x00100000
+# TEXT_BASE must equal the intended FLASH location of u-boot.
+CONFIG_SYS_TEXT_BASE = 0xfff90000
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index c523bca..b518aa7 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -155,7 +155,8 @@ int misc_init_r(void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+ defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
@@ -163,7 +164,8 @@ int misc_init_r(void)
pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+ defined(CONFIG_SYS_RAMBOOT)
mtdcr(EBC0_CFGADDR, PB3CR);
#else
mtdcr(EBC0_CFGADDR, PB0CR);
diff --git a/board/atmel/at91rm9200ek/Makefile b/board/atmel/at91rm9200ek/Makefile
index 500ce72..96a0f05 100644
--- a/board/atmel/at91rm9200ek/Makefile
+++ b/board/atmel/at91rm9200ek/Makefile
@@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += led.o
-COBJS-y += misc.o
-ifdef CONFIG_HAS_DATAFLASH
-COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
-COBJS-y += partition.o
-endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
index 570a09a..d242583 100644
--- a/board/atmel/at91rm9200ek/at91rm9200ek.c
+++ b/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -1,4 +1,8 @@
/*
+ * (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
+ *
+ * derived from previous work
+ *
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
@@ -23,78 +27,44 @@
*/
#include <common.h>
-#include <exports.h>
#include <netdev.h>
-#include <asm/arch/AT91RM9200.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
#include <asm/io.h>
-#if defined(CONFIG_DRIVER_ETHER)
-#include <at91rm9200_net.h>
-#include <dm9161.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
+int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f ();
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
- writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
-
- /*
- * memory and cpu-speed are setup before relocation
- * so we do _nothing_ here
- */
+ writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
/* arch number of AT91RM9200EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init (void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
-#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
-/*
- * Name:
- * at91rm9200_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
-{
- p_phyops->Init = dm9161_InitPhy;
- p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
- p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
- p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
-}
-#endif
-
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
- int rc = 0;
- rc = at91emac_register(bis, 0);
- return rc;
+ return at91emac_register(bis, (u32) AT91_EMAC_BASE);
}
#endif
diff --git a/board/atmel/at91rm9200ek/config.mk b/board/atmel/at91rm9200ek/config.mk
index 2077692..c7323fe 100644
--- a/board/atmel/at91rm9200ek/config.mk
+++ b/board/atmel/at91rm9200ek/config.mk
@@ -1 +1,2 @@
-CONFIG_SYS_TEXT_BASE = 0x21f00000
+# currently only NOR flash booting is supported
+CONFIG_SYS_TEXT_BASE = 0x10000000
diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c
index 9464952..8d512e0 100644
--- a/board/atmel/at91rm9200ek/led.c
+++ b/board/atmel/at91rm9200ek/led.c
@@ -3,6 +3,9 @@
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
*
+ * (C) Copyright 2010
+ * Andreas Bießmann <andreas.devel@gmail.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -23,67 +26,62 @@
*/
#include <common.h>
-#include <asm/arch/AT91RM9200.h>
-#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pmc.h>
-#define GREEN_LED AT91C_PIO_PB0
-#define YELLOW_LED AT91C_PIO_PB1
-#define RED_LED AT91C_PIO_PB2
+/* bit mask in PIO port B */
+#define GREEN_LED (1<<0)
+#define YELLOW_LED (1<<1)
+#define RED_LED (1<<2)
void green_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(GREEN_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(GREEN_LED, &pio->piob.codr);
}
void yellow_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(YELLOW_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(YELLOW_LED, &pio->piob.codr);
}
void red_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(RED_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(RED_LED, &pio->piob.codr);
}
void green_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(GREEN_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(GREEN_LED, &pio->piob.sodr);
}
void yellow_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(YELLOW_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(YELLOW_LED, &pio->piob.sodr);
}
void red_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(RED_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(RED_LED, &pio->piob.sodr);
}
-
void coloured_LED_init (void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
- AT91PS_PMC PMC = AT91C_BASE_PMC;
+ at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/* Enable PIOB clock */
- writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
+ writel(1 << AT91_ID_PIOB, &pmc->pcer);
+
/* Disable peripherals on LEDs */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
/* Enable pins as outputs */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
/* Turn all LEDs OFF */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
}
diff --git a/board/atmel/at91rm9200ek/mux.c b/board/atmel/at91rm9200ek/mux.c
deleted file mode 100644
index bdd44e8..0000000
--- a/board/atmel/at91rm9200ek/mux.c
+++ /dev/null
@@ -1,38 +0,0 @@
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <dataflash.h>
-
-int AT91F_GetMuxStatus(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
-
- if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
- return 1;
-
- return 0;
-}
-
-void AT91F_SelectMMC(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
- /* Set Output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
-}
-
-void AT91F_SelectSPI(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
- /* Clear Output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
-}
diff --git a/board/a4m072/config.mk b/board/balloon3/Makefile
index c6ba51d..7db615e 100644
--- a/board/a4m072/config.mk
+++ b/board/balloon3/Makefile
@@ -1,9 +1,7 @@
#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Balloon3 Support
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -21,19 +19,29 @@
# MA 02111-1307 USA
#
-#
-# a4m072 board:
-#
-# Valid values for TEXT_BASE is:
-#
-# 0xFE000000 boot low
-#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := balloon3.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-ifndef TEXT_BASE
-## Standard: boot low
-TEXT_BASE = 0xFE000000
-endif
+sinclude $(obj).depend
-PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+#########################################################################
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
new file mode 100644
index 0000000..26e34e9
--- /dev/null
+++ b/board/balloon3/balloon3.c
@@ -0,0 +1,238 @@
+/*
+ * Balloon3 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <spartan3.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void balloon3_init_fpga(void);
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Init the FPGA */
+ balloon3_init_fpga();
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_stuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+}
+
+#ifdef CONFIG_CMD_USB
+int usb_board_init(void)
+{
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+#endif
+
+#if defined(CONFIG_FPGA)
+/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
+int fpga_pgm_fn(int nassert, int nflush, int cookie)
+{
+ if (nassert)
+ writel(0x80, GPCR3);
+ else
+ writel(0x80, GPSR3);
+ if (nflush)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+ return nassert;
+}
+
+/* Check GPIO83 -- INITB */
+int fpga_init_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x80000);
+}
+
+/* Check GPIO84 -- BUSY */
+int fpga_busy_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x100000);
+}
+
+/* Check GPIO111 -- DONE */
+int fpga_done_fn(int cookie)
+{
+ return readl(GPLR3) & 0x8000;
+}
+
+/* Configure GPIO104 as GPIO and deassert it */
+int fpga_pre_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
+ writel(0x100, GPCR3);
+ return 0;
+}
+
+/* Configure GPIO104 as nSKTSEL */
+int fpga_post_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
+ return 0;
+}
+
+/* Toggle RDnWR */
+int fpga_wr_fn(int nassert_write, int flush, int cookie)
+{
+ udelay(1000);
+
+ if (nassert_write)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+
+ return nassert_write;
+}
+
+/* Write program to the FPGA */
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+ writeb(data, 0x10f00000);
+ return 0;
+}
+
+/* Toggle Clock pin -- NO-OP */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+/* Toggle ChipSelect pin -- NO-OP */
+int fpga_cs_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_init_fn,
+ NULL, /* err */
+ fpga_done_fn,
+ fpga_clk_fn,
+ fpga_cs_fn,
+ fpga_wr_fn,
+ NULL, /* rdata */
+ fpga_wdata_fn,
+ fpga_busy_fn,
+ NULL, /* abort */
+ fpga_post_config_fn,
+};
+
+Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+ (void *)&balloon3_fpga_fns, 0);
+
+/* Initialize the FPGA */
+void balloon3_init_fpga(void)
+{
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+}
+#else
+void balloon3_init_fpga(void) {}
+#endif /* CONFIG_FPGA */
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
index 84ec38e..8aa7067 100644
--- a/board/colibri_pxa270/colibri_pxa270.c
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -65,28 +66,30 @@ int dram_init (void)
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (UHCHR & UHCHR_FSBIR);
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
@@ -98,14 +101,14 @@ void usb_board_init_fail(void)
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index 21eb655..c4a93f9 100644
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -28,6 +28,7 @@
#include <asm/arch/pxa-regs.h>
#include <common.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -92,8 +93,8 @@ set_led (int led, int color)
int shift = led * 2;
unsigned long mask = 0x3 << shift;
- CRADLE_LED_CLR_REG = mask; /* clear bits */
- CRADLE_LED_SET_REG = (color << shift); /* set bits */
+ writel(mask, GPCR2); /* clear bits */
+ writel((color << shift), GPSR2); /* set bits */
udelay (5000);
}
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
index 6b5cfb9..39964b6 100644
--- a/board/cradle/lowlevel_init.S
+++ b/board/cradle/lowlevel_init.S
@@ -34,10 +34,10 @@ DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
.endm
.macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
+ ldr r6, =GPCR2
ldr r7, =0
str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
+ ldr r6, =GPSR2
ldr r7, =\val
str r7, [r6]
.endm
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index 0a6c13d..6eed9ad 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -26,6 +26,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -108,23 +109,23 @@ void csb226_set_led(int led, int state)
switch(led) {
case 0: if (state==1) {
- GPCR0 |= CSB226_USER_LED0;
+ writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED0;
+ writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
}
break;
case 1: if (state==1) {
- GPCR0 |= CSB226_USER_LED1;
+ writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED1;
+ writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
}
break;
case 2: if (state==1) {
- GPCR0 |= CSB226_USER_LED2;
+ writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED2;
+ writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
}
break;
}
diff --git a/board/delta/delta.c b/board/delta/delta.c
index 68c39d2..df23076 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -28,6 +28,7 @@
#include <malloc.h>
#include <command.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -110,7 +111,7 @@ static uchar kbd_command_prefix[] = "key_cmd";
static void get_pressed_keys(uchar *s)
{
unsigned long val;
- val = GPLR3;
+ val = readl(GPLR3);
if(val & (1<<31))
*s++ = KEYBD_KP_DKIN0;
@@ -124,18 +125,18 @@ static void get_pressed_keys(uchar *s)
static void keys_init()
{
- CKENB |= CKENB_7_GPIO;
+ writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Configure GPIOs */
- GPIO127 = 0xa840; /* KP_DKIN0 */
- GPIO114 = 0xa840; /* KP_DKIN1 */
- GPIO125 = 0xa840; /* KP_DKIN2 */
- GPIO118 = 0xa840; /* KP_DKIN5 */
+ writel(0xa840, GPIO127); /* KP_DKIN0 */
+ writel(0xa840, GPIO114); /* KP_DKIN1 */
+ writel(0xa840, GPIO125); /* KP_DKIN2 */
+ writel(0xa840, GPIO118); /* KP_DKIN5 */
/* Configure GPIOs as inputs */
- GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
- GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
+ writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
+ writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
udelay(100);
}
@@ -283,11 +284,11 @@ int dram_init (void)
void i2c_init_board()
{
- CKENB |= (CKENB_4_I2C);
+ writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
/* setup I2C GPIO's */
- GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
- GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
+ writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */
+ writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */
}
/* initialize the DA9030 Power Controller */
@@ -295,20 +296,20 @@ static void init_DA9030()
{
uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
- CKENB |= CKENB_7_GPIO;
+ writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Rising Edge on EXTON to reset DA9030 */
- GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */
- GPDR0 |= (1<<17); /* GPIO17 is output */
- GSDR0 = (1<<17);
- GPCR0 = (1<<17); /* drive GPIO17 low */
- GPSR0 = (1<<17); /* drive GPIO17 high */
+ writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */
+ writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */
+ writel((1<<17), GSDR0);
+ writel((1<<17), GPCR0); /* drive GPIO17 low */
+ writel((1<<17), GPSR0); /* drive GPIO17 high */
#if CONFIG_SYS_DA9030_EXTON_DELAY
udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
#endif
- GPCR0 = (1<<17); /* drive GPIO17 low */
+ writel((1<<17), GPCR0); /* drive GPIO17 low */
/* reset the watchdog and go active (0xec) */
val = (SYS_CONTROL_A_HWRES_ENABLE |
diff --git a/board/delta/nand.c b/board/delta/nand.c
index 85a6ba2..119a587 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -26,6 +26,7 @@
#include <nand.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
#ifdef CONFIG_SYS_DFC_DEBUG1
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
@@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
+ writel(*long_buf, NDDB);
}
}
if(rest) {
@@ -120,7 +121,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
+ *long_buf = readl(NDDB);
}
}
@@ -166,8 +167,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
unsigned long dummy;
if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
+ read_buf = readl(NDDB);
+ dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -181,7 +182,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
- unsigned long cur = OSCR;
+ unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
@@ -192,7 +193,7 @@ static unsigned long get_delta(unsigned long start)
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
- unsigned long start = OSCR;
+ unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
@@ -202,14 +203,14 @@ static void wait_us(unsigned long us)
static void dfc_clear_nddb(void)
{
- NDCR &= ~NDCR_ND_RUN;
+ writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
- unsigned long ndsr, timeout, start = OSCR;
+ unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
@@ -221,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event)
* OSCR_CLK_FREQ, 1000);
while(1) {
- ndsr = NDSR;
+ ndsr = readl(NDSR);
if(ndsr & event) {
- NDSR |= event;
+ writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
@@ -243,11 +244,11 @@ static void dfc_new_cmd(void)
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
- NDSR = 0xFFF;
+ writel(0xfff, NDSR);
/* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
+ if (!(readl(NDCR) & NDCR_ND_RUN))
+ writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
@@ -357,9 +358,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
}
write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
+ writel(ndcb0, NDCB0);
+ writel(ndcb1, NDCB0);
+ writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
@@ -372,36 +373,36 @@ static void dfc_gpio_init(void)
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
-
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
-
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
+ writel(0x1, GPIO4);
+
+ writel(0x00000001, DF_ALE_nWE1);
+ writel(0x00000001, DF_ALE_nWE2);
+ writel(0x00000001, DF_nCS0);
+ writel(0x00000001, DF_nCS1);
+ writel(0x00000001, DF_nWE);
+ writel(0x00000001, DF_nRE);
+ writel(0x00000001, DF_IO0);
+ writel(0x00000001, DF_IO8);
+ writel(0x00000001, DF_IO1);
+ writel(0x00000001, DF_IO9);
+ writel(0x00000001, DF_IO2);
+ writel(0x00000001, DF_IO10);
+ writel(0x00000001, DF_IO3);
+ writel(0x00000001, DF_IO11);
+ writel(0x00000001, DF_IO4);
+ writel(0x00000001, DF_IO12);
+ writel(0x00000001, DF_IO5);
+ writel(0x00000001, DF_IO13);
+ writel(0x00000001, DF_IO6);
+ writel(0x00000001, DF_IO14);
+ writel(0x00000001, DF_IO7);
+ writel(0x00000001, DF_IO15);
+
+ writel(0x1901, DF_nWE);
+ writel(0x1901, DF_nRE);
+ writel(0x1900, DF_CLE_nOE);
+ writel(0x1901, DF_ALE_nWE1);
+ writel(0x1900, DF_INT_RnB);
}
/*
@@ -430,7 +431,7 @@ int board_nand_init(struct nand_chip *nand)
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+ writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
@@ -485,17 +486,19 @@ int board_nand_init(struct nand_chip *nand)
tRP_high = 0;
}
- NDTR0CS0 = (tCH << 19) |
+ writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
- (tRP << 0);
+ (tRP << 0),
+ NDTR0CS0);
- NDTR1CS0 = (tR << 16) |
+ writel((tR << 16) |
(tWHR << 4) |
- (tAR << 0);
+ (tAR << 0),
+ NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
@@ -512,7 +515,7 @@ int board_nand_init(struct nand_chip *nand)
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
@@ -528,7 +531,8 @@ int board_nand_init(struct nand_chip *nand)
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
+ NDCR_WRCMDREQM, /* write command request ir masked */
+ NDCR);
/* wait 10 us due to cmd buffer clear reset */
diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds
index b414079b..3eeb2a2 100644
--- a/board/eNET/u-boot.lds
+++ b/board/eNET/u-boot.lds
@@ -27,7 +27,7 @@ ENTRY(_start)
SECTIONS
{
- . = TEXT_BASE; /* Location of bootcode in flash */
+ . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
.text : { *(.text*); }
@@ -94,11 +94,11 @@ SECTIONS
* The fff0 offset of resetvec is important, however.
*/
. = 0xfffffe00;
- .start32 : AT (TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
+ .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
. = 0xf800;
- .start16 : AT (TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
+ .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
. = 0xfff0;
- .resetvec : AT (TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
+ .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
}
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 8aa7255..7a56fa2 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
-COBJS-$(CONFIG_DDR_SPD) += ddr.o
+COBJS-y += ddr.o
+COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += law.o
COBJS-y += tlb.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 48d95d6..68c63ac 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -29,7 +29,6 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
@@ -196,20 +195,6 @@ int misc_init_r(void)
return 0;
}
-phys_size_t initdram(int board_type)
-{
- phys_size_t dram_size;
-
- puts("Initializing....\n");
-
- dram_size = fsl_ddr_sdram();
-
- setup_ddr_tlbs(dram_size / 0x100000);
-
- puts(" DDR: ");
- return dram_size;
-}
-
#ifdef CONFIG_MP
void board_lmb_reserve(struct lmb *lmb)
{
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 18adf2f..2ee0188 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -8,9 +8,103 @@
#include <common.h>
#include <i2c.h>
-
+#include <hwconfig.h>
+#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+ unsigned int ctrl_num);
+
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+extern fixed_ddr_parm_t fixed_ddr_parm_1[];
+#endif
+
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ sys_info_t sysinfo;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ unsigned int lawbar1_target_id;
+
+ get_sys_info(&sysinfo);
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freqDDRBus));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((sysinfo.freqDDRBus > fixed_ddr_parm_0[i].min_freq) &&
+ (sysinfo.freqDDRBus <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs,
+ fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freqDDRBus));
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+ memcpy(&ddr_cfg_regs,
+ fixed_ddr_parm_1[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
+#endif
+
+ /*
+ * setup laws for DDR. If not interleaving, presuming half memory on
+ * DDR1 and the other half on DDR2
+ */
+ if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ LAW_TRGT_IF_DDR_INTRLV) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ } else {
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+ /* We require both controllers have identical DIMMs */
+ lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size / 2,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ lawbar1_target_id = LAW_TRGT_IF_DDR_2;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
+ ddr_size / 2,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+#else
+ lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+#endif
+ }
+ return ddr_size;
+}
static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
{
@@ -190,3 +284,38 @@ void fsl_ddr_board_options(memctl_options_t *popts,
/* Enable ZQ calibration */
popts->zq_en = 1;
}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+ int use_spd = 0;
+
+ puts("Initializing....");
+
+#ifdef CONFIG_DDR_SPD
+ /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
+ if (hwconfig_sub("fsl_ddr", "sdram")) {
+ if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
+ use_spd = 1;
+ else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
+ use_spd = 0;
+ else
+ use_spd = 1;
+ } else
+ use_spd = 1;
+#endif
+
+ if (use_spd) {
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+ } else {
+ puts("using fixed parameters\n");
+ dram_size = fixed_sdram();
+ }
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
new file mode 100644
index 0000000..4ad89ff
--- /dev/null
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#define DATARATE_800MHZ 800000000
+#define DATARATE_900MHZ 900000000
+#define DATARATE_1000MHZ 1000000000
+#define DATARATE_1200MHZ 1200000000
+#define DATARATE_1300MHZ 1300000000
+
+#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
+#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
+#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
+#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
+#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
+#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
+#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
+#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
+#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
+#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
+#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
+#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
+#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
+#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
+#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
+#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
+#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
+#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
+#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_TIMING_4 0x00000001
+#define CONFIG_SYS_DDR_TIMING_5 0x02401400
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
+#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800},
+ {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900},
+ {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000},
+ {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200},
+ {0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+ {DATARATE_800MHZ, DATARATE_900MHZ, &ddr_cfg_regs_800_2nd},
+ {DATARATE_900MHZ, DATARATE_1000MHZ, &ddr_cfg_regs_900_2nd},
+ {DATARATE_1000MHZ, DATARATE_1200MHZ, &ddr_cfg_regs_1000_2nd},
+ {DATARATE_1200MHZ, DATARATE_1300MHZ, &ddr_cfg_regs_1200_2nd},
+ {0, 0, NULL}
+};
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 59ada9c..0babd26 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@@ -22,6 +22,7 @@
#include <spd_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
+#include <asm/fsl_enet.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@@ -396,10 +397,8 @@ void ft_board_setup(void *blob, bd_t *bd)
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_setprop(blob, path,
- "phy-connection-type",
- "rgmii-rxid",
- sizeof("rgmii-rxid"));
+ fdt_fixup_phy_connection(blob, path,
+ RGMII_RXID);
}
#endif
#if defined(CONFIG_HAS_ETH1)
@@ -410,10 +409,8 @@ void ft_board_setup(void *blob, bd_t *bd)
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_setprop(blob, path,
- "phy-connection-type",
- "rgmii-rxid",
- sizeof("rgmii-rxid"));
+ fdt_fixup_phy_connection(blob, path,
+ RGMII_RXID);
}
#endif
}
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 32a87ad..51dd692 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* CREDITS: Kim Phillips contribute to LIBFDT code
@@ -15,6 +15,7 @@
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_mpc83xx_serdes.h>
+#include <asm/fsl_enet.h>
#include <spd_sdram.h>
#include <tsec.h>
#include <libfdt.h>
@@ -136,7 +137,6 @@ int board_eth_init(bd_t *bd)
static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
int phy_addr)
{
- const char *phy_type = "sgmii";
const u32 *ph;
int off;
int err;
@@ -148,8 +148,8 @@ static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
return;
}
- err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
- strlen(phy_type) + 1);
+ err = fdt_fixup_phy_connection(blob, off, SGMII);
+
if (err) {
printf("WARNING: could not set phy-connection-type for %s: "
"%s.\n", alias, fdt_strerror(err));
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 795e565..743e712 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -622,8 +622,8 @@ void ft_board_setup(void *blob, bd_t *bd)
break;
}
- err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
- "rmii");
+ err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
+
if (err < 0) {
printf("WARNING: could not set phy-connection-type "
"%s.\n", fdt_strerror(err));
diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds
deleted file mode 100644
index 9c98b2a..0000000
--- a/board/freescale/mpc8610hpcd/u-boot.lds
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2007 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-
- /* Read-only sections, merged into text segment: */
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc86xx/start.o (.text)
- arch/powerpc/cpu/mpc86xx/traps.o (.text)
- arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu.o (.text)
- arch/powerpc/cpu/mpc86xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index fee310a..092ead6 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -142,56 +142,26 @@ int first_free_busno = 0;
void pci_init_board(void)
{
+ struct fsl_pci_info pci_info[2];
+ int pcie_ep;
+ int num = 0;
+
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- struct pci_region *r = hose->regions;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
+ uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-#ifdef DEBUG
- uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
- >> MPC8641_PORBMSR_HA_SHIFT;
- uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-#endif
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
- debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
- debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- debug("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf(" PCIE1 connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
@@ -201,45 +171,22 @@ void pci_init_board(void)
+ CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
} else {
- puts("PCI-EXPRESS 1: Disabled\n");
+ puts(" PCIE1: disabled\n");
}
-}
#else
- puts("PCI-EXPRESS1: Disabled\n");
+ puts(" PCIE1: disabled\n");
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- struct pci_region *r = hose->regions;
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-}
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf(" PCIE2 connected as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
#else
- puts("PCI-EXPRESS 2: Disabled\n");
+ puts(" PCIE2: disabled\n");
#endif /* CONFIG_PCIE2 */
}
diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds
deleted file mode 100644
index 5bf0f2d..0000000
--- a/board/freescale/mpc8641hpcn/u-boot.lds
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Copyright 2006, 2007 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-
- /* Read-only sections, merged into text segment: */
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc86xx/start.o (.text)
- arch/powerpc/cpu/mpc86xx/traps.o (.text)
- arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu.o (.text)
- arch/powerpc/cpu/mpc86xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
- drivers/bios_emulator/atibios.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 84386e6..c8d7d39 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index 3412f10..2c51125 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -27,6 +27,7 @@
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -48,20 +49,21 @@ int i2c_init_board(void)
/* disable I2C controller first, otherwhise it thinks we want to */
/* talk to the slave port... */
- icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
+ icr = readl(ICR);
+ writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
/* set gpio pin low _before_ we change direction to output */
- GPCR(70) = GPIO_bit(70);
+ writel(GPIO_bit(70), GPCR(70));
/* now toggle between output=low and high-impedance */
for (i = 0; i < 20; i++) {
- GPDR(70) |= GPIO_bit(70); /* output */
+ writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
udelay(10);
- GPDR(70) &= ~GPIO_bit(70); /* input */
+ writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
udelay(10);
}
- ICR = icr;
+ writel(icr, ICR);
return 0;
}
@@ -76,7 +78,7 @@ int misc_init_r(void)
char *str;
/* determine if the software update key is pressed during startup */
- if (GPLR0 & 0x00000800) {
+ if (readl(GPLR0) & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {
diff --git a/board/nc650/Makefile b/board/jornada/Makefile
index e4006e7..1b4e192 100644
--- a/board/nc650/Makefile
+++ b/board/jornada/Makefile
@@ -1,8 +1,9 @@
#
-# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
-# (C) Copyright 2004-2006
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
+# 2004 (c) MontaVista Software, Inc.
+#
# See file CREDITS for list of people who contributed to this
# project.
#
@@ -26,14 +27,21 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o nand.o flash.o
+COBJS := jornada.o
+SOBJS := setup.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
diff --git a/board/atmel/at91rm9200ek/misc.c b/board/jornada/jornada.c
index 81de32f..fab1068 100644
--- a/board/atmel/at91rm9200ek/misc.c
+++ b/board/jornada/jornada.c
@@ -3,6 +3,8 @@
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
+ * 2004 (c) MontaVista Software, Inc.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -23,28 +25,36 @@
*/
#include <common.h>
-#include <asm/arch/AT91RM9200.h>
-#include <at91rm9200_net.h>
-#include <dm9161.h>
-#include <net.h>
+#include <SA-1100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
-int board_late_init(void)
+/* ------------------------------------------------------------------------- */
+
+int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
+ gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
+ gd->bd->bi_boot_params = 0xc0000100;
+
+
+ /*
+ * Turn on flashing.
+ * Would be nice to have some protection but
+ * that would have to be implemented in the
+ * flash init function, which isnt possible yet.
+ */
+ PPSR |= (1 << 7);
+ PPDR |= (1 << 7);
- /* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
- eth_init(gd->bd);
return 0;
}
-
-/* checks if addr is in RAM */
-int addr2ram(ulong addr)
+int dram_init(void)
{
- int result = 0;
-
- if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
- result = 1;
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return result;
+ return (0);
}
diff --git a/board/jornada/setup.S b/board/jornada/setup.S
new file mode 100644
index 0000000..885e02f
--- /dev/null
+++ b/board/jornada/setup.S
@@ -0,0 +1,210 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG 0x00
+#define MDCAS00 0x04
+#define MDCAS01 0x08
+#define MDCAS02 0x0C
+#define MSC0 0x10
+#define MSC1 0x14
+#define MECR 0x18
+#define MDREFR 0x1C
+#define MDCAS20 0x20
+#define MDCAS21 0x24
+#define MDCAS22 0x28
+#define MSC2 0x2C
+#define SMCNFG 0x30
+
+#define GPDR 0x04
+#define GPSR 0x08
+#define GPCR 0x0C
+#define GAFR 0x1C
+
+#define PPDR 0x00
+#define PPSR 0x04
+#define PPAR 0x08
+
+#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
+#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
+#define MDREFR_K0DB2 (1 << 18)
+#define MDREFR_K1DB2 (1 << 22)
+#define MDREFR_K2DB2 (1 << 26)
+
+#define MDREFR_K0RUN (1 << 17)
+#define MDREFR_K1RUN (1 << 21)
+#define MDREFR_K2RUN (1 << 25)
+
+#define MDREFR_SLFRSH (1 << 31)
+#define MDREFR_E1PIN (1 << 20)
+
+#define PSSR 0x04
+#define PSSR_DH 0x00000008
+#define POSR 0x08
+#define RCSR 0x04
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+MEM_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
+PWR_BASE: .word 0x90020000
+RST_BASE: .long 0x90030000
+PPC_BASE: .long 0x90060000
+GPIO_BASE: .long 0x90040000
+IC_BASE: .word 0x90050000
+
+cpuspeed: .word 0xa0
+/* calculated from old blob bootloader */
+mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
+mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
+mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
+mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
+msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
+msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
+mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
+mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
+mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
+mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
+mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
+msc2: .long 0x201d2959 /* msc2 0x201d2959 */
+smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
+
+pin_set_out: .long 0x37ff70
+pin_set_dir: .long 0x11480
+
+gpdr_set: .long 0x0B3A0900
+gpsr_set: .long 0x02100800
+gpcr_set: .long 0x092A0100
+gafr_set: .long 0x08600000
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* set output and direction of pins */
+ ldr r0, PPC_BASE
+ ldr r1, pin_set_out
+ str r1, [r0, #PPSR]
+ ldr r1, pin_set_dir
+ str r1, [r0, #PPDR]
+
+ /* Setting up the memory and stuff */
+ /***********************************/
+
+ ldr r0, MEM_BASE
+
+ ldr r1, mdcnfg
+ str r1, [r0, #MDCNFG]
+ ldr r1, mdcas00
+ str r1, [r0, #MDCAS00]
+ ldr r1, mdcas01
+ str r1, [r0, #MDCAS01]
+ ldr r1, mdcas02
+ str r1, [r0, #MDCAS02]
+ ldr r1, mdcas20
+ str r1, [r0, #MDCAS20]
+ ldr r1, mdcas21
+ str r1, [r0, #MDCAS21]
+ ldr r1, mdcas22
+ str r1, [r0, #MDCAS22]
+
+ /* clear kxDB2 */
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+
+ mov r4, #0x2000
+ spin: subs r4, r4, #1
+ bne spin
+
+ ldr r1, PWR_BASE
+ mov r2, #PSSR_DH
+ str r2, [r1, #PSSR]
+
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+ orr r2, r2, #MDREFR_DRI(12)
+ orr r2, r2, #MDREFR_K0DB2
+ orr r2, r2, #MDREFR_K1DB2
+ orr r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_K0RUN
+ orr r2, r2, #MDREFR_K1RUN
+ orr r2, r2, #MDREFR_K2RUN
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_SLFRSH
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_E1PIN
+ str r2, [r0, #MDREFR]
+
+ ldr r2, MEM_START
+.rept 8
+ ldr r3, [r2]
+.endr
+
+ ldr r1, msc0
+ str r1, [r0, #MSC0]
+ ldr r1, msc1
+ str r1, [r0, #MSC1]
+ ldr r1, msc2
+ str r1, [r0, #MSC2]
+ ldr r1, smcnfg
+ str r1, [r0, #SMCNFG]
+ ldr r1, mdcnfg
+ str r1, [r0, #MDCNFG]
+ ldr r1, mecr
+ str r1, [r0, #MECR]
+
+ /* enable SDRAM */
+ orr r1, r1, #0x00000001
+ str r1, [r0, #MDCNFG]
+
+ mov pc, lr
diff --git a/board/jornada/u-boot.lds b/board/jornada/u-boot.lds
new file mode 100644
index 0000000..de6101e
--- /dev/null
+++ b/board/jornada/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/sa1100/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ _end = .;
+}
diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk
index 4283c3e..18b2883 100644
--- a/board/karo/tx25/config.mk
+++ b/board/karo/tx25/config.mk
@@ -1,5 +1,5 @@
ifdef CONFIG_NAND_SPL
CONFIG_SYS_TEXT_BASE = 0x810c0000
else
-CONFIG_SYS_TEXT_BASE = 0x81fc0000
+CONFIG_SYS_TEXT_BASE = 0x81200000
endif
diff --git a/board/logicpd/imx27lite/config.mk b/board/logicpd/imx27lite/config.mk
index 7f22154..018d920 100644
--- a/board/logicpd/imx27lite/config.mk
+++ b/board/logicpd/imx27lite/config.mk
@@ -1 +1,5 @@
+# with relocation CONFIG_SYS_TEXT_BASE can be anything, and making it 0
+# makes relative and absolute relocation fixups interchangeable.
+#CONFIG_SYS_TEXT_BASE = 0
+
CONFIG_SYS_TEXT_BASE = 0xc0000000
diff --git a/board/logicpd/imx31_litekit/config.mk b/board/logicpd/imx31_litekit/config.mk
index 0131edf..a7887ba 100644
--- a/board/logicpd/imx31_litekit/config.mk
+++ b/board/logicpd/imx31_litekit/config.mk
@@ -1 +1 @@
-CONFIG_SYS_TEXT_BASE = 0x87f00000
+CONFIG_SYS_TEXT_BASE = 0xa0000000
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
index 2ac622d..a07ba0e 100644
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -31,12 +31,18 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init (void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
+void
+dram_init_banksize (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
int board_init (void)
{
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
diff --git a/board/nc650/flash.c b/board/nc650/flash.c
deleted file mode 100644
index 8a0eab5..0000000
--- a/board/nc650/flash.c
+++ /dev/null
@@ -1,542 +0,0 @@
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#undef DEBUG
-
-#include <common.h>
-#include <mpc8xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
-#define CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
- OR_SCY_2_CLK | OR_EHTR | OR_BI)
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Protection Flags:
- */
-#define FLAG_PROTECT_SET 0x01
-#define FLAG_PROTECT_CLEAR 0x02
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH8
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH ushort
-#define FLASH_PORT_WIDTHV vu_short
-#elif FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH ulong
-#define FLASH_PORT_WIDTHV vu_long
-#else /* FLASH_PORT_WIDTH8 */
-#define FLASH_PORT_WIDTH uchar
-#define FLASH_PORT_WIDTHV vu_char
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPWV * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
- int scy, trlx, flash_or_timing, clk_diff;
-
- scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
- if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
- trlx = OR_TRLX;
- scy *= 2;
- } else
- trlx = 0;
-
- /* We assume that each 10MHz of bus clock require 1-clk SCY
- * adjustment.
- */
- clk_diff = (gd->bus_clk / 1000000) - 50;
-
- /* We need proper rounding here. This is what the "+5" and "-5"
- * are here for.
- */
- if (clk_diff >= 0)
- scy += (clk_diff + 5) / 10;
- else
- scy += (clk_diff - 5) / 10;
-
- /* For bus frequencies above 50MHz, we want to use relaxed
- * timing (OR_TRLX).
- */
- if (gd->bus_clk >= 50000000)
- trlx = OR_TRLX;
- else
- trlx = 0;
-
- if (trlx)
- scy /= 2;
-
- if (scy > 0xf)
- scy = 0xf;
- if (scy < 1)
- scy = 1;
-
- flash_or_timing = (scy << 4) | trlx |
- (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
-#endif
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- /* Remap FLASH according to real size */
-#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-#else
- memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
-#endif
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- (void) flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00020000);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F320J3A:
- printf ("28F320J3A\n");
- break;
- case FLASH_28F640J3A:
- printf ("28F640J3A\n");
- break;
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (FPWV * addr, flash_info_t * info)
-{
- FPW value;
-
- addr[0] = (FPW) 0x00900090;
-
- value = addr[0];
-
- debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
-
- switch (value) {
- case (FPW) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
-#ifdef FLASH_PORT_WIDTH8
- value = addr[2]; /* device ID */
-#else
- value = addr[1]; /* device ID */
-#endif
-
- debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
-
- switch (value) {
- case (FPW) INTEL_ID_28F320J3A:
- info->flash_id += FLASH_28F320J3A;
- info->sector_count = 32;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (FPW) INTEL_ID_28F640J3A:
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 0x01000000;
- break; /* => 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- rcode = 1;
- break;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp;
- FPW data;
-
- int i, l, rc, port_width;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
- wp = (addr & ~1);
- port_width = 2;
-#elif defined(FLASH_PORT_WIDTH32)
- wp = (addr & ~3);
- port_width = 4;
-#else
- wp = addr;
- port_width = 1;
-#endif
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_data (info, wp, data)) != 0) {
- return (rc);
- }
- wp += port_width;
- cnt -= port_width;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < port_width; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_data (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
-
- while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
- *addr = (FPW) 0x00FF00FF; /* restore read mode */
-
- return (0);
-}
diff --git a/board/nc650/nand.c b/board/nc650/nand.c
deleted file mode 100644
index 7dca97f..0000000
--- a/board/nc650/nand.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
- * (C) Copyright 2006 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-
-#if defined(CONFIG_IDS852_REV1)
-/*
- * hardware specific access to control-lines
- */
-static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- this->IO_ADDR_W += 2;
- else
- this->IO_ADDR_W -= 2;
- if ( ctrl & NAND_ALE )
- this->IO_ADDR_W += 1;
- else
- this->IO_ADDR_W -= 1;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-#elif defined(CONFIG_IDS852_REV2)
-/*
- * hardware specific access to control-lines
- */
-static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- writeb(0, (volatile __u8 *) this->IO_ADDR_W + 0xa);
- else
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
- if ( ctrl & NAND_ALE )
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x9);
- else
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
- if ( ctrl & NAND_NCE )
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8);
- else
- writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0xc);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-#else
-#error Unknown IDS852 module revision
-#endif
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - eccm.ode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-
- nand->cmd_ctrl = nc650_hwcontrol;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->chip_delay = 12;
-/* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
- return 0;
-}
-#endif
diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
deleted file mode 100644
index 056230d..0000000
--- a/board/nc650/nc650.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/*
- * Memory Controller Using
- *
- * CS0 - Flash memory (0x40000000)
- * CS3 - SDRAM (0x00000000}
- */
-
-/* ------------------------------------------------------------------------- */
-
-#define _not_used_ 0xffffffff
-
-const uint sdram_table[] = {
- /* single read. (offset 0 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47,
-
- /* MRS initialization (offset 5) */
-
- 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
-
- /* burst read. (offset 8 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* single write. (offset 18 in upm RAM) */
- 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* burst write. (offset 20 in upm RAM) */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* refresh. (offset 30 in upm RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* exception. (offset 3c in upm RAM) */
- 0x7ffffc07, _not_used_, _not_used_, _not_used_
-};
-
-const uint nand_flash_table[] = {
- /* single read. (offset 0 in upm RAM) */
- 0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
- 0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
-
- /* burst read. (offset 8 in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
-
- /* single write. (offset 18 in upm RAM) */
- 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
- 0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
-
- /* burst write. (offset 20 in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
-
- /* refresh. (offset 30 in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
-
- /* exception. (offset 3c in upm RAM) */
- 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
-};
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-#if !defined(CONFIG_CP850)
- puts ("Board: NC650");
-#else
- puts ("Board: CP850");
-#endif
-#if defined(CONFIG_IDS852_REV1)
- puts (" with IDS852 rev 1 module\n");
-#elif defined(CONFIG_IDS852_REV2)
- puts (" with IDS852 rev 2 module\n");
-#endif
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size8, size9;
- long int size_b0 = 0;
- unsigned long reg;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /*
- * Preliminary prescaler for refresh (depends on number of
- * banks): This value is selected for four cycles every 62.4 us
- * with two SDRAM banks or four cycles every 31.2 us with one
- * bank. It will be adjusted after memory sizing.
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
- memctl->memc_mar = 0x00000088;
-
- /*
- * Map controller bank 1 to the SDRAM bank at
- * preliminary address - these have to be modified after the
- * SDRAM size has been determined.
- */
- memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */
- udelay (200);
- memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */
- udelay (200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /*
- * Check Bank 0 Memory Size for re-configuration
- *
- * try 8 column mode
- */
- size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- /*
- * try 9 column mode
- */
- size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
-
- udelay (1000);
-
- if (size8 < size9) {
- size_b0 = size9;
- } else {
- size_b0 = size8;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
- udelay (500);
- }
-
- /*
- * Adjust refresh rate depending on SDRAM type, both banks.
- * For types > 128 MBit leave it at the current (fast) rate
- */
- if ((size_b0 < 0x02000000)) {
- /* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
- udelay (1000);
- }
-
- /*
- * Final mapping
- */
-
- memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
- memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
- /* adjust refresh rate depending on SDRAM type, one bank */
- reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
- memctl->memc_mptpr = reg;
-
- udelay (10000);
-
- /* Configure UPMB for NAND flash access */
- upmconfig (UPMB, (uint *) nand_flash_table,
- sizeof (nand_flash_table) / sizeof (uint));
-
- memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND;
-
- return (size_b0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-
-
-#if defined(CONFIG_CP850)
-
-#define DPRAM_VARNAME "KP850DIP"
-#define PARAM_ADDR 0x7C0
-#define NAME_ADDR 0x7F8
-#define BOARD_NAME "KP01"
-#define DEFAULT_LB "241111"
-
-int misc_init_r(void)
-{
- int iCompatMode = 0;
- char *pParam = NULL;
- char *envlb;
-
- /*
- First byte in CPLD read address space signals compatibility mode
- 0 - cp850
- 1 - kp852
- */
- pParam = (char*)(CONFIG_SYS_CPLD_BASE);
- if( *pParam != 0)
- iCompatMode = 1;
-
- if ( iCompatMode != 0) {
- /*
- In KP852 compatibility mode we have to write to
- DPRAM as early as possible the binary coded
- line config and board name.
- The line config is derived from the environment
- variable DPRAM_VARNAME by converting from ASCII
- to binary per character.
- */
- if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
- setenv( DPRAM_VARNAME, DEFAULT_LB);
- envlb = DEFAULT_LB;
- }
-
- /* Status string */
- printf("Mode: KP852(LB=%s)\n", envlb);
-
- /* copy appl init */
- pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
- while (*envlb) {
- *(pParam++) = *(envlb++) - '0';
- }
- *pParam = '\0';
-
- /* copy board id */
- pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
- strcpy( pParam, BOARD_NAME);
- } else {
- puts("Mode: CP850\n");
- }
-
- return 0;
-}
-#endif
diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds
deleted file mode 100644
index e89a9bc..0000000
--- a/board/nc650/u-boot.lds
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug
deleted file mode 100644
index 770adf7..0000000
--- a/board/nc650/u-boot.lds.debug
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/timll/devkit8000/config.mk b/board/palmld/Makefile
index cb2cf8f..bcb014d 100644
--- a/board/timll/devkit8000/config.mk
+++ b/board/palmld/Makefile
@@ -1,15 +1,7 @@
#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
+# Palm LifeDrive Support
#
-# (C) Copyright 2009
-# Frederik Kriewitz <frederik@kriewitz.eu>
-#
-# DevKit8000 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -26,10 +18,32 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-# Physical Address:
-# 8000'0000 (bank0)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := palmld.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/palmld/config.mk b/board/palmld/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/palmld/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/zipitz2/lowlevel_init.S b/board/palmld/lowlevel_init.S
index 82a52e8..e3382ee 100644
--- a/board/zipitz2/lowlevel_init.S
+++ b/board/palmld/lowlevel_init.S
@@ -1,9 +1,8 @@
/*
- * Aeronix Zipit Z2 Lowlevel Hardware Initialization
+ * Palm LifeDrive Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
- *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -31,6 +30,12 @@
.globl lowlevel_init
lowlevel_init:
pxa_gpio_setup
+
+ /* Enable GPIO reset */
+ ldr r0, =PCFR
+ mov r1, #0x30
+ str r1, [r0]
+
pxa_wait_ticks 0x8000
pxa_mem_setup
pxa_wakeup
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
new file mode 100644
index 0000000..4f0087e
--- /dev/null
+++ b/board/palmld/palmld.c
@@ -0,0 +1,69 @@
+/*
+ * Palm LifeDrive Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x7, PWM_CTRL0);
+ writel(0x16c, PWM_PERVAL0);
+ writel(0x11a, PWM_PWDUTY0);
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
diff --git a/board/vpac270/u-boot.lds b/board/palmld/u-boot.lds
index 58c371d..fb4358b 100644
--- a/board/vpac270/u-boot.lds
+++ b/board/palmld/u-boot.lds
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -36,7 +36,7 @@ SECTIONS
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
@@ -44,12 +44,13 @@ SECTIONS
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
new file mode 100644
index 0000000..20ac4e1
--- /dev/null
+++ b/board/palmtc/Makefile
@@ -0,0 +1,49 @@
+#
+# Palm Tungsten|C Support
+#
+# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := palmtc.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/palmtc/config.mk b/board/palmtc/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/palmtc/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/vpac270/lowlevel_init.S b/board/palmtc/lowlevel_init.S
index ec0d12c..74050dc 100644
--- a/board/vpac270/lowlevel_init.S
+++ b/board/palmtc/lowlevel_init.S
@@ -1,9 +1,8 @@
/*
- * Voipac PXA270 Lowlevel Hardware Initialization
+ * Palm Tungsten|C Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
- *
* See file CREDITS for list of people who contributed to this
* project.
*
diff --git a/board/atmel/at91rm9200ek/partition.c b/board/palmtc/palmtc.c
index 990cbcf..04cb33e 100644
--- a/board/atmel/at91rm9200ek/partition.c
+++ b/board/palmtc/palmtc.c
@@ -1,4 +1,7 @@
/*
+ * Palm Tungsten|C Support
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -14,25 +17,43 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
- *
*/
+
#include <common.h>
-#include <config.h>
-#include <asm/hardware.h>
-#include <dataflash.h>
-
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
-};
-
-/*define the area offsets*/
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
- {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
- {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
-};
+#include <command.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* Arch number of Palm Tungsten|C */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
+
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x5f, PWM_CTRL1);
+ writel(0x3ff, PWM_PERVAL1);
+ writel(892, PWM_PWDUTY1);
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
diff --git a/board/palmtc/u-boot.lds b/board/palmtc/u-boot.lds
new file mode 100644
index 0000000..fb4358b
--- /dev/null
+++ b/board/palmtc/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ _end = .;
+}
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index a54a95d..4ab8bd4 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -33,6 +33,7 @@
#include <common.h>
#include <netdev.h>
#include <command.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -56,14 +57,14 @@ int board_init (void)
/* set PWM for LCD */
/* a value that works is 60Hz, 77% duty cycle */
- CKEN |= CKEN0_PWM0;
- PWM_CTRL0 = 0x3f;
- PWM_PERVAL0 = 0x3ff;
- PWM_PWDUTY0 = 792;
+ writel(readl(CKEN) | CKEN0_PWM0, CKEN);
+ writel(0x3f, PWM_CTRL0);
+ writel(0x3ff, PWM_PERVAL0);
+ writel(792, PWM_PWDUTY0);
/* clear reset to AC97 codec */
- CKEN |= CKEN2_AC97;
- GCR = GCR_COLD_RST;
+ writel(readl(CKEN) | CKEN2_AC97, CKEN);
+ writel(GCR_COLD_RST, GCR);
/* enable LCD backlight */
/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
@@ -102,11 +103,11 @@ int dram_init (void)
void delay_c(void)
{
/* reset OSCR to 0 */
- OSCR = 0;
- while(OSCR > 0x10000)
+ writel(0, OSCR);
+ while (readl(OSCR) > 0x10000)
;
- while(OSCR < 0xd4000)
+ while (readl(OSCR) < 0xd4000)
;
}
@@ -114,12 +115,12 @@ void blink_c(void)
{
int led_bit = (1<<10);
- GPDR0 = led_bit;
- GPCR0 = led_bit;
+ writel(led_bit, GPDR0);
+ writel(led_bit, GPCR0);
delay_c();
- GPSR0 = led_bit;
+ writel(led_bit, GPSR0);
delay_c();
- GPCR0 = led_bit;
+ writel(led_bit, GPCR0);
}
int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 54b2d0b..d954d2f 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -206,100 +206,45 @@ int first_free_busno = 0;
void pci_init_board(void)
{
+ struct fsl_pci_info pci_info[2];
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
+ uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
+ int pcie_ep;
+ int num = 0;
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- struct pci_region *r = hose->regions;
-#ifdef DEBUG
- uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
- >> MPC8641_PORBMSR_HA_SHIFT;
- uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-#endif
- if ((io_sel == 2 || io_sel == 3 || io_sel == 5
- || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
- && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
- debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
- debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- debug("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
+ int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf(" PCIE1 connected as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- puts("PCI-EXPRESS 1: Disabled\n");
+ puts(" PCIE1: disabled\n");
}
-}
#else
- puts("PCI-EXPRESS1: Disabled\n");
+ puts(" PCIE1: disabled\n");
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- struct pci_region *r = hose->regions;
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-}
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+ printf(" PCIE2 connected as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
#else
- puts("PCI-EXPRESS 2: Disabled\n");
+ puts(" PCIE2: disabled\n");
#endif /* CONFIG_PCIE2 */
-
}
diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds
deleted file mode 100644
index 4cea3b3..0000000
--- a/board/sbc8641d/u-boot.lds
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2006, 2007 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-
- /* Read-only sections, merged into text segment: */
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- arch/powerpc/cpu/mpc86xx/start.o (.text)
- arch/powerpc/cpu/mpc86xx/traps.o (.text)
- arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
- arch/powerpc/cpu/mpc86xx/cpu.o (.text)
- arch/powerpc/cpu/mpc86xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
- lib/zlib.o (.text)
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
- _end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index 7e9a2c7..e684ba2 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -71,7 +71,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#ifdef CONFIG_PCIE1
- SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
#else /* !CONFIG_PCIE1 */
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
#endif /* CONFIG_PCIE1 */
@@ -79,7 +79,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
#ifdef CONFIG_PCIE1
- SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
#endif /* CONFIG_PCIE */
};
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 71fe3ab..75dd348 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
@@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M PCI express MEM Second half
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
@@ -155,7 +155,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 9: 16M Non-cacheable, guarded
* 0xef000000 16M PCI express IO
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
@@ -205,7 +205,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 6: 256M Non-cacheable, guarded
* 0xc0000000 256M PCI express MEM First half
*/
- SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+ SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index dda2cb6..2c3885f 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -38,6 +38,7 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#include <ioports.h>
#include <flash.h>
#include <libfdt.h>
@@ -534,7 +535,6 @@ void local_bus_init (void)
/*
* Initialize PCI Devices, report devices found.
*/
-static int first_free_busno;
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
@@ -544,144 +544,77 @@ static struct pci_controller pci1_hose;
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-static inline void init_pci1(void)
+void pci_init_board (void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_PCI1
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
-
- /* PORDEVSR[15] */
- uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
- /* PORDEVSR[14] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- /* PORPLLSR[16] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+ struct fsl_pci_info pci_info[2];
+ int first_free_busno = 0;
+ int num = 0;
+ int pcie_ep;
+ __maybe_unused int pcie_configured;
- int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ __maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+#ifdef CONFIG_PCI1
+ uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
+ uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n",
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333333) ? "33" :
(pci_speed == 66666666) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
+ pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
-
- /* outbound memory */
- pci_set_region (r++,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region (r++,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- printf (" PCI on bus %02x..%02x\n",
- hose->first_busno, hose->last_busno);
-
- first_free_busno = hose->last_busno + 1;
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
#ifdef CONFIG_PCIX_CHECK
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
+ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
ushort reg16 =
PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- uint dev = PCI_BDF(hose->first_busno, 0, 0);
+ uint dev = PCI_BDF(0, 0, 0);
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
puts ("PCI-X will only work at 66 MHz\n");
- pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
- reg16);
+ pci_write_config_word(dev, PCIX_COMMAND, reg16);
}
#endif
} else {
- puts ("PCI1: disabled\n");
+ printf(" PCI1: disabled\n");
}
-#else /* !CONFIG_PCI1 */
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
-#endif /* CONFIG_PCI1 */
-}
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
-static inline void init_pcie1(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCIE1
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep;
- struct pci_region *r = hose->regions;
-
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR);
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("PCIe: %s, base address %x",
- pcie_ep ? "Endpoint" : "Root complex", (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (", with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- puts ("\n");
-
- /* outbound memory */
- pci_set_region (r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region (r++,
- CONFIG_SYS_PCIE1_IO_BASE,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- printf (" PCIe on bus %02x..%02x\n",
- hose->first_busno, hose->last_busno);
-
- first_free_busno = hose->last_busno + 1;
-
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf(" PCIE1 connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf ("PCIe: disabled\n");
+ printf(" PCIE1: disabled\n");
}
-#else /* !CONFIG_PCIE1 */
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
#endif /* CONFIG_PCIE1 */
}
-void pci_init_board (void)
-{
- init_pci1();
- init_pcie1();
-}
-
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup (void *blob, bd_t *bd)
{
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 8c11456..0c67367 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -34,6 +34,7 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,7 +45,7 @@ extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
-#if CONFIG_POLARIS
+#if CONFIG_MK_POLARIS
#define BOOT_CONSOLE "serial_stuart"
#else
#define BOOT_CONSOLE "serial_ffuart"
@@ -57,25 +58,27 @@ extern struct serial_device serial_stuart_device;
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(RH_A_NPS);
- UHCRHDA |= RH_A_PSM;
+ writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+ writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
return 0;
}
@@ -87,14 +90,14 @@ void usb_board_init_fail(void)
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index c991ee2..ce4cb78 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -26,7 +26,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <mxc_gpio.h>
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
index c6f4c7c..c359917 100644
--- a/board/vpac270/Makefile
+++ b/board/vpac270/Makefile
@@ -1,10 +1,7 @@
-
#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Voipac PXA270 Support
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -27,17 +24,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := vpac270.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
deleted file mode 100644
index 0f10662..0000000
--- a/board/vpac270/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 18e47e2..43bbdff 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -1,16 +1,7 @@
/*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ * Voipac PXA270 Support
*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -31,29 +22,24 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-/* ------------------------------------------------------------------------- */
-
/*
* Miscelaneous platform dependent initialisations
*/
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-struct serial_device *default_serial_console (void)
+int board_init(void)
{
- return &serial_ffuart_device;
-}
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
-int board_init (void)
-{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
- /* arch number of vpac270 */
+ /* Arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
/* adress of boot parameters */
@@ -62,41 +48,58 @@ int board_init (void)
return 0;
}
-int dram_init (void)
+struct serial_device *default_serial_console(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ return &serial_ffuart_device;
+}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return 0;
+#ifdef CONFIG_RAM_256M
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
}
+#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
@@ -108,17 +111,18 @@ void usb_board_init_fail(void)
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
+#endif
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
index fe4b6a9..6e41ea6 100644
--- a/board/wepep250/wepep250.c
+++ b/board/wepep250/wepep250.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,13 +34,13 @@ int board_init (void)
* Setup GPIO stuff to get serial working
*/
#if defined( CONFIG_FFUART )
- GPDR1 = 0x80;
- GAFR1_L = 0x8010;
+ writel(0x80, GPDR1);
+ writel(0x8010, GAFR1_L);
#elif defined( CONFIG_BTUART )
- GPDR1 = 0x800;
- GAFR1_L = 0x900000;
+ writel(0x800, GPDR1);
+ writel(0x900000, GAFR1_L);
#endif
- PSSR = 0x20;
+ writel(0x20, PSSR);
return 0;
}
diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile
index 2673835..8d452de 100644
--- a/board/zipitz2/Makefile
+++ b/board/zipitz2/Makefile
@@ -29,17 +29,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := zipitz2.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/zipitz2/config.mk b/board/zipitz2/config.mk
deleted file mode 100644
index 0f10662..0000000
--- a/board/zipitz2/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
index 14d1d76..9e6a0d5 100644
--- a/board/zipitz2/zipitz2.c
+++ b/board/zipitz2/zipitz2.c
@@ -28,6 +28,7 @@
#include <serial.h>
#include <asm/arch/hardware.h>
#include <spi.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,10 +44,11 @@ inline void lcd_start(void) {};
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
- /* arch number of Lubbock-Board */
+ /* arch number of Z2 */
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
/* adress of boot parameters */
@@ -58,24 +60,23 @@ int board_init (void)
return 0;
}
-int board_late_init(void)
+struct serial_device *default_serial_console (void)
{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
+ return &serial_stuart_device;
}
-struct serial_device *default_serial_console (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
{
- return &serial_stuart_device;
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_SPI
@@ -129,24 +130,24 @@ void zipitz2_spi_sda(int set)
{
/* GPIO 13 */
if (set)
- GPSR0 = (1 << 13);
+ writel((1 << 13), GPSR0);
else
- GPCR0 = (1 << 13);
+ writel((1 << 13), GPCR0);
}
void zipitz2_spi_scl(int set)
{
/* GPIO 22 */
if (set)
- GPCR0 = (1 << 22);
+ writel((1 << 22), GPCR0);
else
- GPSR0 = (1 << 22);
+ writel((1 << 22), GPSR0);
}
unsigned char zipitz2_spi_read(void)
{
/* GPIO 40 */
- return !!(GPLR1 & (1 << 8));
+ return !!(readl(GPLR1) & (1 << 8));
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -158,13 +159,13 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
void spi_cs_activate(struct spi_slave *slave)
{
/* GPIO 88 low */
- GPCR2 = (1 << 24);
+ writel((1 << 24), GPCR2);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* GPIO 88 high */
- GPSR2 = (1 << 24);
+ writel((1 << 24), GPSR2);
}
@@ -176,20 +177,20 @@ void lcd_start(void)
unsigned char dummy[3] = { 0, 0, 0 };
/* PWM2 AF */
- GAFR0_L |= 0x00800000;
+ writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
/* Enable clock to all PWM */
- CKEN |= 0x3;
+ writel(readl(CKEN) | 0x3, CKEN);
/* Configure PWM2 */
- PWM_CTRL2 = 0x4f;
- PWM_PWDUTY2 = 0x2ff;
- PWM_PERVAL2 = 792;
+ writel(0x4f, PWM_CTRL2);
+ writel(0x2ff, PWM_PWDUTY2);
+ writel(792, PWM_PERVAL2);
/* Toggle the reset pin to reset the LCD */
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(100000);
- GPCR0 = (1 << 19);
+ writel((1 << 19), GPCR0);
udelay(20000);
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(20000);
/* Program the LCD init sequence */
@@ -208,6 +209,6 @@ void lcd_start(void)
udelay(lcd_data[i].mdelay * 1000);
}
- GPSR0 = (1 << 11);
+ writel((1 << 11), GPSR0);
}
#endif
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 7cad1ac..71d18a6 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -21,6 +21,7 @@
*/
#include <common.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NAND)
@@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
+ writel(*long_buf, NDDB);
}
}
if(rest) {
@@ -125,7 +126,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
+ *long_buf = readl(NDDB);
}
}
@@ -171,8 +172,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
unsigned long dummy;
if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
+ read_buf = readl(NDDB);
+ dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -186,7 +187,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
- unsigned long cur = OSCR;
+ unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
@@ -197,7 +198,7 @@ static unsigned long get_delta(unsigned long start)
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
- unsigned long start = OSCR;
+ unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
@@ -207,14 +208,14 @@ static void wait_us(unsigned long us)
static void dfc_clear_nddb(void)
{
- NDCR &= ~NDCR_ND_RUN;
+ writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
- unsigned long ndsr, timeout, start = OSCR;
+ unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
@@ -226,9 +227,9 @@ static unsigned long dfc_wait_event(unsigned long event)
* OSCR_CLK_FREQ, 1000);
while(1) {
- ndsr = NDSR;
+ ndsr = readl(NDSR);
if(ndsr & event) {
- NDSR |= event;
+ writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
@@ -248,11 +249,11 @@ static void dfc_new_cmd(void)
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
- NDSR = 0xFFF;
+ writel(0xFFF, NDSR);
/* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
+ if (!(readl(NDCR) & NDCR_ND_RUN))
+ writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
@@ -362,9 +363,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
}
write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
+ writel(ndcb0, NDCB0);
+ writel(ndcb1, NDCB0);
+ writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
@@ -377,36 +378,36 @@ static void dfc_gpio_init(void)
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
-
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
-
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
+ writel(0x1, GPIO4);
+
+ writel(0x00000001, DF_ALE_nWE1);
+ writel(0x00000001, DF_ALE_nWE2);
+ writel(0x00000001, DF_nCS0);
+ writel(0x00000001, DF_nCS1);
+ writel(0x00000001, DF_nWE);
+ writel(0x00000001, DF_nRE);
+ writel(0x00000001, DF_IO0);
+ writel(0x00000001, DF_IO8);
+ writel(0x00000001, DF_IO1);
+ writel(0x00000001, DF_IO9);
+ writel(0x00000001, DF_IO2);
+ writel(0x00000001, DF_IO10);
+ writel(0x00000001, DF_IO3);
+ writel(0x00000001, DF_IO11);
+ writel(0x00000001, DF_IO4);
+ writel(0x00000001, DF_IO12);
+ writel(0x00000001, DF_IO5);
+ writel(0x00000001, DF_IO13);
+ writel(0x00000001, DF_IO6);
+ writel(0x00000001, DF_IO14);
+ writel(0x00000001, DF_IO7);
+ writel(0x00000001, DF_IO15);
+
+ writel(0x1901, DF_nWE);
+ writel(0x1901, DF_nRE);
+ writel(0x1900, DF_CLE_nOE);
+ writel(0x1901, DF_ALE_nWE1);
+ writel(0x1900, DF_INT_RnB);
}
/*
@@ -435,7 +436,7 @@ int board_nand_init(struct nand_chip *nand)
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+ writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
@@ -490,17 +491,19 @@ int board_nand_init(struct nand_chip *nand)
tRP_high = 0;
}
- NDTR0CS0 = (tCH << 19) |
+ writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
- (tRP << 0);
+ (tRP << 0),
+ NDTR0CS0);
- NDTR1CS0 = (tR << 16) |
+ writel((tR << 16) |
(tWHR << 4) |
- (tAR << 0);
+ (tAR << 0),
+ NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
@@ -517,7 +520,7 @@ int board_nand_init(struct nand_chip *nand)
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
@@ -533,7 +536,8 @@ int board_nand_init(struct nand_chip *nand)
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
+ NDCR_WRCMDREQM, /* write command request ir masked */
+ NDCR);
/* wait 10 us due to cmd buffer clear reset */
diff --git a/boards.cfg b/boards.cfg
index 3a965e9..0f3292f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -3,9 +3,7 @@
#
# Syntax:
# white-space separated list of entries;
-# each entry has the following fields:
-#
-# Targetname Architecture CPU Boardname Vendor SoC
+# each entry has the fields documented below.
#
# Unused fields can be specified as "-", or omitted if they
# are the last field on the line.
@@ -13,6 +11,16 @@
# Lines starting with '#' are comments.
# Blank lines are ignored.
#
+# The options field takes the form:
+# <board config name>[:comma separated config options]
+# Each config option has the form (value defaults to "1"):
+# option[=value]
+# So if you have:
+# FOO:HAS_BAR,BAZ=64
+# The file include/configs/FOO.h will be used, and these defines created:
+# #define CONFIG_HAS_BAR 1
+# #define CONFIG_BAZ 64
+#
# To keep the list sorted, use something like
#
# :.,$! sort -f -k2,2 -k3,3 -k6,6 -k5,5 -k1,1
@@ -46,20 +54,28 @@ pm9263 arm arm926ejs - ronetix at91
suen3 arm arm926ejs km_arm keymile kirkwood
rd6281a arm arm926ejs - Marvell kirkwood
jadecpu arm arm926ejs jadecpu syteco mb86r0x
-mx51evk arm armv7 mx51evk freescale mx51
-vision2 arm armv7 vision2 ttcontrol mx51
+mx51evk arm armv7 mx51evk freescale mx5
+vision2 arm armv7 vision2 ttcontrol mx5
actux1 arm ixp
actux2 arm ixp
actux3 arm ixp
actux4 arm ixp
ixdp425 arm ixp
+balloon3 arm pxa
cerf250 arm pxa
cradle arm pxa
csb226 arm pxa
delta arm pxa
innokom arm pxa
lubbock arm pxa
+palmld arm pxa
+palmtc arm pxa
pleb2 arm pxa
+polaris arm pxa trizepsiv - - trizepsiv:POLARIS
+trizepsiv arm pxa
+vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M
+vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M
+vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M
xaeniax arm pxa
xm250 arm pxa
zipitz2 arm pxa
@@ -69,6 +85,7 @@ dnp1110 arm sa1100
gcplus arm sa1100
lart arm sa1100
shannon arm sa1100
+jornada arm sa1100
mimc200 avr32 at32ap - mimc at32ap700x
ip04 blackfin blackfin
eNET i386 i386 - - sc520
@@ -244,7 +261,6 @@ TQM866M powerpc mpc8xx tqm8xx tqc
TQM885D powerpc mpc8xx tqm8xx tqc
AMX860 powerpc mpc8xx amx860 westel
AdderII powerpc mpc8xx adder - - Adder:MPC852T
-CP850 powerpc mpc8xx nc650 - - NC650:CP850=1,IDS852_REV2=1
IVML24 powerpc mpc8xx ivm - - IVML24:IVML24_16M
IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M
NETTA powerpc mpc8xx netta - - NETTA
@@ -344,7 +360,7 @@ modnet50 arm arm720t
lpc2292sodimm arm arm720t - - lpc2292
eb_cpux9k2 arm arm920t - BuS at91
at91rm9200dk arm arm920t - atmel at91rm9200
-at91rm9200ek arm arm920t - atmel at91rm9200
+at91rm9200ek arm arm920t - atmel at91
sbc2410x arm arm920t - - s3c24x0
smdk2400 arm arm920t - samsung s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
@@ -603,8 +619,6 @@ IVML24_128 powerpc mpc8xx ivm - - IVML24:IVML24_32M
IVML24_256 powerpc mpc8xx ivm - - IVML24:IVML24_64M
IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M
IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M
-NC650_Rev1 powerpc mpc8xx nc650 - - NC650:IDS852_REV2=1
-NC650_Rev2 powerpc mpc8xx nc650 - - NC650:IDS852_REV1=1
NETTA2_V2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=2
NETTA_6412 powerpc mpc8xx netta - - NETTA:NETTA_6412=1
NETTA_ISDN powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index e50c9de..0ad310f 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -163,6 +163,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
char *devstr = getenv ("fpga");
char *datastr = getenv ("fpgadata");
int rc = FPGA_FAIL;
+ int wrong_parms = 0;
#if defined (CONFIG_FIT)
const char *fit_uname = NULL;
ulong fit_addr;
@@ -229,6 +230,32 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
break;
}
+ if (dev == FPGA_INVALID_DEVICE) {
+ puts("FPGA device not specified\n");
+ op = FPGA_NONE;
+ }
+
+ switch (op) {
+ case FPGA_NONE:
+ case FPGA_INFO:
+ break;
+ case FPGA_LOAD:
+ case FPGA_LOADB:
+ case FPGA_DUMP:
+ if (!fpga_data || !data_size)
+ wrong_parms = 1;
+ break;
+ case FPGA_LOADMK:
+ if (!fpga_data)
+ wrong_parms = 1;
+ break;
+ }
+
+ if (wrong_parms) {
+ puts("Wrong parameters for FPGA request\n");
+ op = FPGA_NONE;
+ }
+
switch (op) {
case FPGA_NONE:
return cmd_usage(cmdtp);
@@ -342,17 +369,18 @@ static int fpga_get_op (char *opstr)
}
U_BOOT_CMD (fpga, 6, 1, do_fpga,
- "loadable FPGA image support",
- "fpga [operation type] [device number] [image address] [image size]\n"
- "fpga operations:\n"
- "\tinfo\tlist known device information\n"
- "\tload\tLoad device from memory buffer\n"
- "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
- "\tloadmk\tLoad device generated with mkimage\n"
- "\tdump\tLoad device to memory buffer"
+ "loadable FPGA image support",
+ "[operation type] [device number] [image address] [image size]\n"
+ "fpga operations:\n"
+ " dump\t[dev]\t\t\tLoad device to memory buffer\n"
+ " info\t[dev]\t\t\tlist known device information\n"
+ " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
+ " loadb\t[dev] [address] [size]\t"
+ "Load device from bitstream buffer (Xilinx only)\n"
+ " loadmk [dev] [address]\tLoad device generated with mkimage"
#if defined(CONFIG_FIT)
- "\n"
- "\tFor loadmk operating on FIT format uImage address must include\n"
- "\tsubimage unit name in the form of addr:<subimg_uname>"
+ "\n"
+ "\tFor loadmk operating on FIT format uImage address must include\n"
+ "\tsubimage unit name in the form of addr:<subimg_uname>"
#endif
);
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 90e9097..5829afd 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -396,7 +396,6 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
int addr_cell_len, size_cell_len, len;
u8 tmp[banks * 8];
int bank;
- const u32 *addrcell, *sizecell;
err = fdt_check_header(blob);
if (err < 0) {
diff --git a/common/image.c b/common/image.c
index 385464d..89c10b8 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1176,8 +1176,10 @@ static int fit_check_fdt (const void *fit, int fdt_noffset, int verify)
* @of_flat_tree: pointer to a char* variable, will hold fdt start address
* @of_size: pointer to a ulong variable, will hold fdt length
*
- * boot_relocate_fdt() determines if the of_flat_tree address is within
- * the bootmap and if not relocates it into that region
+ * boot_relocate_fdt() allocates a region of memory within the bootmap and
+ * relocates the of_flat_tree into that region, even if the fdt is already in
+ * the bootmap. It also expands the size of the fdt by CONFIG_SYS_FDT_PAD
+ * bytes.
*
* of_flat_tree and of_size are set to final (after relocation) values
*
@@ -1189,9 +1191,10 @@ static int fit_check_fdt (const void *fit, int fdt_noffset, int verify)
int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base,
char **of_flat_tree, ulong *of_size)
{
- char *fdt_blob = *of_flat_tree;
- ulong relocate = 0;
+ void *fdt_blob = *of_flat_tree;
+ void *of_start = 0;
ulong of_len = 0;
+ int err;
/* nothing to do */
if (*of_size == 0)
@@ -1202,62 +1205,32 @@ int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base,
goto error;
}
-#ifndef CONFIG_SYS_NO_FLASH
- /* move the blob if it is in flash (set relocate) */
- if (addr2info ((ulong)fdt_blob) != NULL)
- relocate = 1;
-#endif
-
- /*
- * The blob needs to be inside the boot mapping.
- */
- if (fdt_blob < (char *)bootmap_base)
- relocate = 1;
-
- if ((fdt_blob + *of_size + CONFIG_SYS_FDT_PAD) >=
- ((char *)CONFIG_SYS_BOOTMAPSZ + bootmap_base))
- relocate = 1;
-
- /* move flattend device tree if needed */
- if (relocate) {
- int err;
- ulong of_start = 0;
-
- /* position on a 4K boundary before the alloc_current */
- /* Pad the FDT by a specified amount */
- of_len = *of_size + CONFIG_SYS_FDT_PAD;
- of_start = (unsigned long)lmb_alloc_base(lmb, of_len, 0x1000,
- (CONFIG_SYS_BOOTMAPSZ + bootmap_base));
-
- if (of_start == 0) {
- puts("device tree - allocation error\n");
- goto error;
- }
+ /* position on a 4K boundary before the alloc_current */
+ /* Pad the FDT by a specified amount */
+ of_len = *of_size + CONFIG_SYS_FDT_PAD;
+ of_start = (void *)(unsigned long)lmb_alloc_base(lmb, of_len, 0x1000,
+ (CONFIG_SYS_BOOTMAPSZ + bootmap_base));
- debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
- (ulong)fdt_blob, (ulong)fdt_blob + *of_size - 1,
- of_len, of_len);
-
- printf (" Loading Device Tree to %08lx, end %08lx ... ",
- of_start, of_start + of_len - 1);
+ if (of_start == 0) {
+ puts("device tree - allocation error\n");
+ goto error;
+ }
- err = fdt_open_into (fdt_blob, (void *)of_start, of_len);
- if (err != 0) {
- fdt_error ("fdt move failed");
- goto error;
- }
- puts ("OK\n");
+ debug ("## device tree at %p ... %p (len=%ld [0x%lX])\n",
+ fdt_blob, fdt_blob + *of_size - 1, of_len, of_len);
- *of_flat_tree = (char *)of_start;
- *of_size = of_len;
- } else {
- *of_flat_tree = fdt_blob;
- of_len = *of_size + CONFIG_SYS_FDT_PAD;
- lmb_reserve(lmb, (ulong)fdt_blob, of_len);
- fdt_set_totalsize(*of_flat_tree, of_len);
+ printf (" Loading Device Tree to %p, end %p ... ",
+ of_start, of_start + of_len - 1);
- *of_size = of_len;
+ err = fdt_open_into (fdt_blob, of_start, of_len);
+ if (err != 0) {
+ fdt_error ("fdt move failed");
+ goto error;
}
+ puts ("OK\n");
+
+ *of_flat_tree = of_start;
+ *of_size = of_len;
set_working_fdt_addr(*of_flat_tree);
return 0;
diff --git a/common/serial.c b/common/serial.c
index 7bebc12..c3323ea 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct serial_device *serial_devices = NULL;
static struct serial_device *serial_current = NULL;
-#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA250) && !defined(CONFIG_PXA27X)
struct serial_device *__default_serial_console (void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
index 4ab3c7c..3856633 100644
--- a/doc/README.arm-relocation
+++ b/doc/README.arm-relocation
@@ -1,49 +1,54 @@
To make relocation on arm working, the following changes are done:
-Add new compilerflag:
+At arch level: add linker flag -pie
--fPIC
+ This causes the linker to generate fixup tables .rel.dyn and .dynsym,
+ which must be applied to the relocated image before transferring
+ control to it.
- -> compiler generates position independent code
+ These fixups are described in the ARM ELF documentation as type 23
+ (program-base-relative) and 2 (symbol-relative)
-changes in board code:
+At cpu level: modify linker file and add a relocation and fixup loop
-- dram_init:
- - bd pointer is now at this point not accessible, so only
- detect the real dramsize, and store it in gd->ram_size.
- best detected with get_ram_size();
- ToDo: move there also the dram initialization on boards where
- it is possible.
- - setup the bd_t dram bank info in the new function
- dram_init_banksize().
+ the linker file must be modified to include the .rel.dyn and .dynsym
+ tables in the binary image, and to provide symbols for the relocation
+ code to access these tables
-- board.c code is adapted from ppc code
+ The relocation and fixup loop must be executed after executing
+ board_init_f at initial location and before executing board_init_r
+ at final location.
-- undef CONFIG_RELOC_FIXUP_WORKS
+At board level:
- -> cmdtabl, and subcommand table must be handled from "hand"
- collected in section "__datarellocal_start".
+ dram_init(): bd pointer is now at this point not accessible, so only
+ detect the real dramsize, and store it in gd->ram_size. Bst detected
+ with get_ram_size().
- - How To fixup the sections:
+TODO: move also dram initialization there on boards where it is possible.
- __datarel_start, __datarelrolocal_start, __datarellocal_start and
- __datarelro_start
+ Setup of the the bd_t dram bank info is done in the new function
+ dram_init_banksize() called after bd is accessible.
- automatically? Then it should be possible to define again
- CONFIG_RELOC_FIXUP_WORKS
+At lib level:
-- irq stack setup is now not longer on a fix position, instead it is
- calculated in board_init_f, and stored in gd->irq_sp
+ Board.c code is adapted from ppc code
--------------------------------------------------------------------------------------
+At config level:
-To compile a board without relocation, define CONFIG_SYS_ARM_WITHOUT_RELOC
-This possibility will removed!! So please fix your board to compile without
-CONFIG_SYS_ARM_WITHOUT_RELOC defined!!!
+ Define CONFIG_RELOC_FIXUP_WORKS.
+ Undefine CONFIG_SYS_ARM_WITHOUT_RELOC
--------------------------------------------------------------------------------------
+* WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING *
+
+Boards which are not fixed to support relocation will be REMOVED!
+
+Eventually, CONFIG_SYS_ARM_WITHOUT_RELOC and CONFIG_RELOC_FIXUP_WORKS will
+disappear and boards which have to migrated to relocation will disappear too.
+
+-----------------------------------------------------------------------------
-For boards which boot from nand_spl, it is possible to save a copy
+For boards which boot from nand_spl, it is possible to save one copy
if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
is copied again in relocate_code().
@@ -64,9 +69,9 @@ f) u-boot code steps through board_init_f() and calculates
If CONFIG_SYS_TEXT_BASE == relocation address, the copying of u-boot
in f) could be saved.
--------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
-ToDo:
+TODO
- fill in bd_t infos (check)
- adapt all boards
@@ -80,7 +85,7 @@ ToDo:
- new function dram_init_banksize() is actual board specific. Maybe
we make a weak default function in arch/arm/lib/board.c ?
--------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------
Relocation with NAND_SPL (example for the tx25):
@@ -92,164 +97,17 @@ Relocation with NAND_SPL (example for the tx25):
the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
@CONFIG_SYS_NAND_U_BOOT_START
-- This u-boot does no ram int, nor cpu register setup. Just looks
- where it have to relocate and relocate itself to this address.
- If relocate address = CONFIG_SYS_TEXT_BASE(not the same, as the TEXT_BASE
- from the nand_spl code), no need to copy, just go on with bss clear
- and jump to board_init_r.
-
--------------------------------------------------------------------------------------
-
-Relocation:
-How to translate flash addresses in GOT to ram addresses.
-This is automagically done from code, but this example
-shows, how this magic code works ;-)
-(example on the qong board)
-
-Find a variable:
-
-a) search it in System.map
-(for example flash_info)
-
-a005b4c0 B BootpID
-a005b4c4 B BootpTry
-a005b4c8 b slave
-a005b4cc B flash_info
-^^^^^^^^
-a005c908 b saved_sector.4002
-a005c910 b cfi_mtd_info
-a005c9c0 b cfi_mtd_names
-a005c9d0 B mtd_table
-
----------------------------------------
-
-b) create hexdump from u-boot code:
-
-hexdump -C u-boot > gnlmpfhex
-
----------------------------------------
-
-c) search the variables address in the hexdump
-
-
-*
-0005fc80 00 00 00 00 00 00 00 00 2c 06 01 a0 18 cd 05 a0 |........,.......|
-0005fc90 9c d4 05 a0 bc b4 05 a0 1c 7f 05 a0 f0 05 01 a0 |................|
-0005fca0 08 5a 04 a0 1c ab 05 a0 ec a4 05 a0 98 c3 01 a0 |.Z..............|
-0005fcb0 a0 d6 05 a0 04 71 05 a0 c0 f9 00 a0 3c cd 05 a0 |.....q......<...|
-0005fcc0 cc b4 05 a0 f0 fa 00 a0 f0 d6 05 a0 10 86 05 a0 |................|
- ^^^^^^^^^^^
-0005fcd0 a4 16 06 a0 dc 64 05 a0 18 86 05 a0 52 48 05 a0 |.....d......RH..|
-0005fce0 c0 86 05 a0 24 6e 02 a0 b4 6c 05 a0 b0 94 01 a0 |....$n...l......|
-0005fcf0 1c 86 05 a0 50 85 05 a0 d4 0c 06 a0 bc 0b 06 a0 |....P...........|
-
-
--> 0005fcc0
-
-----------------------------------------
-
-d) know we calculate this address in RAM
-
-
- 8ff08000 (new address of code in RAM *1)
-
-+ 0005fcc0
-
-- 00008000 (offset of text *2)
-
-----------
-
- 8ff5fcc0 -> Addr GOT in RAM
-
-*1:
-activate debug and look for the line:
-Now running in RAM - U-Boot at: 8ff08000
- ^^^^^^^^
- new address of u-boot code in RAM
+- This u-boot does no RAM init, nor CPU register setup. Just look
+ where it has to copy and relocate itself to this address. If
+ relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the
+ CONFIG_SYS_TEXT_BASE from the nand_spl code), then there is no need
+ to copy, just go on with bss clear and jump to board_init_r.
-*2:
-Section Headers:
- [Nr] Name Type Addr Off Size ES Flg Lk Inf Al
- [ 0] NULL 00000000 000000 000000 00 0 0 0
- [ 1] .text PROGBITS a0000000 008000 04599c 00 AX 0 0 32
- ^^^^^^
- Offset of text
+-----------------------------------------------------------------------------
-----------------------------------------
+How ELF relocations 23 and 2 work.
-e) now we look in 8ff5fcc0 (RAM)
-
-
-QongEVB>md 0x8ff5fcc0
-8ff5fcc0 : a005b4cc a000faf0 a005d6f0 a0058610 ................
- ^^^^^^^^
- Bingo, here we have the old flash address (when relocation
- is working, here is the fixed ram address. see @ f, how
- it gets calculated)
-
-
-----------------------------------------
-
-f) now translate it in the new RAM address
-
- a005b4cc
-
-- a0000000 TextBase
-
-+ 8ff08000 new address of u-boot in ram
-----------
- 8ff634cc
-
-QongEVB>mm 0x8ff5fcc0 0x8ff634cc 1
-QongEVB>md 0x8ff5fcc0
-8ff5fcc0 : 8ff634cc a000faf0 a005d6f0 a0058610 .4..............
-8ff5fcd0 : a00616a4 a00564dc a0058618 a0054852 .....d......RH..
-
-As this must be done for all address in the GOT, the u-boot
-code did this automagically ... :-)
-
-----------------------------------------------
-
-g) check if the new address is really in the bss section:
-
-bss start:
-8ff6054c (8ff08000 + 0005854C monitorlen)
-
-bss end:
-8ff698ac (8ff08000 + 618AC)
-
-8ff634cc is in bss :-)
-
-----------------------------------------------
-
-h) u-boot prints:
-
-important addresses:
-
-U-Boot code: A0000000 -> A005854C BSS: -> A00618AC TextBase 0xa0000000
-Now running in RAM - U-Boot at: 8ff08000 relocBase 0x8ff08000
-
-
----------
-
-U-Boot 2010.06-rc2-00002-gf8fbb25-dirty (Jun 18 2010 - 17:07:19)
-
-U-Boot code: A0000000 -> A005854C BSS: -> A00618AC
-CPU: Freescale i.MX31 at 398 MHz
-Board: DAVE/DENX Qong
-mon: FFFFFFFF gd->monLen: 000618AC
-Top of RAM usable for U-Boot at: 90000000
-LCD panel info: 640 x 480, 16 bit/pix
-Reserving 600k for LCD Framebuffer at: 8ff6a000
-Reserving 390k for U-Boot at: 8ff08000
-Reserving 1280k for malloc() at: 8fdc8000
-Reserving 28 Bytes for Board Info at: 8fdc7fe4
-Reserving 48 Bytes for Global Data at: 8fdc7fb4
-New Stack Pointer is: 8fdc7fb0
-RAM Configuration:
-Bank #0: 80000000 256 MiB
-mon: 0005854C gd->monLen: 000618AC
-Now running in RAM - U-Boot at: 8ff08000
+TBC
-------------------------------------------------------------------------------------
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index e108a0d..1657ef6 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -78,6 +78,20 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig.
Syntax is:
hwconfig=fsl_ddr:addr_hash=true
+
+Memory testing options for mpc85xx
+==================================
+1. Memory test can be done once U-boot prompt comes up using mtest, or
+2. Memory test can be done with Power-On-Self-Test function, activated at
+ compile time.
+
+ In order to enable the POST memory test, CONFIG_POST needs to be
+ defined in board configuraiton header file. By default, POST memory test
+ performs a fast test. A slow test can be enabled by changing the flag at
+ compiling time. To test memory bigger than 2GB, 36BIT support is needed.
+ Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
+ window to physical address so that all physical memory can be tested.
+
Combination of hwconfig
=======================
Hwconfig can be combined with multiple parameters, for example, on a supported
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
new file mode 100644
index 0000000..a707c6f
--- /dev/null
+++ b/doc/README.scrapyard
@@ -0,0 +1,29 @@
+Over time, support for more and more boards gets added to U-Boot -
+while other board support code dies a silent death caused by
+negligence in combination with ordinary bitrot. Sometimes this goes
+by unnoticed, but often build errors will result. If nobody cares any
+more to resolve such problems, then the code is really dead and will
+be removed from the U-Boot source tree. The remainders rest in piece
+in the imperishable depths of the git history. This document tries to
+maintain a list of such former fellows, so archeologists can check
+easily if here is something they might want to dig for...
+
+
+Board Arch CPU removed Commit last known maintainer/contact
+=============================================================================
+NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
+CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
+logodl ARM PXA2xx 059e778 2010-10-18 August Hoeraendl <august.hoerandl@gmx.at>
+CCM powerpc MPC860 dff07e1 2010-10-06 Wolfgang Grandegger <wg@denx.de>
+PCU_E powerpc MPC860T 544d97e 2010-10-06 Wolfgang Denk <wd@denx.de>
+spieval powerpc MPC5200 69434e4 2010-09-19
+smmaco4 powerpc MPC5200 9ddc3af 2010-09-19
+HMI10 powerpc MPC823 77efe35 2010-09-19 Wolfgang Denk <wd@denx.de>
+GTH powerpc MPC860 0fe247b 2010-07-17 Thomas Lange <thomas@corelatus.se>
+AmigaOneG3SE 953b7e6 2010-06-23
+suzaku microblaze 4f18060 2009-10-03 Yasushi Shoji <yashi@atmark-techno.com>
+XUPV2P microblaze 8fab49e 2008-12-10 Michal Simek <monstr@monstr.eu>
+MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwarz <andre.schwarz@matrix-vision.de>
+adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi <adrian.filipi@eurotech.com>
+R5200 ColdFire 48ead7a 2008-03-31 Zachary P. Landau <zachary.landau@labxtechnologies.com>
+CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com>
diff --git a/doc/README.ubi b/doc/README.ubi
new file mode 100644
index 0000000..da2dfac
--- /dev/null
+++ b/doc/README.ubi
@@ -0,0 +1,144 @@
+-------------------
+UBI usage in U-Boot
+-------------------
+
+Here the list of the currently implemented UBI commands:
+
+=> help ubi
+ubi - ubi commands
+
+Usage:
+ubi part [part] [offset]
+ - Show or set current partition (with optional VID header offset)
+ubi info [l[ayout]] - Display volume and ubi layout information
+ubi create[vol] volume [size] [type] - create volume name with size
+ubi write[vol] address volume size - Write volume from address with size
+ubi read[vol] address volume [size] - Read volume to address with size
+ubi remove[vol] volume - Remove volume
+[Legends]
+ volume: character name
+ size: specified in bytes
+ type: s[tatic] or d[ynamic] (default=dynamic)
+
+
+The first command that is needed to be issues is "ubi part" to connect
+one mtd partition to the UBI subsystem. This command will either create
+a new UBI device on the requested MTD partition. Or it will attach a
+previously created UBI device. The other UBI commands will only work
+when such a UBI device is attached (via "ubi part"). Here an example:
+
+=> mtdparts
+
+device nor0 <1fc000000.nor_flash>, # parts = 6
+ #: name size offset mask_flags
+ 0: kernel 0x00200000 0x00000000 0
+ 1: dtb 0x00040000 0x00200000 0
+ 2: root 0x00200000 0x00240000 0
+ 3: user 0x01ac0000 0x00440000 0
+ 4: env 0x00080000 0x01f00000 0
+ 5: u-boot 0x00080000 0x01f80000 0
+
+active partition: nor0,0 - (kernel) 0x00200000 @ 0x00000000
+
+defaults:
+mtdids : nor0=1fc000000.nor_flash
+mtdparts: mtdparts=1fc000000.nor_flash:2m(kernel),256k(dtb),2m(root),27392k(user),512k(env),512k(u-boot)
+
+=> ubi part root
+Creating 1 MTD partitions on "nor0":
+0x000000240000-0x000000440000 : "mtd=2"
+UBI: attaching mtd1 to ubi0
+UBI: physical eraseblock size: 262144 bytes (256 KiB)
+UBI: logical eraseblock size: 262016 bytes
+UBI: smallest flash I/O unit: 1
+UBI: VID header offset: 64 (aligned 64)
+UBI: data offset: 128
+UBI: attached mtd1 to ubi0
+UBI: MTD device name: "mtd=2"
+UBI: MTD device size: 2 MiB
+UBI: number of good PEBs: 8
+UBI: number of bad PEBs: 0
+UBI: max. allowed volumes: 128
+UBI: wear-leveling threshold: 4096
+UBI: number of internal volumes: 1
+UBI: number of user volumes: 1
+UBI: available PEBs: 0
+UBI: total number of reserved PEBs: 8
+UBI: number of PEBs reserved for bad PEB handling: 0
+UBI: max/mean erase counter: 2/1
+
+
+Now that the UBI device is attached, this device can be modified
+using the following commands:
+
+ubi info Display volume and ubi layout information
+ubi createvol Create UBI volume on UBI device
+ubi removevol Remove UBI volume from UBI device
+ubi read Read data from UBI volume to memory
+ubi write Write data from memory to UBI volume
+
+
+Here a few examples on the usage:
+
+=> ubi create testvol
+Creating dynamic volume testvol of size 1048064
+
+=> ubi info l
+UBI: volume information dump:
+UBI: vol_id 0
+UBI: reserved_pebs 4
+UBI: alignment 1
+UBI: data_pad 0
+UBI: vol_type 3
+UBI: name_len 7
+UBI: usable_leb_size 262016
+UBI: used_ebs 4
+UBI: used_bytes 1048064
+UBI: last_eb_bytes 262016
+UBI: corrupted 0
+UBI: upd_marker 0
+UBI: name testvol
+
+UBI: volume information dump:
+UBI: vol_id 2147479551
+UBI: reserved_pebs 2
+UBI: alignment 1
+UBI: data_pad 0
+UBI: vol_type 3
+UBI: name_len 13
+UBI: usable_leb_size 262016
+UBI: used_ebs 2
+UBI: used_bytes 524032
+UBI: last_eb_bytes 2
+UBI: corrupted 0
+UBI: upd_marker 0
+UBI: name layout volume
+
+=> ubi info
+UBI: MTD device name: "mtd=2"
+UBI: MTD device size: 2 MiB
+UBI: physical eraseblock size: 262144 bytes (256 KiB)
+UBI: logical eraseblock size: 262016 bytes
+UBI: number of good PEBs: 8
+UBI: number of bad PEBs: 0
+UBI: smallest flash I/O unit: 1
+UBI: VID header offset: 64 (aligned 64)
+UBI: data offset: 128
+UBI: max. allowed volumes: 128
+UBI: wear-leveling threshold: 4096
+UBI: number of internal volumes: 1
+UBI: number of user volumes: 1
+UBI: available PEBs: 0
+UBI: total number of reserved PEBs: 8
+UBI: number of PEBs reserved for bad PEB handling: 0
+UBI: max/mean erase counter: 4/1
+
+=> ubi write 800000 testvol 80000
+Volume "testvol" found at volume id 0
+
+=> ubi read 900000 testvol 80000
+Volume testvol found at volume id 0
+read 524288 bytes from volume 0 to 900000(buf address)
+
+=> cmp.b 800000 900000 80000
+Total of 524288 bytes were the same
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 3febd1f..a72d1a1 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -27,7 +27,7 @@
#include "omap24xx_i2c.h"
-#define I2C_TIMEOUT 10
+#define I2C_TIMEOUT 1000
static void wait_for_bb (void);
static u16 wait_for_pin (void);
@@ -159,58 +159,56 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
/* no stop bit needed here */
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
- /* Important: have to use byte access */
- writeb (regoffset, &i2c_base->data);
- udelay (20000);
- if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
+ /* send register offset */
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
i2c_error = 1;
+ goto read_exit;
+ }
+ if (status & I2C_STAT_XRDY) {
+ /* Important: have to use byte access */
+ writeb(regoffset, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
}
- } else {
- i2c_error = 1;
}
- if (!i2c_error) {
- writew (I2C_CON_EN, &i2c_base->con);
- while (readw(&i2c_base->stat) &
- (I2C_STAT_XRDY | I2C_STAT_ARDY)) {
- udelay (10000);
- /* Have to clear pending interrupt to clear I2C_STAT */
- writew (0xFFFF, &i2c_base->stat);
+ /* set slave address */
+ writew(devaddr, &i2c_base->sa);
+ /* read one byte from slave */
+ writew(1, &i2c_base->cnt);
+ /* need stop bit here */
+ writew(I2C_CON_EN | I2C_CON_MST |
+ I2C_CON_STT | I2C_CON_STP,
+ &i2c_base->con);
+
+ /* receive data */
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ goto read_exit;
}
-
- /* set slave address */
- writew (devaddr, &i2c_base->sa);
- /* read one byte from slave */
- writew (1, &i2c_base->cnt);
- /* need stop bit here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
- &i2c_base->con);
-
- status = wait_for_pin ();
if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
defined(CONFIG_OMAP44XX)
- *value = readb (&i2c_base->data);
+ *value = readb(&i2c_base->data);
#else
- *value = readw (&i2c_base->data);
+ *value = readw(&i2c_base->data);
#endif
- udelay (20000);
- } else {
- i2c_error = 1;
+ writew(I2C_STAT_RRDY, &i2c_base->stat);
}
-
- if (!i2c_error) {
- writew (I2C_CON_EN, &i2c_base->con);
- while (readw (&i2c_base->stat) &
- (I2C_STAT_RRDY | I2C_STAT_ARDY)) {
- udelay (10000);
- writew (0xFFFF, &i2c_base->stat);
- }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
}
}
+
+read_exit:
flush_fifo();
writew (0xFFFF, &i2c_base->stat);
writew (0, &i2c_base->cnt);
@@ -220,7 +218,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
{
int i2c_error = 0;
- u16 status, stat;
+ u16 status;
/* wait until bus not busy */
wait_for_bb ();
@@ -233,49 +231,55 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
I2C_CON_STP, &i2c_base->con);
- /* wait until state change */
- status = wait_for_pin ();
-
- if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
- /* send out 1 byte */
- writeb (regoffset, &i2c_base->data);
- writew (I2C_STAT_XRDY, &i2c_base->stat);
-
- status = wait_for_pin ();
- if ((status & I2C_STAT_XRDY)) {
- /* send out next 1 byte */
- writeb (value, &i2c_base->data);
- writew (I2C_STAT_XRDY, &i2c_base->stat);
- } else {
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
i2c_error = 1;
+ goto write_exit;
}
+ if (status & I2C_STAT_XRDY) {
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
+ /* send register offset */
+ writeb(regoffset, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ goto write_exit;
+ }
+ if (status & I2C_STAT_XRDY) {
+ /* send data */
+ writeb(value, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
+ }
+ break;
#else
- /* send out two bytes */
- writew ((value << 8) + regoffset, &i2c_base->data);
+ /* send out two bytes */
+ writew((value << 8) + regoffset, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
#endif
- /* must have enough delay to allow BB bit to go low */
- udelay (50000);
- if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
- i2c_error = 1;
}
- } else {
- i2c_error = 1;
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
}
- if (!i2c_error) {
- int eout = 200;
+ wait_for_bb();
- writew (I2C_CON_EN, &i2c_base->con);
- while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
- udelay (1000);
- /* have to read to clear intrrupt */
- writew (0xFFFF, &i2c_base->stat);
- if(--eout == 0) /* better leave with error than hang */
- break;
- }
- }
+ status = readw(&i2c_base->stat);
+ if (status & I2C_STAT_NACK)
+ i2c_error = 1;
+
+write_exit:
flush_fifo();
writew (0xFFFF, &i2c_base->stat);
writew (0, &i2c_base->cnt);
@@ -306,6 +310,7 @@ static void flush_fifo(void)
int i2c_probe (uchar chip)
{
+ u16 status;
int res = 1; /* default = fail */
if (chip == readw (&i2c_base->oa)) {
@@ -321,19 +326,37 @@ int i2c_probe (uchar chip)
writew (chip, &i2c_base->sa);
/* stop bit needed here */
writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
- /* enough delay for the NACK bit set */
- udelay (50000);
- if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
- res = 0; /* success case */
- flush_fifo();
- writew(0xFFFF, &i2c_base->stat);
- } else {
- writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/
- writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
- udelay(20000);
- wait_for_bb ();
+ while (1) {
+ status = wait_for_pin();
+ if (status == 0) {
+ res = 1;
+ goto probe_exit;
+ }
+ if (status & I2C_STAT_NACK) {
+ res = 1;
+ writew(0xff, &i2c_base->stat);
+ writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
+ wait_for_bb ();
+ break;
+ }
+ if (status & I2C_STAT_ARDY) {
+ writew(I2C_STAT_ARDY, &i2c_base->stat);
+ break;
+ }
+ if (status & I2C_STAT_RRDY) {
+ res = 0;
+#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
+ defined(CONFIG_OMAP44XX)
+ readb(&i2c_base->data);
+#else
+ readw(&i2c_base->data);
+#endif
+ writew(I2C_STAT_RRDY, &i2c_base->stat);
+ }
}
+
+probe_exit:
flush_fifo();
writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
writew(0xFFFF, &i2c_base->stat);
@@ -392,13 +415,13 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
static void wait_for_bb (void)
{
- int timeout = 10;
+ int timeout = I2C_TIMEOUT;
u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/
while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
writew (stat, &i2c_base->stat);
- udelay (50000);
+ udelay(1000);
}
if (timeout <= 0) {
@@ -411,7 +434,7 @@ static void wait_for_bb (void)
static u16 wait_for_pin (void)
{
u16 status;
- int timeout = 10;
+ int timeout = I2C_TIMEOUT;
do {
udelay (1000);
@@ -424,8 +447,10 @@ static u16 wait_for_pin (void)
if (timeout <= 0) {
printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
readw (&i2c_base->stat));
- writew(0xFFFF, &i2c_base->stat);
-}
+ writew(0xFFFF, &i2c_base->stat);
+ status = 0;
+ }
+
return status;
}
diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c
index 8776903..48e21ef 100644
--- a/drivers/mmc/pxa_mmc.c
+++ b/drivers/mmc/pxa_mmc.c
@@ -27,6 +27,7 @@
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <part.h>
+#include <asm/io.h>
#include "pxa_mmc.h"
@@ -59,18 +60,20 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
cmdat | wide);
- MMC_STRPCL = MMC_STRPCL_STOP_CLK;
- MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
- while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ;
- MMC_CMD = cmd;
- MMC_ARGH = argh;
- MMC_ARGL = argl;
- MMC_CMDAT = cmdat | wide;
- MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES;
- MMC_STRPCL = MMC_STRPCL_START_CLK;
- while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ;
-
- status = MMC_STAT;
+ writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+ writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF))
+ ;
+ writel(cmd, MMC_CMD);
+ writel(argh, MMC_ARGH);
+ writel(argl, MMC_ARGL);
+ writel(cmdat | wide, MMC_CMDAT);
+ writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK);
+ writel(MMC_STRPCL_START_CLK, MMC_STRPCL);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES))
+ ;
+
+ status = readl(MMC_STAT);
debug("MMC status 0x%08x\n", status);
if (status & MMC_STAT_TIME_OUT_RESPONSE) {
return 0;
@@ -80,10 +83,10 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
* Did I mention this is Sick. We always need to
* discard the upper 8 bits of the first 16-bit word.
*/
- a = (MMC_RES & 0xffff);
+ a = (readl(MMC_RES) & 0xffff);
for (i = 0; i < 4; i++) {
- b = (MMC_RES & 0xffff);
- c = (MMC_RES & 0xffff);
+ b = (readl(MMC_RES) & 0xffff);
+ c = (readl(MMC_RES) & 0xffff);
resp[i] = (a << 24) | (b << 8) | (c >> 8);
a = c;
debug("MMC resp[%d] = %#08x\n", i, resp[i]);
@@ -115,37 +118,38 @@ mmc_block_read(uchar * dst, ulong src, ulong len)
/* send read command */
argh = src >> 16;
argl = src & 0xffff;
- MMC_STRPCL = MMC_STRPCL_STOP_CLK;
- MMC_RDTO = 0xffff;
- MMC_NOB = 1;
- MMC_BLKLEN = len;
+ writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+ writel(0xffff, MMC_RDTO);
+ writel(1, MMC_NOB);
+ writel(len, MMC_BLKLEN);
mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl,
MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK |
MMC_CMDAT_DATA_EN);
- MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
+ writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
while (len) {
- if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
+ if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
int i;
for (i = min(len, 32); i; i--) {
- *dst++ = *((volatile uchar *)&MMC_RXFIFO);
+ *dst++ = readb(MMC_RXFIFO);
len--;
}
#else
- *dst++ = MMC_RXFIFO;
+ *dst++ = readb(MMC_RXFIFO);
len--;
#endif
}
- status = MMC_STAT;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
}
- MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
- while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
- status = MMC_STAT;
+ writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
+ ;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
@@ -176,37 +180,39 @@ mmc_block_write(ulong dst, uchar * src, int len)
/* send write command */
argh = dst >> 16;
argl = dst & 0xffff;
- MMC_STRPCL = MMC_STRPCL_STOP_CLK;
- MMC_NOB = 1;
- MMC_BLKLEN = len;
+ writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
+ writel(1, MMC_NOB);
+ writel(len, MMC_BLKLEN);
mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl,
MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK |
MMC_CMDAT_DATA_EN);
- MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
+ writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK);
while (len) {
- if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
+ if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) {
int i, bytes = min(32, len);
for (i = 0; i < bytes; i++) {
- MMC_TXFIFO = *src++;
+ writel(*src++, MMC_TXFIFO);
}
if (bytes < 32) {
- MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
+ writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF);
}
len -= bytes;
}
- status = MMC_STAT;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
}
- MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
- while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ;
- MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
- while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ;
- status = MMC_STAT;
+ writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
+ ;
+ writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK);
+ while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE))
+ ;
+ status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
@@ -559,13 +565,13 @@ mmc_legacy_init(int verbose)
set_GPIO_mode(GPIO8_MMCCS0_MD);
#endif
#ifdef CONFIG_CPU_MONAHANS /* pxa3xx */
- CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1;
+ writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA);
#else /* pxa2xx */
- CKEN |= CKEN12_MMC; /* enable MMC unit clock */
+ writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */
#endif
- MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
- MMC_RESTO = MMC_RES_TO_MAX;
- MMC_SPI = MMC_SPI_DISABLE;
+ writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT);
+ writel(MMC_RES_TO_MAX, MMC_RESTO);
+ writel(MMC_SPI_DISABLE, MMC_SPI);
/* reset */
mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0);
@@ -624,7 +630,7 @@ mmc_legacy_init(int verbose)
mmc_decode_cid(cid_resp);
}
- MMC_CLKRT = 0; /* 20 MHz */
+ writel(0, MMC_CLKRT); /* 20 MHz */
resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 2d4ffed..3f09c2b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -414,6 +414,9 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
uint32_t base;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
+ /* Initialize MAC address */
+ fec_set_hwaddr(dev);
+
/*
* reserve memory for both buffer descriptor chains at once
* Datasheet forces the startaddress of each chain is 16 byte
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
index 56eee7b..d626d68 100644
--- a/drivers/net/uli526x.c
+++ b/drivers/net/uli526x.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007, 2010 Freescale Semiconductor, Inc.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
*
@@ -311,7 +311,8 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
i));
/* Set Node address */
- if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)
+ if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
+ ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
/* SROM absent, so write MAC address to ID Table */
set_mac_addr(dev);
else { /*Exist SROM*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 48033d7..282ab23 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -324,9 +324,9 @@ static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
}
static int uec_set_mac_if_mode(uec_private_t *uec,
- enet_interface_type_e if_mode, int speed)
+ enum fsl_phy_enet_if if_mode, int speed)
{
- enet_interface_type_e enet_if_mode;
+ enum fsl_phy_enet_if enet_if_mode;
uec_info_t *uec_info;
uec_t *uec_regs;
u32 upsmr;
@@ -521,7 +521,7 @@ static void adjust_link(struct eth_device *dev)
struct uec_mii_info *mii_info = uec->mii_info;
extern void change_phy_interface_mode(struct eth_device *dev,
- enet_interface_type_e mode, int speed);
+ enum fsl_phy_enet_if mode, int speed);
uec_regs = uec->uec_regs;
if (mii_info->link) {
@@ -539,7 +539,7 @@ static void adjust_link(struct eth_device *dev)
}
if (mii_info->speed != uec->oldspeed) {
- enet_interface_type_e mode = \
+ enum fsl_phy_enet_if mode = \
uec->uec_info->enet_interface_type;
if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
switch (mii_info->speed) {
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 2a9e2dc..94eb9a2 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
@@ -25,6 +25,7 @@
#include "qe.h"
#include "uccf.h"
+#include <asm/fsl_enet.h>
#define MAX_TX_THREADS 8
#define MAX_RX_THREADS 8
@@ -660,21 +661,6 @@ typedef enum uec_num_of_threads {
UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
} uec_num_of_threads_e;
-/* UEC ethernet interface type
-*/
-typedef enum enet_interface_type {
- MII,
- RMII,
- RGMII,
- GMII,
- RGMII_ID,
- RGMII_RXID,
- RGMII_TXID,
- TBI,
- RTBI,
- SGMII
-} enet_interface_type_e;
-
/* UEC initialization info struct
*/
#define STD_UEC_INFO(num) \
@@ -705,7 +691,7 @@ typedef struct uec_info {
u16 rx_bd_ring_len;
u16 tx_bd_ring_len;
u8 phy_address;
- enet_interface_type_e enet_interface_type;
+ enum fsl_phy_enet_if enet_interface_type;
int speed;
} uec_info_t;
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 9be784e..35f2368 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2005 Freescale Semiconductor, Inc.
+ * Copyright (C) 2005,2010 Freescale Semiconductor, Inc.
*
* Author: Shlomi Gridish
*
@@ -485,7 +485,7 @@ static int marvell_init(struct uec_mii_info *mii_info)
{
struct eth_device *edev = mii_info->dev;
uec_private_t *uec = edev->priv;
- enum enet_interface_type iface = uec->uec_info->enet_interface_type;
+ enum fsl_phy_enet_if iface = uec->uec_info->enet_interface_type;
int speed = uec->uec_info->speed;
if ((speed == 1000) &&
@@ -853,7 +853,7 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
}
void marvell_phy_interface_mode (struct eth_device *dev,
- enet_interface_type_e type,
+ enum fsl_phy_enet_if type,
int speed
)
{
@@ -907,7 +907,7 @@ void marvell_phy_interface_mode (struct eth_device *dev,
}
void change_phy_interface_mode (struct eth_device *dev,
- enet_interface_type_e type, int speed)
+ enum fsl_phy_enet_if type, int speed)
{
#ifdef CONFIG_PHY_MODE_NEED_CHANGE
marvell_phy_interface_mode (dev, type, speed);
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index b74e439..e457980 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -32,6 +32,7 @@
#include <watchdog.h>
#include <serial.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -73,60 +74,60 @@ void pxa_setbrg_dev (unsigned int uart_index)
switch (uart_index) {
case FFUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_22_FFUART;
+ writel(readl(CKENA) | CKENA_22_FFUART, CKENA);
#else
- CKEN |= CKEN6_FFUART;
+ writel(readl(CKEN) | CKEN6_FFUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
- FFIER = 0; /* Disable for now */
- FFFCR = 0; /* No fifos enabled */
+ writel(0, FFIER); /* Disable for now */
+ writel(0, FFFCR); /* No fifos enabled */
/* set baud rate */
- FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
- FFDLL = quot & 0xff;
- FFDLH = quot >> 8;
- FFLCR = LCR_WLS0 | LCR_WLS1;
+ writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR);
+ writel(quot & 0xff, FFDLL);
+ writel(quot >> 8, FFDLH);
+ writel(LCR_WLS0 | LCR_WLS1, FFLCR);
- FFIER = IER_UUE; /* Enable FFUART */
+ writel(IER_UUE, FFIER); /* Enable FFUART */
break;
case BTUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_21_BTUART;
+ writel(readl(CKENA) | CKENA_21_BTUART, CKENA);
#else
- CKEN |= CKEN7_BTUART;
+ writel(readl(CKEN) | CKEN7_BTUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
- BTIER = 0;
- BTFCR = 0;
+ writel(0, BTIER);
+ writel(0, BTFCR);
/* set baud rate */
- BTLCR = LCR_DLAB;
- BTDLL = quot & 0xff;
- BTDLH = quot >> 8;
- BTLCR = LCR_WLS0 | LCR_WLS1;
+ writel(LCR_DLAB, BTLCR);
+ writel(quot & 0xff, BTDLL);
+ writel(quot >> 8, BTDLH);
+ writel(LCR_WLS0 | LCR_WLS1, BTLCR);
- BTIER = IER_UUE; /* Enable BFUART */
+ writel(IER_UUE, BTIER); /* Enable BFUART */
break;
case STUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
- CKENA |= CKENA_23_STUART;
+ writel(readl(CKENA) | CKENA_23_STUART, CKENA);
#else
- CKEN |= CKEN5_STUART;
+ writel(readl(CKEN) | CKEN5_STUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
- STIER = 0;
- STFCR = 0;
+ writel(0, STIER);
+ writel(0, STFCR);
/* set baud rate */
- STLCR = LCR_DLAB;
- STDLL = quot & 0xff;
- STDLH = quot >> 8;
- STLCR = LCR_WLS0 | LCR_WLS1;
+ writel(LCR_DLAB, STLCR);
+ writel(quot & 0xff, STDLL);
+ writel(quot >> 8, STDLH);
+ writel(LCR_WLS0 | LCR_WLS1, STLCR);
- STIER = IER_UUE; /* Enable STUART */
+ writel(IER_UUE, STIER); /* Enable STUART */
break;
default:
@@ -156,21 +157,21 @@ void pxa_putc_dev (unsigned int uart_index,const char c)
switch (uart_index) {
case FFUART_INDEX:
/* wait for room in the tx FIFO on FFUART */
- while ((FFLSR & LSR_TEMT) == 0)
+ while ((readl(FFLSR) & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- FFTHR = c;
+ writel(c, FFTHR);
break;
case BTUART_INDEX:
- while ((BTLSR & LSR_TEMT ) == 0 )
+ while ((readl(BTLSR) & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- BTTHR = c;
+ writel(c, BTTHR);
break;
case STUART_INDEX:
- while ((STLSR & LSR_TEMT ) == 0 )
+ while ((readl(STLSR) & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- STTHR = c;
+ writel(c, STTHR);
break;
}
@@ -188,11 +189,11 @@ int pxa_tstc_dev (unsigned int uart_index)
{
switch (uart_index) {
case FFUART_INDEX:
- return FFLSR & LSR_DR;
+ return readl(FFLSR) & LSR_DR;
case BTUART_INDEX:
- return BTLSR & LSR_DR;
+ return readl(BTLSR) & LSR_DR;
case STUART_INDEX:
- return STLSR & LSR_DR;
+ return readl(STLSR) & LSR_DR;
}
return -1;
}
@@ -206,18 +207,21 @@ int pxa_getc_dev (unsigned int uart_index)
{
switch (uart_index) {
case FFUART_INDEX:
- while (!(FFLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) FFRBR & 0xff;
+ while (!(readl(FFLSR) & LSR_DR))
+ /* Reset HW Watchdog, if needed */
+ WATCHDOG_RESET();
+ return (char) readl(FFRBR) & 0xff;
case BTUART_INDEX:
- while (!(BTLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) BTRBR & 0xff;
+ while (!(readl(BTLSR) & LSR_DR))
+ /* Reset HW Watchdog, if needed */
+ WATCHDOG_RESET();
+ return (char) readl(BTRBR) & 0xff;
case STUART_INDEX:
- while (!(STLSR & LSR_DR))
- WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
- return (char) STRBR & 0xff;
+ while (!(readl(STLSR) & LSR_DR))
+ /* Reset HW Watchdog, if needed */
+ WATCHDOG_RESET();
+ return (char) readl(STRBR) & 0xff;
}
return -1;
}
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 37d056e..f44fc4e 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -288,6 +288,7 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
idx = 0;
while (idx < 5) {
td->qt_buffer[idx] = cpu_to_hc32(addr);
+ td->qt_buffer_hi[idx] = 0;
next = (addr + 4096) & ~4095;
delta = next - addr;
if (delta >= sz)
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index af8ee90..8d7b380 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -117,6 +117,8 @@ int ehci_hcd_init(void)
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+ udelay(10000);
+
return 0;
}
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 6fae8ba..d3aa55b 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -166,12 +166,16 @@ struct usb_linux_config_descriptor {
/* Queue Element Transfer Descriptor (qTD). */
struct qTD {
- uint32_t qt_next;
+ /* this part defined by EHCI spec */
+ uint32_t qt_next; /* see EHCI 3.5.1 */
#define QT_NEXT_TERMINATE 1
- uint32_t qt_altnext;
- uint32_t qt_token;
- uint32_t qt_buffer[5];
-};
+ uint32_t qt_altnext; /* see EHCI 3.5.2 */
+ uint32_t qt_token; /* see EHCI 3.5.3 */
+ uint32_t qt_buffer[5]; /* see EHCI 3.5.4 */
+ uint32_t qt_buffer_hi[5]; /* Appendix B */
+ /* pad struct for 32 byte alignment */
+ uint32_t unused[3];
+} __attribute__ ((aligned (32)));
/* Queue Head (QH). */
struct QH {
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 744e961..a75e4f2 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -858,7 +858,7 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
if (disk_read(cursect,
(mydata->fatsize == 32) ?
(mydata->clust_size) :
- LINEAR_PREFETCH_SIZE,
+ LINEAR_PREFETCH_SIZE / SECTOR_SIZE,
do_fat_read_block) < 0) {
debug("Error: reading rootdir block\n");
return -1;
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
deleted file mode 100644
index df1c1ca..0000000
--- a/include/configs/NC650.h
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC852T 1
-#define CONFIG_NC650 1
-
-#define CONFIG_SYS_TEXT_BASE 0x40700000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-
-/*
- * 10 MHz - PLL input clock
- */
-#define CONFIG_8xx_OSCLK 10000000
-
-/*
- * 50 MHz - default CPU clock
- */
-#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
-
-/*
- * 15 MHz - CPU minimum clock
- */
-#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000
-
-/*
- * 133 MHz - CPU maximum clock
- */
-#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
-
-#define CONFIG_SYS_MEASURE_CPUCLK
-#define CONFIG_SYS_8XX_XIN CONFIG_8xx_OSCLK
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT \
- "\nEnter password - autoboot in %d seconds...\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "ids"
-#define CONFIG_BOOT_RETRY_TIME 900
-#define CONFIG_BOOT_RETRY_MIN 30
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
- "bootm"
-
-#define CONFIG_WATCHDOG /* watchdog enabled */
-
-#undef CONFIG_STATUS_LED /* Status LED disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
-#define FEC_ENET
-#define CONFIG_MII
-#define CONFIG_SYS_DISCOVER_PHY 1
-
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#if defined(CONFIG_IDS852_REV1)
-
-#define SCL 0x1000 /* PA 3 */
-#define SDA 0x2000 /* PA 2 */
-
-#define __I2C_DIR immr->im_ioport.iop_padir
-#define __I2C_DAT immr->im_ioport.iop_padat
-#define __I2C_PAR immr->im_ioport.iop_papar
-
-#elif defined(CONFIG_IDS852_REV2)
-
-#define SCL 0x0002 /* PB 30 */
-#define SDA 0x0001 /* PB 31 */
-
-#define __I2C_PAR immr->im_cpm.cp_pbpar
-#define __I2C_DIR immr->im_cpm.cp_pbdir
-#define __I2C_DAT immr->im_cpm.cp_pbdat
-
-#endif
-
-#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
- __I2C_DIR |= (SDA|SCL); }
-#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
-#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
-#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
-#define I2C_DELAY { udelay(5); }
-#define I2C_ACTIVE { __I2C_DIR |= SDA; }
-#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
-
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR 0x51
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x40000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00740000
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
-#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*
- * NAND flash support
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \
- SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
- SCCR_DFLCD000 | SCCR_DFALCD00)
-
- /*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
-
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/* FLASH timing: Default value of OR0 after reset */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
- OR_SCY_15_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-/*
- * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
- * rev2 only uses the chipselect
- */
-#define CONFIG_SYS_NAND_BASE 0x50000000
-#define CONFIG_SYS_NAND_SIZE 0x04000000
-
-#define CONFIG_SYS_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-
-#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V )
-#define CONFIG_SYS_OR2_PRELIM (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI )
-
-/*
- * BR3 and OR3 (SDRAM)
- */
-#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
-#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
-
- /*
- * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
- */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-
-/*
- * BR4 and OR4 (CPLD)
- */
-#define CONFIG_SYS_CPLD_BASE 0x80000000 /* CPLD */
-#define CONFIG_SYS_CPLD_SIZE 0x10000 /* only 16 used */
-
-#define CONFIG_SYS_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- OR_SCY_1_CLK)
-
-#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD)
-
-/*
- * BR5 and OR5 (SRAM)
- */
-#define CONFIG_SYS_SRAM_BASE 0x60000000
-#define CONFIG_SYS_SRAM_SIZE 0x00080000
-
-#define CONFIG_SYS_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
- OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
-
-#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
-#define CONFIG_SYS_OR5_PRELIM (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM)
-
-#if defined(CONFIG_CP850)
-/*
- * BR6 and OR6 (DPRAM) - only on CP850
- */
-#define CONFIG_SYS_OR6_PRELIM 0xffff8170
-#define CONFIG_SYS_BR6_PRELIM 0xa0000401
-#define DPRAM_BASE_ADDR 0xa0000000
-
-#define CONFIG_MISC_INIT_R 1
-#endif
-
-/*
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 39
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
-#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
-
-/*
- * MAMR settings for SDRAM
- */
-
-#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * MBMR settings for NAND flash
- */
-
-#define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X )
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00400000
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
-
-#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
- "4m(cramfs1),1m(cramfs2)," \
- "256k(u-boot),128k(env);" \
- "nc650-nand:4m(jffs1),28m(jffs2)"
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index e7cdb92..8c7d528 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -77,8 +77,9 @@
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#endif
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x7fffffff
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 59655b1..d5c116f 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -380,11 +380,11 @@
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000)
+#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
#ifdef CONFIG_PCIE1
@@ -393,16 +393,16 @@
* Addresses are mapped 1-1.
*/
#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0xaf000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000
#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0xef000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000
#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
-#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BASE
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
#endif /* CONFIG_PCIE1 */
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index 6dcebe6..24a04eb 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -37,6 +37,8 @@
#define CONFIG_A4M072 1 /* ... on A4M072 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
@@ -125,7 +127,7 @@
#define CONFIG_CMD_PCI
#endif
-#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
#define CONFIG_SYS_LOWBOOT 1
#define CONFIG_SYS_LOWBOOT32 1
#endif
@@ -238,7 +240,7 @@
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index b9f1f6b..b5d3e10 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -81,17 +81,6 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
-#if defined(CONFIG_SYS_RAMBOOT)
-/*
- * Disable NOR FLASH commands on RAM-booting version. One main reason for this
- * RAM-booting version is boards with NAND and without NOR. This image can
- * be used for initial NAND programming.
- */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#endif
-
/*
* Miscellaneous configurable options
*/
@@ -282,13 +271,13 @@
"load=tftp 200000 ${u-boot}\0" \
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}" \
+ "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
"u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \
"nload=tftp 200000 ${u-boot-nand}\0" \
- "nupdate=nand erase 0 100000;nand write 200000 0 100000" \
+ "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \
"nupd=run nload nupdate\0"
#endif /* __AMCC_COMMON_H */
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 145c3c3..b386057 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -1,4 +1,8 @@
/*
+ * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
+ *
+ * based on previous work by
+ *
* Ulf Samuelsson <ulf@atmel.com>
* Rick Bronson <rick@efn.org>
*
@@ -23,40 +27,52 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __AT91RM9200EK_CONFIG_H__
+#define __AT91RM9200EK_CONFIG_H__
-#define CONFIG_AT91_LEGACY
+#include <asm/sizes.h>
-/* ARM asynchronous clock */
/*
- * from 18.432 MHz crystal
- * (18432000 / 4 * 39)
+ * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
+ * AT91C_MAIN_CLOCK is the frequency of PLLA output
+ * AT91C_MASTER_CLOCK is the peripherial clock
+ * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
+ * set in arch/arm/cpu/arm920t/at91/timer.c)
+ * CONFIG_SYS_HZ is the tick rate for timer tc0
*/
-#define AT91C_MAIN_CLOCK 179712000
-/*
- * peripheral clock
- * (AT91C_MASTER_CLOCK / 3)
- */
-#define AT91C_MASTER_CLOCK 59904000
+#define AT91C_XTAL_CLOCK 18432000
+#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
+#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
+#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
+#define CONFIG_SYS_HZ 1000
-#define AT91_SLOW_CLOCK 32768 /* slow clock */
+/* CPU configuration */
+#define CONFIG_ARM920T
+#define CONFIG_AT91RM9200
+#define CONFIG_AT91RM9200EK
+#define CONFIG_CPUAT91
+#define USE_920T_MMU
-#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
-#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-#define USE_920T_MMU 1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG 1
+/*
+ * Memory Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE SZ_32M
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
/*
* LowLevel Init
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
@@ -73,50 +89,26 @@
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
-#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
-#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-#else
-#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
-#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
-
-/*
- * Memory Configuration
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */
-
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END \
- (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144)
-
/*
* Hardware drivers
*/
-
/*
- * UART Configuration
- *
- * define one of these to choose the DBGU,
- * USART0 or USART1 as console
+ * Choose a USART for serial console
+ * CONFIG_DBGU is DBGU unit on J10
+ * CONFIG_USART1 is USART1 on J14
*/
#define CONFIG_AT91RM9200_USART
#define CONFIG_DBGU
-#undef CONFIG_USART0
-#undef CONFIG_USART1
-/* don't include RTS/CTS flow control support */
-#undef CONFIG_HWFLOW
-/* disable modem initialization stuff */
-#undef CONFIG_MODEM_SUPPORT
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_BAUDRATE 115200
@@ -130,156 +122,75 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_IMI
+#define CONFIG_CMD_USB
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_LOADS
-
-#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
-/* Options for MMC/SD Card */
-#define CONFIG_DOS_PARTITION 1
-#undef CONFIG_MMC
-#define CONFIG_SYS_MMC_BASE 0xFFFB4000
-#define CONFIG_SYS_MMC_BLOCKSIZE 512
/*
* Network Driver Setting
*/
-#define CONFIG_NET_MULTI 1
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_DRIVER_AT91EMAC 1
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-#else
-#define CONFIG_DRIVER_ETHER 1
-#endif
-#define CONFIG_NET_RETRY_COUNT 20
-#define CONFIG_AT91C_USE_RMII
-
-/*
- * AC Characteristics
- * DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns
- */
-#define DATAFLASH_TCSS (0xC << 16)
-#define DATAFLASH_TCHS (0x1 << 24)
-
-#if defined(CONFIG_HAS_DATAFLASH)
-#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
-#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
-/* Logical adress for CS0 */
-#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
-/* Logical adress for CS3 */
-#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000
-#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1
-#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22
-#endif
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AT91EMAC
+#define CONFIG_SYS_RX_ETH_BUFFER 16
+#define CONFIG_RMII
+#define CONFIG_MII
/*
* NOR Flash
*/
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define PHYS_FLASH_SIZE 0x800000 /* 8MB */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define PHYS_FLASH_SIZE SZ_8M
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_PROTECTION
/*
- * Environment Settings
- */
-#ifdef CONFIG_ENV_IS_IN_DATAFLASH
-/*
- * Datasflash Environment Settings
+ * USB Config
*/
-#define CONFIG_ENV_OFFSET 0x4200
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
-/* 8 * 1056 really , but start.s is not OK with this*/
-#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_USB_ATMEL 1
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_USB_KEYBOARD 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION 1
-#else
-/*
- * NOR Flash Environment Settings
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
/*
- * between boot.bin and u-boot.bin.gz
+ * Environment Settings
*/
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000)
-#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
-#else
+#define CONFIG_ENV_IS_IN_FLASH
+
/*
* after u-boot.bin
*/
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
+#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN \
- (CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE)
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
+#define CONFIG_SYS_MONITOR_LEN SZ_256K
/*
* Boot option
*/
#define CONFIG_BOOTDELAY 3
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-/* boot.bin, env, u-boot.bin.gz */
-#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
-#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000)
-#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
-#else
-/* u-boot.bin */
-#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */
-#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
-#define CONFIG_ENV_OVERWRITE 1
-
-/*
- * USB Config
- */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_USB_KEYBOARD 1
-#define CONFIG_USB_STORAGE 1
-#define CONFIG_DOS_PARTITION 1
-
-#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C
-
-#ifdef CONFIG_HARD_I2C
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C_SPEED 0 /* not used */
-#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
-#endif
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
+#define CONFIG_ENV_OVERWRITE
/*
* Shell Settings
*/
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_AUTO_COMPLETE 1
-#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
@@ -288,41 +199,18 @@
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#ifndef __ASSEMBLY__
-/*-----------------------------------------------------------------------
- * Board specific extension for bd_info
- *
- * This structure is embedded in the global bd_info (bd_t) structure
- * and can be used by the board specific code (eg board/...)
- */
-
-struct bd_info_ext {
- /* helper variable for board environment handling
- *
- * env_crc_valid == 0 => uninitialised
- * env_crc_valid > 0 => environment crc in flash is valid
- * env_crc_valid < 0 => environment crc in flash is invalid
- */
- int env_crc_valid;
-};
-#endif
-
-#define CONFIG_SYS_HZ 1000
-/*
- * AT91C_TC0_CMR is implicitly set to
- * AT91C_TC_TIMER_DIV1_CLOCK
- */
-#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
-
/*
* Size of malloc() pool
*/
-#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \
- , 0x1000)
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
+ SZ_4K)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
-#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
-#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/
-#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/
-#endif
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
+ - CONFIG_SYS_GBL_DATA_SIZE)
+
+#define CONFIG_STACKSIZE SZ_32K /* regular stack */
+#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/
+#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/
+#endif /* __AT91RM9200EK_CONFIG_H__ */
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
new file mode 100644
index 0000000..ae60f2e
--- /dev/null
+++ b/include/configs/balloon3.h
@@ -0,0 +1,274 @@
+/*
+ * Balloon3 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_BALLOON3 1 /* Balloon3 board */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOOTCOMMAND \
+ "fpga load 0x0 0x50000 0x62638; " \
+ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "bootm 0xd0000;"
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_TEXT_BASE 0x0
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_STUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FPGA
+#undef CONFIG_LCD
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ "
+#else
+#define CONFIG_SYS_PROMPT "=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0xa1000000
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_ENV_IS_IN_FLASH
+#else
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x000000
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd
+#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e
+#define CONFIG_SYS_GPSR2_VAL 0x7131c000
+#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff
+
+#define CONFIG_SYS_GPCR0_VAL 0x0
+#define CONFIG_SYS_GPCR1_VAL 0x0
+#define CONFIG_SYS_GPCR2_VAL 0x0
+#define CONFIG_SYS_GPCR3_VAL 0x0
+
+#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02
+#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7
+#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff
+#define CONFIG_SYS_GPDR3_VAL 0x000201fe
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b
+#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa
+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa
+#define CONFIG_SYS_GAFR3_L_VAL 0x54510003
+#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0xffffffff
+#define CONFIG_SYS_CCCR 0x00000290
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8
+#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
+#define CONFIG_SYS_MSC2_VAL 0x74a42491
+#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3
+#define CONFIG_SYS_MDREFR_VAL 0x001d8018
+#define CONFIG_SYS_MDMRS_VAL 0x00220022
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+#define CONFIG_SYS_MEM_BUF_IMP 0x0f
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000000
+#define CONFIG_SYS_MCMEM0_VAL 0x00014307
+#define CONFIG_SYS_MCMEM1_VAL 0x00014307
+#define CONFIG_SYS_MCATT0_VAL 0x0001c787
+#define CONFIG_SYS_MCATT1_VAL 0x0001c787
+#define CONFIG_SYS_MCIO0_VAL 0x0001430f
+#define CONFIG_SYS_MCIO1_VAL 0x0001430f
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_BALLOON3LCD
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3"
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * FPGA
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT 1000
+#define CONFIG_MAX_FPGA_DEVICES 1
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 477b94a..98b69e3 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -161,6 +161,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 277ff67..5f457f8 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -169,6 +169,9 @@
#define CONFIG_SYS_LOAD_ADDR (0xa1000000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NOR FLASH
*/
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c021d82..85147d0 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -86,6 +86,7 @@
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
#endif
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_ALT_MEMTEST
@@ -129,68 +130,10 @@
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
-#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
-#else
-#define CONFIG_SYS_SDRAM_SIZE 4096
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_TIMING_3 0x01031000
-#define CONFIG_SYS_DDR_TIMING_0 0x55440804
-#define CONFIG_SYS_DDR_TIMING_1 0x74713a66
-#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b
-#define CONFIG_SYS_DDR_MODE_1 0x00421850
-#define CONFIG_SYS_DDR_MODE_2 0x00100000
-#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x10400100
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03401500
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608
-#define CONFIG_SYS_DDR_CONTROL 0xc7048000
-#define CONFIG_SYS_DDR_CONTROL2 0x24400011
-#define CONFIG_SYS_DDR_CDR1 0x00000000
-#define CONFIG_SYS_DDR_CDR2 0x00000000
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-#define CONFIG_SYS_DDR_DEBUG_18 0x40100400
-
-#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf
-#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff
-#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG
-#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG
-#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3
-#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0
-#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1
-#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2
-#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1
-#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2
-#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL
-#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL
-#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT
-#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL
-#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4
-#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5
-#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL
-#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL
-#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL
-#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2
-#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1
-#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2
-#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN
-#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS
-#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE
-#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18
-
-#endif
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* Local Bus Definitions
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 200b61e..d1c1a48 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -145,6 +145,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
@@ -339,8 +342,6 @@
#define LED_IRDA1 2
#define LED_IRDA2 4
#define LED_IRDA3 6
-#define CRADLE_LED_SET_REG GPSR2
-#define CRADLE_LED_CLR_REG GPCR2
/* SuperIO defines */
#define CRADLE_SIO_INDEX 0x2e
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index 0661d65..ae05734 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -181,6 +181,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
# if 0
/* FIXME: switch to _documented_ registers */
/*
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 9c46c5b..d53acbf 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -28,6 +28,7 @@
* (easy to change)
*/
#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_CPU_PXA320
#define CONFIG_DELTA 1 /* Delta board */
/* #define CONFIG_LCD 1 */
@@ -217,6 +218,9 @@
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* NAND Flash
*/
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 2815771..c47e17c 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -38,6 +38,8 @@
#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
@@ -306,4 +308,7 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
#endif /* __CONFIG_H */
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 4ff4a85..8d8af93 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -42,7 +42,7 @@
#define CONFIG_MISC_INIT_R
/*--------------------------------------------------------------------------*/
-
+#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
@@ -98,12 +98,14 @@
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM 0x20000000
-#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_BASE 0x20000000
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
- PHYS_SDRAM_SIZE - 0x00400000 - \
+ CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
@@ -249,6 +251,7 @@
/* FLASH organization */
/* NOR-FLASH */
+#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_FLASH_CFI_DRIVER 1
@@ -396,16 +399,6 @@
"nandboot=run bootargsdefaults;" \
"set bootargs $(bootargs) root=initramfs boot=nand " \
";bootm $(kerneladdr)\0" \
- "uu=run update_uboot\0" \
- "ur=run update_root;run nk\0" \
- "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
- "boot=local " \
- ";echo $(bootargs)" \
- ";dhcp uImage_cpux9k2;bootm\0" \
- "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \
- "boot=nand " \
- ";echo $(bootargs)" \
- ";dhcp uImage_cpux9k2;bootm\0" \
" "
/*--------------------------------------------------------------------------*/
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index ccfc660..43e5e87 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -223,4 +223,9 @@
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
#define CONFIG_SYS_MAXARGS 16
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - CONFIG_SYS_GBL_DATA_SIZE)
+
#endif /* _CONFIG_EDMINIV2_H */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 88c62d1..9425237 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -147,6 +147,13 @@
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#undef CONFIG_SYS_ARM_WITHOUT_RELOC
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 9cb0d42..007cceb 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -192,6 +192,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* JFFS2 partitions
*
diff --git a/include/configs/jornada.h b/include/configs/jornada.h
new file mode 100644
index 0000000..69a045c
--- /dev/null
+++ b/include/configs/jornada.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2010 (C)
+ * Kristoffer Ericson <kristoffer.ericson@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1110 1 /* This is an SA110 CPU */
+#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */
+#define CONFIG_SYS_FLASH_PROTECTION 1
+#define CONFIG_SYS_ARM_WITHOUT_RELOC 1
+
+#define CONFIG_SYS_TEXT_BASE 0xC1F00000
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+#undef CONFIG_USE_IRQ
+
+/* Console setting */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size for initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SA1100_SERIAL 1
+#define CONFIG_SERIAL3 1 /* we use serial 3 */
+#define CONFIG_BAUDRATE 19200
+#define CONFIG_LOADS_ECHO 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1"
+#define CONFIG_BOOTCOMMAND "run boot_kernel"
+#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
+#define CONFIG_SYS_LOAD_ADDR 0xc0000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "HP Jornada# "
+#define CONFIG_SYS_CBSIZE 256 /* console buffsize */
+#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */
+#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_SYS_FLASH_ERASE_TOUT (4096)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (4096)
+#define CONFIG_SYS_FLASH_INCREMENT 0x02000000
+#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */
+#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
+#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 260
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1
+#define CONFIG_SYS_MONITOR_LEN 0x00040000
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+#define CONFIG_FLASH_SHOW_PROGRESS 1
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR 0x00040000
+#define CONFIG_ENV_OFFSET 0x00040000
+#define CONFIG_ENV_SIZE 0x00040000
+#define CONFIG_ENV_SECT_SIZE 0x00040000
+#define CONFIG_ENV_OVERWRITE 1
+
+/*
+ Monitor - 0x00000000 - 0x00040000 (256kb)
+ Environment - 0x00040000 - 0x00080000 (256kb)
+ Kernel - 0x00080000 - 0x00380000 (3mb)
+ Rootfs - 0x00380000 - 0x........ (rest)
+*/
+
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_INIT_SP_ADDR 0x0
+#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=jornada7xx-0"
+#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\
+ "3m(kernel),-(user);"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "flash_kernel=protect off all; " \
+ "erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \
+ "flash_uboot=protect off all; " \
+ "erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \
+ "boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0"
+#endif /* __CONFIG_H */
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index 0a69210..3a99ec2 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -176,6 +176,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
#define FPGA_REGS_BASE_PHYSICAL 0x08000000
/*
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index d003710..a4e92cc 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -193,6 +193,17 @@
#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
CONFIG_SYS_NS16550_COM2 }
+#define CONFIG_POST_UART { \
+ "UART test", \
+ "uart", \
+ "This test verifies the UART operation.", \
+ POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
+ &uart_post_test, \
+ NULL, \
+ NULL, \
+ CONFIG_SYS_POST_UART \
+ }
+
#define CONFIG_POST_WATCHDOG { \
"Watchdog timer test", \
"watchdog", \
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 8864f3a..6165473 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -30,8 +30,8 @@
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_SKIP_RELOCATE_UBOOT
-#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
-#define CONFIG_MX51_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
new file mode 100644
index 0000000..926728b
--- /dev/null
+++ b/include/configs/palmld.h
@@ -0,0 +1,276 @@
+/*
+ * Palm LifeDrive configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
+#define CONFIG_PALMLD 1 /* Palm LifeDrive board */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \
+ "source 0xa0000000; " \
+ "else " \
+ "bootm 0x0x60000; " \
+ "fi; "
+#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_IDE
+#define CONFIG_LCD
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_LQ038J7DH53
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ "
+#else
+#define CONFIG_SYS_PROMPT "=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+
+#define CONFIG_SYS_MONITOR_BASE 0
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#else
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_ADDR 0x40000
+#define CONFIG_ENV_SIZE 0x4000
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_LBA48
+#undef CONFIG_IDE_LED
+#undef CONFIG_IDE_RESET
+
+#define __io
+
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+
+#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x10
+#define CONFIG_SYS_ATA_REG_OFFSET 0x10
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x10
+
+#define CONFIG_SYS_ATA_STRIDE 1
+#endif
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012
+#define CONFIG_SYS_GAFR1_L_VAL 0x69988056
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa
+#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x01040001
+#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
+#define CONFIG_SYS_GAFR3_U_VAL 0x00000009
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000000
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+#define CONFIG_SYS_GPCR3_VAL 0x00000000
+#define CONFIG_SYS_GPDR0_VAL 0xc26b0000
+#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93
+#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff
+#define CONFIG_SYS_GPDR3_VAL 0x006ff38d
+#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee
+#define CONFIG_SYS_GPSR1_VAL 0x03affdae
+#define CONFIG_SYS_GPSR2_VAL 0x07554000
+#define CONFIG_SYS_GPSR3_VAL 0x01bc0785
+
+#define CONFIG_SYS_PSSR_VAL 0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN 0x01ffffff
+#define CONFIG_SYS_CCCR 0x02000210
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x7ff844c8
+#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4
+#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8
+#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd
+#define CONFIG_SYS_MDREFR_VAL 0x201fa031
+#define CONFIG_SYS_MDMRS_VAL 0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000003
+#define CONFIG_SYS_MCMEM0_VAL 0x0001c391
+#define CONFIG_SYS_MCMEM1_VAL 0x0001c391
+#define CONFIG_SYS_MCATT0_VAL 0x0001c391
+#define CONFIG_SYS_MCATT1_VAL 0x0001c391
+#define CONFIG_SYS_MCIO0_VAL 0x00014611
+#define CONFIG_SYS_MCIO1_VAL 0x0001c391
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
new file mode 100644
index 0000000..fe87648
--- /dev/null
+++ b/include/configs/palmtc.h
@@ -0,0 +1,248 @@
+/*
+ * Palm Tungsten|C configuration file
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_PXA250 1 /* Intel PXA255 CPU */
+#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
+ "source 0xa0000000; " \
+ "else " \
+ "bootm 0x80000; " \
+ "fi; "
+#define CONFIG_BOOTARGS \
+ "console=tty0 console=ttyS0,115200"
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_LZMA /* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ * STUART - the lower serial port on Colibri board
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MMC
+#define CONFIG_LCD
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_SYS_MMC_BASE 0xF0000000
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_ACX517AKN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "$ "
+#else
+#define CONFIG_SYS_PROMPT "=> "
+#endif
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+
+/*
+ * Clock Configuration
+ */
+#undef CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */
+#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
+/*
+ * NOR FLASH
+ */
+#ifdef CONFIG_CMD_FLASH
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 64
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#else
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE 0x0
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+
+#define CONFIG_ENV_SIZE 0x4000
+#define CONFIG_ENV_ADDR 0x40000
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL 0x00011004
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008
+#define CONFIG_SYS_GAFR1_L_VAL 0x60888050
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa
+#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
+#define CONFIG_SYS_GPCR0_VAL 0x0
+#define CONFIG_SYS_GPCR1_VAL 0x0
+#define CONFIG_SYS_GPCR2_VAL 0x0
+#define CONFIG_SYS_GPDR0_VAL 0xcfff8140
+#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3
+#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
+#define CONFIG_SYS_GPSR0_VAL 0x00010f8f
+#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5
+#define CONFIG_SYS_GPSR2_VAL 0x03fe0800
+
+#define CONFIG_SYS_PSSR_VAL PSSR_RDH
+
+/* Clock setup:
+ * CKEN[1] - PWM1 ; CKEN[6] - FFUART
+ * CKEN[12] - MMC ; CKEN[16] - LCD
+ */
+#define CONFIG_SYS_CKEN 0x00011042
+#define CONFIG_SYS_CCCR 0x00000161
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL 0x800092c2
+#define CONFIG_SYS_MSC1_VAL 0x80008000
+#define CONFIG_SYS_MSC2_VAL 0x80008000
+#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9
+#define CONFIG_SYS_MDREFR_VAL 0x00118018
+#define CONFIG_SYS_MDMRS_VAL 0x00220032
+#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe
+#define CONFIG_SYS_SXCNFG_VAL 0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL 0x00000000
+#define CONFIG_SYS_MCMEM0_VAL 0x00010504
+#define CONFIG_SYS_MCMEM1_VAL 0x00010504
+#define CONFIG_SYS_MCATT0_VAL 0x00010504
+#define CONFIG_SYS_MCATT1_VAL 0x00010504
+#define CONFIG_SYS_MCIO0_VAL 0x00010e04
+#define CONFIG_SYS_MCIO1_VAL 0x00010e04
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 9e69411..3b6e60a 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -179,6 +179,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 6c1defc..4581674 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -292,6 +292,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
diff --git a/include/configs/qong.h b/include/configs/qong.h
index f26ced1..426d90d 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -102,6 +102,7 @@
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
+#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* CONFIG_CMD_USB */
@@ -124,25 +125,16 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SPI
-#define CONFIG_CMD_DATE
-#define BOARD_LATE_INIT
-/*
- * You can compile in a MAC address and your custom net settings by using
- * the following syntax.
- *
- * #define CONFIG_ETHADDR xx:xx:xx:xx:xx:xx
- * #define CONFIG_SERVERIP <server ip>
- * #define CONFIG_IPADDR <board ip>
- * #define CONFIG_GATEWAYIP <gateway ip>
- * #define CONFIG_NETMASK <your netmask>
- */
+#define BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 5
@@ -164,7 +156,7 @@
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"uboot_addr=A0000000\0" \
- "kernel_addr=A00A0000\0" \
+ "kernel_addr=A00C0000\0" \
"ramdisk_addr=A0300000\0" \
"u-boot=qong/u-boot.bin\0" \
"kernel_addr_r=80800000\0" \
@@ -296,10 +288,14 @@ extern int qong_nand_rdy(void *chip);
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
+ "nand0=gen_nand"
#define MTDPARTS_DEFAULT \
- "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \
- "128k(env2),2432k(kernel),13m(ramdisk),-(user)"
+ "mtdparts=physmap-flash.0:" \
+ "512k(U-Boot),128k(env1),128k(env2)," \
+ "2304k(kernel),13m(ramdisk),-(user);" \
+ "gen_nand:" \
+ "128m(nand)"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index fa5aae8..4743495 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -212,6 +212,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* GPIO settings
*/
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index bcc8140..996afa3 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -41,7 +41,7 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x81fc0000)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000)
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 44a6f8b..a2ecbe5 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -29,8 +29,8 @@
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
-#define CONFIG_MX51_HCLK_FREQ 24000000
-#define CONFIG_MX51_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 24000000
+#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index d3e22d9..c9d9c69 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -10,7 +10,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -19,8 +19,8 @@
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_H
+#define __CONFIG_H
/*
* High Level Board Configuration Options
@@ -28,20 +28,13 @@
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
-#undef BOARD_LATE_INIT
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-#undef CONFIG_USE_IRQ
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-
/*
* Environment settings
*/
-#define CONFIG_ENV_SIZE 0x4000
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128
-
-#define CONFIG_ENV_OVERWRITE /* override default environment */
-
+#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa4000000 uImage; then " \
"bootm 0xa4000000; " \
@@ -49,13 +42,16 @@
"if usb reset && fatload usb 0 0xa4000000 uImage; then " \
"bootm 0xa4000000; " \
"fi; " \
- "bootm 0x40000;"
+ "if ide reset && fatload ide 0 0xa4000000 uImage; then " \
+ "bootm 0xa4000000; " \
+ "fi; " \
+ "bootm 0x60000;"
#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
#define CONFIG_TIMESTAMP
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_LZMA /* LZMA compression support */
/*
@@ -79,7 +75,7 @@
#undef CONFIG_LCD
#define CONFIG_CMD_IDE
-#ifdef CONFIG_ONENAND_U_BOOT
+#ifdef CONFIG_ONENAND
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_ONENAND
#else
@@ -97,9 +93,9 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_DRIVER_DM9000 1
-#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
-#define DM9000_IO (CONFIG_DM9000_BASE)
-#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */
+#define DM9000_IO (CONFIG_DM9000_BASE)
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_BOOTP_BOOTFILESIZE
@@ -116,6 +112,7 @@
#define CONFIG_PXA_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#endif
@@ -123,8 +120,8 @@
* KGDB
*/
#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
@@ -133,29 +130,27 @@
#define CONFIG_SYS_HUSH_PARSER 1
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "$ "
#else
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "=> "
#endif
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_DEVICE_NULLDEV 1
/*
* Clock Configuration
*/
-#undef CONFIG_SYS_CLKS_IN_HZ
-#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
-#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
+#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */
/*
* Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
@@ -166,33 +161,58 @@
/*
* DRAM Map
*/
-#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+
+#ifdef CONFIG_RAM_256M
#define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+#endif
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
+#ifdef CONFIG_RAM_256M
#define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */
+#else
+#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
+#endif
-#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
-#define CONFIG_SYS_LOAD_ADDR (0x5c000000)
+#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
+#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000)
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048)
/*
* NOR FLASH
*/
+#define CONFIG_SYS_MONITOR_BASE 0x0
+#define CONFIG_SYS_MONITOR_LEN 0x40000
+#define CONFIG_ENV_ADDR \
+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x4000
+
#if defined(CONFIG_CMD_FLASH) /* NOR */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#ifdef CONFIG_RAM_256M
#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+#endif
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
+#ifdef CONFIG_RAM_256M
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+#else
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
@@ -200,26 +220,30 @@
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_FLASH_PROTECTION 1
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH 1
+
+/*
+ * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the
+ * flash consists of 0x20000 bytes big sectors.
+ */
+#if (CONFIG_ENV_ADDR <= 0x18000)
+#define CONFIG_ENV_SECT_SIZE 0x8000
+#else
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
#elif defined(CONFIG_CMD_ONENAND) /* OneNAND */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ONENAND_BASE 0x00000000
+
#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SECT_SIZE 0x20000
#else /* No flash */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ENV_IS_NOWHERE
#endif
-#define CONFIG_SYS_MONITOR_BASE 0x000000
-#define CONFIG_SYS_MONITOR_LEN 0x40000
-
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE 0x40000
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
/*
* IDE
*/
@@ -230,15 +254,15 @@
#define __io
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 1
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
-#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
+#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
-#define CONFIG_SYS_ATA_REG_OFFSET 0x120
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x120
+#define CONFIG_SYS_ATA_REG_OFFSET 0x120
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x120
#define CONFIG_SYS_ATA_STRIDE 2
#endif
@@ -284,7 +308,11 @@
#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa
#define CONFIG_SYS_MSC1_VAL 0x02ccf974
#define CONFIG_SYS_MSC2_VAL 0x00000000
+#ifdef CONFIG_RAM_256M
#define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3
+#else
+#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3
+#endif
#define CONFIG_SYS_MDREFR_VAL 0x201fe01e
#define CONFIG_SYS_MDMRS_VAL 0x00000000
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
@@ -306,13 +334,13 @@
* LCD
*/
#ifdef CONFIG_LCD
-#define CONFIG_VOIPAC_LCD
+#define CONFIG_VOIPAC_LCD
#endif
/*
* USB
*/
-#ifdef CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index 9a20cce..a961a27 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -183,6 +183,10 @@
#define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */
#define CONFIG_ENV_SIZE 0x2000
+#define PHYS_SDRAM_1 WEP_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
#undef CONFIG_ENV_OVERWRITE /* env is not writable now */
/*
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 1329f0f..67d4106 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -167,6 +167,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index cd56ce7..2ff9a28 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -174,6 +174,9 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/*
* FLASH and environment organization
*/
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index f68461b..9606b53 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -53,6 +53,9 @@
#define CONFIG_SYS_DRAM_BASE 0xa0000000
#define CONFIG_SYS_DRAM_SIZE 0x04000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
/* FLASH organization */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index a5a873b..ce65d1f 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -41,8 +41,9 @@
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE)
+#define CONFIG_SYS_MALLOC_LEN (128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 512
+#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOTCOMMAND \
"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
@@ -56,7 +57,7 @@
#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
-
+#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_LZMA /* LZMA compression support */
/*
@@ -175,6 +176,9 @@ unsigned char zipitz2_spi_read(void);
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048)
+
/*
* NOR FLASH
*/
@@ -218,7 +222,7 @@ unsigned char zipitz2_spi_read(void);
#define CONFIG_SYS_GPCR3_VAL 0x00000000
#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
-#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff
+#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
#define CONFIG_SYS_GPSR0_VAL 0x06080400
#define CONFIG_SYS_GPSR1_VAL 0x007f0000
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index d0fc138..c33ca2d 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -35,6 +35,7 @@
* (easy to change)
*/
#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
+#define CONFIG_CPU_PXA320
#define CONFIG_ZYLONITE 1 /* Zylonite board */
/* #define CONFIG_LCD 1 */
@@ -189,6 +190,8 @@
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
/*
* NAND Flash
diff --git a/include/lattice.h b/include/lattice.h
index 33d2ac3..75729b6 100755
--- a/include/lattice.h
+++ b/include/lattice.h
@@ -308,6 +308,7 @@ int lattice_info(Lattice_desc *desc);
void ispVMStart(void);
void ispVMEnd(void);
+extern void ispVMFreeMem(void);
signed char ispVMCode(void);
void ispVMDelay(unsigned short int a_usMicroSecondDelay);
void ispVMCalculateCRC32(unsigned char a_ucData);
diff --git a/include/post.h b/include/post.h
index 625da55..daa9047 100644
--- a/include/post.h
+++ b/include/post.h
@@ -57,8 +57,8 @@
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
#elif defined (CONFIG_MPC85xx)
-#include <asm/cpm_85xx.h>
-#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
+#include <asm/immap_85xx.h>
+#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_4xx)
#define _POST_WORD_ADDR \
diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds
index c572557..5f95c87 100644
--- a/nand_spl/board/karo/tx25/u-boot.lds
+++ b/nand_spl/board/karo/tx25/u-boot.lds
@@ -53,6 +53,11 @@ SECTIONS
*(.data.rel.ro)
}
+ . = ALIGN(4);
+ __rel_dyn_start = .;
+ __rel_dyn_end = .;
+ __dynsym_start = .;
+
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
@@ -67,4 +72,12 @@ SECTIONS
__bss_start = .;
.bss : { *(.bss) }
_end = .;
+ /DISCARD/ : { *(.bss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynsym*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.hash*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
}
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index 4d6db14..ccd0af2 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -224,7 +224,8 @@ static int nand_load(struct mtd_info *mtd, unsigned int offs,
#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
void board_init_f (ulong bootflag)
{
- relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE);
+ relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+ CONFIG_SYS_TEXT_BASE);
}
#endif
diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c
index 959f162..21ed3fc 100644
--- a/nand_spl/nand_boot_fsl_nfc.c
+++ b/nand_spl/nand_boot_fsl_nfc.c
@@ -266,7 +266,8 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
void board_init_f (ulong bootflag)
{
- relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE);
+ relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
+ CONFIG_SYS_TEXT_BASE);
}
#endif
diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile
index ac7a8f0..a86bc00 100644
--- a/onenand_ipl/board/vpac270/Makefile
+++ b/onenand_ipl/board/vpac270/Makefile
@@ -1,5 +1,6 @@
-IPL =onenand_ipl
+
include $(TOPDIR)/config.mk
+include $(TOPDIR)/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
@@ -25,7 +26,7 @@ ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand
all: $(obj).depend $(ALL)
$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x0800 -O binary $< $@
$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index 0062360..3f47449 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -452,30 +452,66 @@ static int memory_post_tests (unsigned long start, unsigned long size)
return ret;
}
-int memory_post_test (int flags)
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
- int ret = 0;
bd_t *bd = gd->bd;
- unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
- 256 << 20 : bd->bi_memsize) - (1 << 20);
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = (bd->bi_memsize >= 256 << 20 ?
+ 256 << 20 : bd->bi_memsize) - (1 << 20);
/* Limit area to be tested with the board info struct */
- if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
- memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+ if ((*vstart) + (*size) > (ulong)bd)
+ *size = (ulong)bd - *vstart;
+
+ return 0;
+}
- if (flags & POST_SLOWTEST) {
- ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
- } else { /* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 1;
+}
- unsigned long i;
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 0;
+}
- for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
- if (ret == 0)
- ret = memory_post_tests (i << 20, 0x800);
- if (ret == 0)
- ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+ return;
+}
+
+int memory_post_test(int flags)
+{
+ int ret = 0;
+ phys_addr_t phys_offset = 0;
+ u32 memsize, vstart;
+
+ arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+
+ do {
+ if (flags & POST_SLOWTEST) {
+ ret = memory_post_tests(vstart, memsize);
+ } else { /* POST_NORMAL */
+ unsigned long i;
+ for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+ if (ret == 0)
+ ret = memory_post_tests(i << 20, 0x800);
+ if (ret == 0)
+ ret = memory_post_tests(
+ (i << 20) + 0xff800, 0x800);
+ }
}
- }
+ } while (!ret &&
+ !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
+
+ arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+ if (ret)
+ arch_memory_failure_handle();
return ret;
}
diff --git a/post/tests.c b/post/tests.c
index a4066f9..5f59fbb 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -165,6 +165,9 @@ struct post_test post_list[] =
},
#endif
#if CONFIG_POST & CONFIG_SYS_POST_UART
+#if defined(CONFIG_POST_UART)
+ CONFIG_POST_UART,
+#else
{
"UART test",
"uart",
@@ -175,6 +178,7 @@ struct post_test post_list[] =
NULL,
CONFIG_SYS_POST_UART
},
+#endif /* CONFIG_POST_UART */
#endif
#if CONFIG_POST & CONFIG_SYS_POST_ETHER
{