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| author | Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> | 2010-08-26 23:24:22 +0400 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-10-19 22:47:31 +0200 |
| commit | 80124df14f43e08c86892f5344c23cff1e943dbc (patch) | |
| tree | 83e6350138a7221cf7b10eef1fef6c2e0da3bb6d | |
| parent | 11934fbf520a02e3ddff95607c60e79efad7dab1 (diff) | |
| download | u-boot-imx-80124df14f43e08c86892f5344c23cff1e943dbc.zip u-boot-imx-80124df14f43e08c86892f5344c23cff1e943dbc.tar.gz u-boot-imx-80124df14f43e08c86892f5344c23cff1e943dbc.tar.bz2 | |
PXA: fix MDREFR[APD] bit setting
pxa_mem_setup macro use r6 to store CONFIG_SYS_MDREFR_VAL during memory
initialization. This reg is modified during execution of pxa_wait_ticks.
Later we use r6 to setup MDREFR[APD] bit. As result MDREFR[APD] is always
zero.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
| -rw-r--r-- | arch/arm/include/asm/arch-pxa/macro.h | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 035a57e..85958dd 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,7 +102,11 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE + * and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not + * use this regs for other purpose inside this macro. + * + * Clobbered regs: r3, r4, r5, r6, r7 */ .macro pxa_mem_setup /* This comes handy when setting MDREFR */ @@ -157,7 +161,7 @@ bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 + mov r7, r4 lsl r4, #20 lsr r4, #20 /* Get a valid DRI field */ @@ -187,12 +191,12 @@ * 6) Initialize SDRAM */ - bic r6, #MDREFR_SLFRSH - str r6, [r3, #MDREFR_OFFSET] + bic r7, #MDREFR_SLFRSH + str r7, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] - orr r6, #MDREFR_E1PIN - str r6, [r3, #MDREFR_OFFSET] + orr r7, #MDREFR_E1PIN + str r7, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] /* @@ -250,8 +254,8 @@ */ ldr r4, [r3, #MDREFR_OFFSET] - and r6, r6, #MDREFR_APD - orr r4, r4, r6 + and r7, r7, #MDREFR_APD + orr r4, r4, r7 str r4, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] .endm |