Add support for Bluewater Systems Snapper 9260/9G20 modules

Add support for Bluewater Systems AT91 based Snapper 9260 and 9G20
single board computer modules. Includes NAND flash and Ethernet
support.

Signed-off-by: Ryan Mallon <ryan@bluewatersys.com>

4 files changed, 418 insertions, 0 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index c462ae2..5686d4f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -302,6 +302,11 @@ Dan Malek <dan@embeddedalley.com>
 	stxssa		MPC85xx
 	stxxtc		MPC8xx
 
+Ryan Mallon <ryan@bluewatersys.com>
+
+	snapper9260		ARM926EJS (AT91SAM9260 SoC)
+	snapper9g20		ARM926EJS (AT91SAM9G20 SoC)
+
 Eran Man <eran@nbase.co.il>
 
 	EVB64260_750CX	MPC750CX
diff --git a/board/bluewater/snapper9260/Makefile b/board/bluewater/snapper9260/Makefile
new file mode 100644
index 0000000..4fccdaa
--- /dev/null
+++ b/board/bluewater/snapper9260/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= snapper9260.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c
new file mode 100644
index 0000000..60c55e9
--- /dev/null
+++ b/board/bluewater/snapper9260/snapper9260.c
@@ -0,0 +1,169 @@
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <net.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET	(0 << 1)
+#define IO_EXP_ETH_POWER	(1 << 1)
+
+static void macb_hw_init(void)
+{
+	struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+	unsigned long erstl;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+	/* Disable pull-ups to prevent PHY going into test mode */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA18),
+	       &pioa->pudr);
+
+	/* Power down ethernet */
+	pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
+	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
+
+	/* Hold ethernet in reset */
+	pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
+	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
+
+	/* Enable ethernet power */
+	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
+
+	/* Need to reset PHY -> 500ms reset */
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
+	       AT91_RSTC_MR_URSTEN, &rstc->mr);
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+	/* Wait for end hardware reset */
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
+		;
+
+	/* Restore NRST value */
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	/* Bring the ethernet out of reset */
+	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
+
+	/* The phy internal reset take 21ms */
+	udelay(21 * 1000);
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA14) |
+	       pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA18),
+	       &pioa->puer);
+
+	at91_macb_hw_init();
+}
+
+static void nand_hw_init(void)
+{
+	struct at91_smc *smc       = (struct at91_smc    *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Enable CS3 as NAND/SmartMedia */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+int board_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable PIO clocks */
+	writel((1 << ATMEL_ID_PIOA) |
+	       (1 << ATMEL_ID_PIOB) |
+	       (1 << ATMEL_ID_PIOC), &pmc->pcer);
+
+	/* The mach-type is the same for both Snapper 9260 and 9G20 */
+	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Initialise peripherals */
+	at91_seriald_hw_init();
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	nand_hw_init();
+	macb_hw_init();
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+void reset_phy(void)
+{
+}
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
new file mode 100644
index 0000000..7def16f
--- /dev/null
+++ b/include/configs/snapper9260.h
@@ -0,0 +1,191 @@
+/*
+ * Bluewater Systems Snapper 9260 and 9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <asm/sizes.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x20000000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* External Crystal, in Hz */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CONFIG_SYS_HZ			1000
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_FIT
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM1 + 0x1000 - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Mem test settings */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
+
+/* NAND Flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_TFTP_PORT
+#define CONFIG_TFTP_TSIZE
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+
+/* GPIOs and IO expander */
+#define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP		1
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x28
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x28, 16} }
+
+/* UARTs/Serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+#define CONFIG_SYS_PROMPT		"Snapper> "
+
+/* I2C - Bit-bashed */
+#define CONFIG_SOFT_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_I2C_MULTI_BUS
+#define I2C_INIT do {							\
+		at91_set_gpio_output(AT91_PIN_PA23, 1);			\
+		at91_set_gpio_output(AT91_PIN_PA24, 1);			\
+		at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1);	\
+		at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1);	\
+	} while (0)
+#define I2C_SOFT_DECLARATIONS
+#define I2C_ACTIVE
+#define I2C_TRISTATE	at91_set_gpio_input(AT91_PIN_PA23, 1);
+#define I2C_READ	at91_get_gpio_value(AT91_PIN_PA23);
+#define I2C_SDA(bit) do {						\
+		if (bit) {						\
+			at91_set_gpio_input(AT91_PIN_PA23, 1);		\
+		} else {						\
+			at91_set_gpio_output(AT91_PIN_PA23, 1);		\
+			at91_set_gpio_value(AT91_PIN_PA23, bit);	\
+		}							\
+	} while (0)
+#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
+#define I2C_DELAY	udelay(2)
+
+/* Boot options */
+#define CONFIG_SYS_LOAD_ADDR		0x23000000
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Environment settings */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_ENV_SIZE			(256 << 10)
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BOOTARGS			"console=ttyS0,115200 ip=any"
+
+/* Console settings */
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_EXTBDINFO
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* U-Boot memory settings */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+#define CONFIG_STACKSIZE		(256 << 10)
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_GPIO
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+
+#endif /* __CONFIG_H */