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| author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2011-01-27 10:06:08 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2011-02-02 16:38:41 +0900 |
| commit | 68260aab93afd7f4570d09cc63ed32752841039d (patch) | |
| tree | 89a905414ef770719b207f4e1b3ab3d8c296b74f | |
| parent | 3d0075fa7ad7357de48ade6ef05089542dd762cf (diff) | |
| download | u-boot-imx-68260aab93afd7f4570d09cc63ed32752841039d.zip u-boot-imx-68260aab93afd7f4570d09cc63ed32752841039d.tar.gz u-boot-imx-68260aab93afd7f4570d09cc63ed32752841039d.tar.bz2 | |
net: sh_eth: add cache handling
Some CPU needs cache handling. So this patch add the config of
CONFIG_SH_ETHER_CACHE_WRITEBACK, and it calls wback function.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| -rw-r--r-- | README | 3 | ||||
| -rw-r--r-- | drivers/net/sh_eth.c | 9 |
2 files changed, 12 insertions, 0 deletions
@@ -901,6 +901,9 @@ The following options need to be configured: CONFIG_SH_ETHER_PHY_ADDR Define the ETH PHY's address + CONFIG_SH_ETHER_CACHE_WRITEBACK + If this option is set, the driver enables cache flush. + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 86cc324..53d918d 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -36,6 +36,12 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif +#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK +#define flush_cache_wback(addr, len) \ + dcache_wback_range((u32)addr, (u32)(addr + len - 1)) +#else +#define flush_cache_wback(...) +#endif #define SH_ETH_PHY_DELAY 50000 @@ -197,6 +203,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) } /* Update tx descriptor */ + flush_cache_wback(packet, len); port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); port_info->tx_desc_cur->td1 = len << 16; /* Must preserve the end of descriptor list indication */ @@ -312,6 +319,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & ~(TX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); port_info->tx_desc_cur = port_info->tx_desc_base; @@ -361,6 +369,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & ~(RX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); |