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| author | Ed Swarthout <Ed.Swarthout@freescale.com> | 2007-07-11 14:52:01 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2007-07-11 23:43:21 +0200 |
| commit | 571f49fa717004ca4268b4e24057efc7bf9f987b (patch) | |
| tree | 658f90785e7e4787b75b143f89de396dec0297b1 | |
| parent | ba5feb12581bb2912ce301e4866b71f846e9fc07 (diff) | |
| download | u-boot-imx-571f49fa717004ca4268b4e24057efc7bf9f987b.zip u-boot-imx-571f49fa717004ca4268b4e24057efc7bf9f987b.tar.gz u-boot-imx-571f49fa717004ca4268b4e24057efc7bf9f987b.tar.bz2 | |
Support PCIe extended config registers
FSL PCIe block has extended cfg registers in the 100 and 400 range.
For example, to read the LTSSM register: pci display <busn>.0 404 1
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| -rw-r--r-- | drivers/pci_indirect.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c index d7be081..a8220fb 100644 --- a/drivers/pci_indirect.c +++ b/drivers/pci_indirect.c @@ -45,7 +45,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ } -#elif defined(CONFIG_E500) +#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ static int \ indirect_##rw##_config_##size(struct pci_controller *hose, \ @@ -55,7 +55,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \ b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ b = b - hose->first_busno; \ dev = PCI_BDF(b, d, f); \ - *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \ + *(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \ sync(); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ return 0; \ |