Merge branch 'master' into next

Conflicts:
	Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>

85 files changed, 7365 insertions, 267 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 7a13d28..f10e924 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -62,6 +62,10 @@ Oliver Brown <obrown@adventnetworks.com>
 
 	gw8260		MPC8260
 
+Cyril Chemparathy <cyril@ti.com>
+
+	tnetv107x_evm	tnetv107x
+
 Conn Clark <clark@esteem.com>
 
 	ESTEEM192E	MPC8xx
@@ -228,6 +232,7 @@ Ilko Iliev <iliev@ronetix.at>
 
 	PM9261		AT91SAM9261
 	PM9263		AT91SAM9263
+	PM9G45		ARM926EJS (AT91SAM9G45 SoC)
 
 Gary Jennejohn <garyj@denx.de>
 
@@ -349,6 +354,10 @@ Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240		MPC8240
 	sbc405		PPC405GP
 
+Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+
+	da850evm	ARM926EJS (DA850/OMAP-L138)
+
 Ricardo Ribalda <ricardo.ribalda@uam.es>
 
 	ml507 		PPC440x5
@@ -525,6 +534,10 @@ Unknown / orphaned boards:
 #	Board		CPU						#
 #########################################################################
 
+Albert ARIBAUD <albert.aribaud@free.fr>
+
+	edminiv2	ARM926EJS (Orion5x SoC)
+
 Rowel Atienza <rowel@diwalabs.com>
 
 	armadillo	ARM720T
@@ -600,6 +613,10 @@ Kshitij Gupta <kshitij@ti.com>
 	omap1510inn	ARM925T
 	omap1610inn	ARM926EJS
 
+Vaibhav Hiremath <hvaibhav@ti.com>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+
 Grazvydas Ignotas <notasas@gmail.com>
 
 	omap3_pandora	ARM CORTEX-A8 (OMAP3xx SoC)
@@ -626,14 +643,15 @@ Simon Kagstrom <simon.kagstrom@netinsight.net>
 
        openrd_base     ARM926EJS (Kirkwood SoC)
 
-Minkyu Kang <mk7.kang@samsung.com>
-
-	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
-
 Nishant Kamat <nskamat@ti.com>
 
 	omap1610h2	ARM926EJS
 
+Minkyu Kang <mk7.kang@samsung.com>
+
+	s5p_goni	ARM CORTEX-A8 (S5PC110 SoC)
+	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
+
 Frederik Kriewitz <frederik@kriewitz.eu>
 
 	devkit8000	ARM CORTEX-A8 (OMAP3530 SoC)
diff --git a/MAKEALL b/MAKEALL
index 2527352..d6d5f5b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -561,6 +561,7 @@ LIST_ARM9="			\
 	cp946es			\
 	cp966			\
 	da830evm		\
+	da850evm		\
 	edb9301			\
 	edb9302			\
 	edb9302a		\
@@ -569,6 +570,7 @@ LIST_ARM9="			\
 	edb9312			\
 	edb9315			\
 	edb9315a		\
+	edminiv2		\
 	guruplug		\
 	imx27lite		\
 	lpd7a400		\
@@ -635,12 +637,14 @@ LIST_ARM11="			\
 	mx31pdk_nand		\
 	qong			\
 	smdk6400		\
+	tnetv107x_evm		\
 "
 
 #########################################################################
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="		\
+	am3517_evm		\
 	devkit8000		\
 	mx51evk			\
 	omap3_beagle		\
@@ -650,6 +654,7 @@ LIST_ARM_CORTEX_A8="		\
 	omap3_sdp3430		\
 	omap3_zoom1		\
 	omap3_zoom2		\
+	s5p_goni		\
 	smdkc100		\
 "
 
@@ -682,6 +687,7 @@ LIST_at91="			\
 	otc570			\
 	pm9261			\
 	pm9263			\
+	pm9g45			\
 	SBC35_A9G20		\
 	TNY_A9260		\
 	TNY_A9G20		\
diff --git a/Makefile b/Makefile
index 9f7883a..3e11f6f 100644
--- a/Makefile
+++ b/Makefile
@@ -1999,6 +1999,10 @@ at91sam9g45ekes_config	:	unconfig
 	fi;
 	@$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
 
+pm9g45_config	:	unconfig
+	@mkdir -p $(obj)include
+	@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
+
 SBC35_A9G20_NANDFLASH_config \
 SBC35_A9G20_EEPROM_config \
 SBC35_A9G20_config	:	unconfig
@@ -2042,18 +2046,6 @@ cp922_XA10_config	\
 cp1026_config: unconfig
 	@board/armltd/integrator/split_by_variant.sh cp $@
 
-da830evm_config			\
-davinci_dvevm_config		\
-davinci_schmoogie_config	\
-davinci_sffsdr_config		\
-davinci_sonata_config		\
-davinci_dm355evm_config		\
-davinci_dm355leopard_config	\
-davinci_dm365evm_config		\
-davinci_dm6467evm_config	:	unconfig
-	@$(MKCONFIG) -n $@ $@ arm arm926ejs \
-		$(subst davinci_,,$(@:_config=)) davinci davinci
-
 nhk8815_config \
 nhk8815_onenand_config:	unconfig
 	@mkdir -p $(obj)include
@@ -2221,7 +2213,8 @@ smdk6400_config	:	unconfig
 	else										\
 		echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
 	fi
-	@$(MKCONFIG) $(subst _noUSB,,$(@:_config=)) arm arm1176 smdk6400 samsung s3c64xx
+	@$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
 #========================================================================
 # MIPS
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index ade7f46..2b91631 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -71,6 +71,7 @@ static void cache_flush(void)
 {
 	unsigned long i = 0;
 
+	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
 	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
 	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
 }
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 957f438..922d01c 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -226,8 +226,8 @@ cpu_init_crit:
 	 * flush v4 I/D caches
 	 */
 	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
 
 	/*
 	 * disable MMU stuff and caches
diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c
index befa0cd..c0fd114 100644
--- a/arch/arm/cpu/arm1176/cpu.c
+++ b/arch/arm/cpu/arm1176/cpu.c
@@ -33,9 +33,6 @@
 
 #include <common.h>
 #include <command.h>
-#ifdef CONFIG_S3C64XX
-#include <asm/arch/s3c6400.h>
-#endif
 #include <asm/system.h>
 
 static void cache_flush (void);
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index e2b6c9b..a540edb 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -1,5 +1,5 @@
 /*
- *  armboot - Startup Code for S3C6400/ARM1176 CPU-core
+ *  armboot - Startup Code for ARM1176 CPU-core
  *
  * Copyright (c) 2007	Samsung Electronics
  *
@@ -35,9 +35,6 @@
 #ifdef CONFIG_ENABLE_MMU
 #include <asm/proc/domain.h>
 #endif
-#ifdef CONFIG_S3C64XX
-#include <asm/arch/s3c6400.h>
-#endif
 
 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
 #define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
@@ -172,14 +169,10 @@ cpu_init_crit:
 	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+
 	/* Prepare to disable the MMU */
-	adr	r1, mmu_disable_phys
-	/* We presume we're within the first 1024 bytes */
-	and	r1, r1, #0x3fc
-	ldr	r2, _TEXT_PHY_BASE
-	ldr	r3, =0xfff00000
-	and	r2, r2, r3
-	orr	r2, r2, r1
+	adr	r2, mmu_disable_phys
+	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE)
 	b	mmu_disable
 
 	.align 5
@@ -189,14 +182,30 @@ mmu_disable:
 	nop
 	nop
 	mov	pc, r2
+mmu_disable_phys:
+
+#ifdef CONFIG_DISABLE_TCM
+	/*
+	 * Disable the TCMs
+	 */
+	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
+	cmp	r0, #0
+	beq	skip_tcmdisable
+	mov	r1, #0
+	mov	r2, #1
+	tst	r0, r2
+	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
+	tst	r0, r2, LSL #16
+	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
+skip_tcmdisable:
+#endif
 #endif
 
-mmu_disable_phys:
-#ifdef CONFIG_S3C64XX
+#ifdef CONFIG_PERIPORT_REMAP
 	/* Peri port setup */
-	ldr	r0, =0x70000000
-	orr	r0, r0, #0x13
-	mcr	p15,0,r0,c15,c2,4       @ 256M (0x70000000 - 0x7fffffff)
+	ldr	r0, =CONFIG_PERIPORT_BASE
+	orr	r0, r0, #CONFIG_PERIPORT_SIZE
+	mcr	p15,0,r0,c15,c2,4
 #endif
 
 	/*
@@ -204,7 +213,25 @@ mmu_disable_phys:
 	 */
 	bl	lowlevel_init		/* go setup pll,mux,memory */
 
-after_copy:
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+relocate:				/* relocate U-Boot to RAM	    */
+	adr	r0, _start		/* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
+	cmp     r0, r1                  /* don't reloc during debug         */
+	beq     stack_setup
+
+	ldr	r2, _armboot_start
+	ldr	r3, _bss_start
+	sub	r2, r3, r2		/* r2 <- size of armboot            */
+	add	r2, r0, r2		/* r2 <- source end address         */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */
+	ble	copy_loop
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
+
 #ifdef CONFIG_ENABLE_MMU
 enable_mmu:
 	/* enable domain access */
@@ -240,9 +267,9 @@ mmu_enable:
 	nop
 	nop
 	mov	pc, r2
+skip_hw_init:
 #endif
 
-skip_hw_init:
 	/* Set up the stack						    */
 stack_setup:
 	ldr	r0, =CONFIG_SYS_UBOOT_BASE	/* base of copy in DRAM	    */
@@ -310,6 +337,8 @@ phy_last_jump:
 	mov	r0, #0
 	mov	pc, r9
 #endif
+
+
 /*
  *************************************************************************
  *
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
new file mode 100644
index 0000000..fe9d8a0
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile
@@ -0,0 +1,44 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	+= aemif.o clock.o init.o mux.o timer.o wdt.o
+SOBJS	+= lowlevel_init.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
new file mode 100644
index 0000000..172f583
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
@@ -0,0 +1,93 @@
+/*
+ * TNETV107X: Asynchronous EMIF Configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define ASYNC_EMIF_BASE			TNETV107X_ASYNC_EMIF_CNTRL_BASE
+#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
+#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
+#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
+#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)
+
+#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
+#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
+#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
+#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)
+#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
+#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
+#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
+#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
+#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
+#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)
+
+#define NUM_CS				4
+
+#define set_config_field(reg, field, val)			\
+	do {							\
+		if (val != -1) {				\
+			reg &= ~CONFIG_##field(0xffffffff);	\
+			reg |=	CONFIG_##field(val);		\
+		}						\
+	} while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+	unsigned long tmp;
+
+	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+		tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
+
+	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+		tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
+	}
+
+	tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
+
+	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
+	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
+	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
+	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
+	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
+	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
+	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
+	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
+	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
+	set_config_field(tmp, WIDTH,		cfg->width);
+
+	__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+	int cs;
+
+	clk_enable(TNETV107X_LPSC_AEMIF);
+
+	for (cs = 0; cs < num_cs; cs++)
+		configure_async_emif(cs, config + cs);
+}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
new file mode 100644
index 0000000..e26fec1
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -0,0 +1,451 @@
+/*
+ * TNETV107X: Clock management APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+
+#define CLOCK_BASE		TNETV107X_CLOCK_CONTROL_BASE
+#define PSC_BASE		TNETV107X_PSC_BASE
+
+#define BIT(x)			(1 << (x))
+
+#define MAX_PREDIV		64
+#define MAX_POSTDIV		8
+#define MAX_MULT		512
+#define MAX_DIV			(MAX_PREDIV * MAX_POSTDIV)
+
+/* LPSC registers */
+#define PSC_PTCMD		0x120
+#define PSC_PTSTAT		0x128
+#define PSC_MDSTAT(n)		(0x800 + (n) * 4)
+#define PSC_MDCTL(n)		(0xA00 + (n) * 4)
+
+#define PSC_MDCTL_LRSTZ		BIT(8)
+
+#define psc_reg_read(reg)	__raw_readl((u32 *)(PSC_BASE + (reg)))
+#define psc_reg_write(reg, val)	__raw_writel(val, (u32 *)(PSC_BASE + (reg)))
+
+/* SSPLL registers */
+struct sspll_regs {
+	u32	modes;
+	u32	postdiv;
+	u32	prediv;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+/* SSPLL base addresses */
+static struct sspll_regs *sspll_regs[] = {
+	(struct sspll_regs *)(CLOCK_BASE + 0x040),
+	(struct sspll_regs *)(CLOCK_BASE + 0x080),
+	(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
+};
+
+#define sspll_reg(pll, reg)		(&(sspll_regs[pll]->reg))
+#define sspll_reg_read(pll, reg)	__raw_readl(sspll_reg(pll, reg))
+#define sspll_reg_write(pll, reg, val)	__raw_writel(val, sspll_reg(pll, reg))
+
+
+/* PLL Control Registers */
+struct pllctl_regs {
+	u32	ctl;		/* 00 */
+	u32	ocsel;		/* 04 */
+	u32	secctl;		/* 08 */
+	u32	__pad0;
+	u32	mult;		/* 10 */
+	u32	prediv;		/* 14 */
+	u32	div1;		/* 18 */
+	u32	div2;		/* 1c */
+	u32	div3;		/* 20 */
+	u32	oscdiv1;	/* 24 */
+	u32	postdiv;	/* 28 */
+	u32	bpdiv;		/* 2c */
+	u32	wakeup;		/* 30 */
+	u32	__pad1;
+	u32	cmd;		/* 38 */
+	u32	stat;		/* 3c */
+	u32	alnctl;		/* 40 */
+	u32	dchange;	/* 44 */
+	u32	cken;		/* 48 */
+	u32	ckstat;		/* 4c */
+	u32	systat;		/* 50 */
+	u32	ckctl;		/* 54 */
+	u32	__pad2[2];
+	u32	div4;		/* 60 */
+	u32	div5;		/* 64 */
+	u32	div6;		/* 68 */
+	u32	div7;		/* 6c */
+	u32	div8;		/* 70 */
+};
+
+struct lpsc_map {
+	int	pll, div;
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+	(struct pllctl_regs *)(CLOCK_BASE + 0x700),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x300),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x500),
+};
+
+#define pllctl_reg(pll, reg)		(&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg)	__raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val)	__raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val)			\
+	pllctl_reg_write(pll, reg,				\
+		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, mask, 0)
+
+/* PLLCTL Bits */
+#define PLLCTL_CLKMODE		BIT(8)
+#define PLLCTL_PLLSELB		BIT(7)
+#define PLLCTL_PLLENSRC		BIT(5)
+#define PLLCTL_PLLDIS		BIT(4)
+#define PLLCTL_PLLRST		BIT(3)
+#define PLLCTL_PLLPWRDN		BIT(1)
+#define PLLCTL_PLLEN		BIT(0)
+
+#define PLLDIV_ENABLE		BIT(15)
+
+static int pll_div_offset[] = {
+#define div_offset(reg)	offsetof(struct pllctl_regs, reg)
+	div_offset(div1), div_offset(div2), div_offset(div3),
+	div_offset(div4), div_offset(div5), div_offset(div6),
+	div_offset(div7), div_offset(div8),
+};
+
+static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
+static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
+
+/* Mappings from PLL+DIV to subsystem clocks */
+#define sys_arm1176_clk		{SYS_PLL, 0}
+#define sys_dsp_clk		{SYS_PLL, 1}
+#define sys_ddr_clk		{SYS_PLL, 2}
+#define sys_full_clk		{SYS_PLL, 3}
+#define sys_lcd_clk		{SYS_PLL, 4}
+#define sys_vlynq_ref_clk	{SYS_PLL, 5}
+#define sys_tsc_clk		{SYS_PLL, 6}
+#define sys_half_clk		{SYS_PLL, 7}
+
+#define eth_clk_5		{ETH_PLL, 0}
+#define eth_clk_50		{ETH_PLL, 1}
+#define eth_clk_125		{ETH_PLL, 2}
+#define eth_clk_250		{ETH_PLL, 3}
+#define eth_clk_25		{ETH_PLL, 4}
+
+#define tdm_clk			{TDM_PLL, 0}
+#define tdm_extra_clk		{TDM_PLL, 1}
+#define tdm1_clk		{TDM_PLL, 2}
+
+/* Optimization barrier */
+#define barrier()	\
+	__asm__ __volatile__("mov r0, r0\n" : : : "memory");
+
+static const struct lpsc_map lpsc_clk_map[] = {
+	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
+	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
+	[TNETV107X_LPSC_DDR2_PHY]		= sys_ddr_clk,
+	[TNETV107X_LPSC_TPCC]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC0]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC1]			= sys_full_clk,
+	[TNETV107X_LPSC_RAM]			= sys_full_clk,
+	[TNETV107X_LPSC_MBX_LITE]		= sys_arm1176_clk,
+	[TNETV107X_LPSC_LCD]			= sys_lcd_clk,
+	[TNETV107X_LPSC_ETHSS]			= eth_clk_125,
+	[TNETV107X_LPSC_AEMIF]			= sys_full_clk,
+	[TNETV107X_LPSC_CHIP_CFG]		= sys_half_clk,
+	[TNETV107X_LPSC_TSC]			= sys_tsc_clk,
+	[TNETV107X_LPSC_ROM]			= sys_half_clk,
+	[TNETV107X_LPSC_UART2]			= sys_half_clk,
+	[TNETV107X_LPSC_PKTSEC]			= sys_half_clk,
+	[TNETV107X_LPSC_SECCTL]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYMGR]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYPAD]			= sys_half_clk,
+	[TNETV107X_LPSC_GPIO]			= sys_half_clk,
+	[TNETV107X_LPSC_MDIO]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART1]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER0]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER1]			= sys_half_clk,
+	[TNETV107X_LPSC_WDT_ARM]		= sys_half_clk,
+	[TNETV107X_LPSC_WDT_DSP]		= sys_half_clk,
+	[TNETV107X_LPSC_SSP]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM0]			= tdm_clk,
+	[TNETV107X_LPSC_VLYNQ]			= sys_vlynq_ref_clk,
+	[TNETV107X_LPSC_MCDMA]			= sys_half_clk,
+	[TNETV107X_LPSC_USB0]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM1]			= tdm1_clk,
+	[TNETV107X_LPSC_DEBUGSS]		= sys_half_clk,
+	[TNETV107X_LPSC_ETHSS_RGMII]		= eth_clk_250,
+	[TNETV107X_LPSC_SYSTEM]			= sys_half_clk,
+	[TNETV107X_LPSC_IMCOP]			= sys_dsp_clk,
+	[TNETV107X_LPSC_SPARE]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO1]			= sys_half_clk,
+	[TNETV107X_LPSC_USB1]			= sys_half_clk,
+	[TNETV107X_LPSC_USBSS]			= sys_half_clk,
+	[TNETV107X_LPSC_DDR2_EMIF1_VRST]	= sys_ddr_clk,
+	[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]	= sys_ddr_clk,
+};
+
+static const unsigned long pll_ext_freq[] = {
+	[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
+	[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
+	[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
+};
+
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, postdiv = 1;
+	unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
+	unsigned long ret;
+	u32 bypass;
+
+	bypass = __raw_readl((u32 *)(CLOCK_BASE));
+	if (!(bypass & pll_bypass_mask[pll])) {
+		mult	= sspll_reg_read(pll, mult_factor);
+		prediv	= sspll_reg_read(pll, prediv) + 1;
+		postdiv	= sspll_reg_read(pll, postdiv) + 1;
+	}
+
+	if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
+		return ref;
+
+	ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
+					int div)
+{
+	int divider = 1;
+	unsigned long divreg;
+
+	divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
+
+	if (divreg & PLLDIV_ENABLE)
+		divider = (divreg & pll_div_mask[pll]) + 1;
+
+	return fpll / divider;
+}
+
+static unsigned long pll_div_freq_get(int pll, int div)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
+			       unsigned long hz)
+{
+	int divider = (fpll / hz - 1);
+
+	divider &= pll_div_mask[pll];
+	divider |= PLLDIV_ENABLE;
+
+	__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
+	pllctl_reg_setbits(pll, alnctl, (1 << div));
+	pllctl_reg_setbits(pll, dchange, (1 << div));
+}
+
+static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	__pll_div_freq_set(pll, fpll, div, hz);
+
+	pllctl_reg_write(pll, cmd, 1);
+
+	/* Wait until new divider takes effect */
+	while (pllctl_reg_read(pll, stat) & 0x01);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
+}
+
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
+{
+	unsigned long fpll, divider, pll;
+
+	pll = lpsc_clk_map[clk].pll;
+	fpll = pll_freq_get(pll);
+	divider = (fpll / hz - 1);
+	divider &= pll_div_mask[pll];
+
+	return fpll / (divider + 1);
+}
+
+int clk_set_rate(unsigned int clk, unsigned long _hz)
+{
+	unsigned long hz;
+
+	hz = clk_round_rate(clk, _hz);
+	if (hz != _hz)
+		return -EINVAL;	/* Cannot set to target freq */
+
+	pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
+	return 0;
+}
+
+void lpsc_control(int mod, unsigned long state, int lrstz)
+{
+	u32 mdctl;
+
+	mdctl = psc_reg_read(PSC_MDCTL(mod));
+	mdctl &= ~0x1f;
+	mdctl |= state;
+
+	if (lrstz == 0)
+		mdctl &= ~PSC_MDCTL_LRSTZ;
+	else if (lrstz == 1)
+		mdctl |= PSC_MDCTL_LRSTZ;
+
+	psc_reg_write(PSC_MDCTL(mod), mdctl);
+
+	psc_reg_write(PSC_PTCMD, 1);
+
+	/* wait for power domain transition to end */
+	while (psc_reg_read(PSC_PTSTAT) & 1);
+
+	/* Wait for module state change */
+	while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
+}
+
+int lpsc_status(unsigned int id)
+{
+	return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
+}
+
+static void init_pll(const struct pll_init_data *data)
+{
+	unsigned long fpll;
+	unsigned long best_pre = 0, best_post = 0, best_mult = 0;
+	unsigned long div, prediv, postdiv, mult;
+	unsigned long delta, actual;
+	long best_delta = -1;
+	int i;
+	u32 tmp;
+
+	if (data->pll == SYS_PLL)
+		return; /* cannot reconfigure system pll on the fly */
+
+	tmp = pllctl_reg_read(data->pll, ctl);
+	if (data->internal_osc) {
+		tmp &= ~PLLCTL_CLKMODE;
+		fpll = CONFIG_SYS_INT_OSC_FREQ;
+	} else {
+		tmp |= PLLCTL_CLKMODE;
+		fpll = pll_ext_freq[data->pll];
+	}
+	pllctl_reg_write(data->pll, ctl, tmp);
+
+	mult = data->pll_freq / fpll;
+	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
+		div = (fpll * mult) / data->pll_freq;
+		if (div < 1 || div > MAX_DIV)
+			continue;
+
+		for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
+			prediv = div / postdiv;
+			if (prediv < 1 || prediv > MAX_PREDIV)
+				continue;
+
+			actual = (fpll / prediv) * (mult / postdiv);
+			delta = (actual - data->pll_freq);
+			if (delta < 0)
+				delta = -delta;
+			if ((delta < best_delta) || (best_delta == -1)) {
+				best_delta = delta;
+				best_mult = mult;
+				best_pre = prediv;
+				best_post = postdiv;
+				if (delta == 0)
+					goto done;
+			}
+		}
+	}
+done:
+
+	if (best_delta == -1) {
+		printf("pll cannot derive %lu from %lu\n",
+				data->pll_freq, fpll);
+		return;
+	}
+
+	fpll = fpll * best_mult;
+	fpll /= best_pre * best_post;
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
+
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
+
+	sspll_reg_write(data->pll, mult_factor,	(best_mult - 1) << 8);
+	sspll_reg_write(data->pll, prediv,	best_pre - 1);
+	sspll_reg_write(data->pll, postdiv,	best_post - 1);
+
+	for (i = 0; i < 10; i++)
+		if (data->div_freq[i])
+			__pll_div_freq_set(data->pll, fpll, i,
+					   data->div_freq[i]);
+
+	pllctl_reg_write(data->pll, cmd, 1);
+
+	/* Wait until pll "go" operation completes */
+	while (pllctl_reg_read(data->pll, stat) & 0x01);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+	int i;
+
+	for (i = 0; i < num_pll; i++)
+		init_pll(&config[i]);
+}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c
new file mode 100644
index 0000000..ce3a025
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/init.c
@@ -0,0 +1,37 @@
+/*
+ * TNETV107X: Architecture initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void chip_configuration_unlock(void)
+{
+       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
+       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+       chip_configuration_unlock();
+
+       return 0;
+}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
new file mode 100644
index 0000000..3ee32ef
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
@@ -0,0 +1,25 @@
+/*
+ * TNETV107X: Low-level pre-relocation initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* nothing for now, maybe needed for more exotic boot modes */
+	mov	pc, lr
diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c
new file mode 100644
index 0000000..ccc5314
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/mux.c
@@ -0,0 +1,334 @@
+/*
+ * TNETV107X: Pinmux configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define MUX_MODE_1		0x00
+#define MUX_MODE_2		0x04
+#define MUX_MODE_3		0x0c
+#define MUX_MODE_4		0x1c
+
+#define MUX_DEBUG		0
+
+static const struct pin_config pin_table[] = {
+	/*		  reg	shift	mode	*/
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(11,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(11,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(19,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(20,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(26,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_2),
+};
+
+const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
+
+int mux_select_pin(short index)
+{
+	const struct pin_config *cfg;
+	unsigned long mask, mode, reg;
+
+	if (index >= pin_table_size)
+		return 0;
+
+	cfg = &pin_table[index];
+
+	mask = 0x1f << cfg->mask_offset;
+	mode = cfg->mode << cfg->mask_offset;
+
+	reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
+	reg = (reg & ~mask) | mode;
+	__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
+
+	return 1;
+}
+
+int mux_select_pins(const short *pins)
+{
+	int i, ret = 1;
+
+	for (i = 0; pins[i] >= 0; i++)
+		ret &= mux_select_pin(pins[i]);
+
+	return ret;
+}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c
new file mode 100644
index 0000000..a7a400d
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/timer.c
@@ -0,0 +1,122 @@
+/*
+ * TNETV107X: Timer implementation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+struct timer_regs {
+	u_int32_t pid12;
+	u_int32_t pad[3];
+	u_int32_t tim12;
+	u_int32_t tim34;
+	u_int32_t prd12;
+	u_int32_t prd34;
+	u_int32_t tcr;
+	u_int32_t tgcr;
+	u_int32_t wdtcr;
+};
+
+#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
+
+#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define TIM_CLK_DIV	16
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init(void)
+{
+	clk_enable(TNETV107X_LPSC_TIMER0);
+
+	lastinc = timestamp = 0;
+
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	__raw_writel(0x0, &regs->tcr);
+	__raw_writel(0x0, &regs->tgcr);
+	__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
+	__raw_writel(0x0, &regs->tim34);
+	__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
+	__raw_writel(2 << 22, &regs->tcr);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	lastinc = timestamp = 0;
+
+	__raw_writel(0,		&regs->tcr);
+	__raw_writel(0,		&regs->tim34);
+	__raw_writel(2 << 22,	&regs->tcr);
+}
+
+static ulong get_timer_raw(void)
+{
+	ulong now = __raw_readl(&regs->tim34);
+
+	if (now >= lastinc)
+		timestamp += now - lastinc;
+	else
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
+
+	lastinc = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= (1000 * TIM_CLK_DIV);
+
+	endtime = get_timer_raw() + tmo;
+
+	do {
+		ulong now = get_timer_raw();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/wdt.c b/arch/arm/cpu/arm1176/tnetv107x/wdt.c
new file mode 100644
index 0000000..18aadb0
--- /dev/null
+++ b/arch/arm/cpu/arm1176/tnetv107x/wdt.c
@@ -0,0 +1,180 @@
+/*
+ * TNETV107X: Watchdog timer implementation (for reset)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#define MAX_DIV		0xFFFE0001
+
+struct wdt_regs {
+	u32 kick_lock;
+#define KICK_LOCK_1	0x5555
+#define KICK_LOCK_2	0xaaaa
+	u32 kick;
+
+	u32 change_lock;
+#define CHANGE_LOCK_1	0x6666
+#define CHANGE_LOCK_2	0xbbbb
+	u32 change;
+
+	u32 disable_lock;
+#define DISABLE_LOCK_1	0x7777
+#define DISABLE_LOCK_2	0xcccc
+#define DISABLE_LOCK_3	0xdddd
+	u32 disable;
+
+	u32 prescale_lock;
+#define PRESCALE_LOCK_1	0x5a5a
+#define PRESCALE_LOCK_2	0xa5a5
+	u32 prescale;
+};
+
+static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
+
+#define wdt_reg_read(reg)	__raw_readl(&regs->reg)
+#define wdt_reg_write(reg, val)	__raw_writel((val), &regs->reg)
+
+static int write_prescale_reg(unsigned long prescale_value)
+{
+	wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
+	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
+	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(prescale, prescale_value);
+
+	return 0;
+}
+
+static int write_change_reg(unsigned long initial_timer_value)
+{
+	wdt_reg_write(change_lock, CHANGE_LOCK_1);
+	if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(change_lock, CHANGE_LOCK_2);
+	if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(change, initial_timer_value);
+
+	return 0;
+}
+
+static int wdt_control(unsigned long disable_value)
+{
+	wdt_reg_write(disable_lock, DISABLE_LOCK_1);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(disable_lock, DISABLE_LOCK_2);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
+		return -1;
+
+	wdt_reg_write(disable_lock, DISABLE_LOCK_3);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(disable, disable_value);
+	return 0;
+}
+
+static int wdt_set_period(unsigned long msec)
+{
+	unsigned long change_value, count_value;
+	unsigned long prescale_value = 1;
+	unsigned long refclk_khz, maxdiv;
+	int ret;
+
+	refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
+	maxdiv = (MAX_DIV / refclk_khz);
+
+	if ((!msec) || (msec > maxdiv))
+		return -1;
+
+	count_value = refclk_khz * msec;
+	if (count_value > 0xffff) {
+		change_value = count_value / 0xffff + 1;
+		prescale_value = count_value / change_value;
+	} else {
+		change_value = count_value;
+	}
+
+	ret = write_prescale_reg(prescale_value - 1);
+	if (ret)
+		return ret;
+
+	ret = write_change_reg(change_value);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+unsigned long last_wdt = -1;
+
+int wdt_start(unsigned long msecs)
+{
+	int ret;
+	ret = wdt_control(0);
+	if (ret)
+		return ret;
+	ret = wdt_set_period(msecs);
+	if (ret)
+		return ret;
+	ret = wdt_control(1);
+	if (ret)
+		return ret;
+	ret = wdt_kick();
+	last_wdt = msecs;
+	return ret;
+}
+
+int wdt_stop(void)
+{
+	last_wdt = -1;
+	return wdt_control(0);
+}
+
+int wdt_kick(void)
+{
+	wdt_reg_write(kick_lock, KICK_LOCK_1);
+	if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(kick_lock, KICK_LOCK_2);
+	if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(kick, 1);
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	clk_enable(TNETV107X_LPSC_WDT_ARM);
+	wdt_start(1);
+	wdt_kick();
+}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile
new file mode 100644
index 0000000..11f4141
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS-y	= cpu.o
+COBJS-y	+= dram.o
+COBJS-y	+= timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
new file mode 100644
index 0000000..c2f5253
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/arch/orion5x.h>
+#include <hush.h>
+
+#define BUFLEN	16
+
+void reset_cpu(unsigned long ignored)
+{
+	struct orion5x_cpu_registers *cpureg =
+	    (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
+
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+		&cpureg->rstoutn_mask);
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+		&cpureg->sys_soft_rst);
+	while (1)
+		;
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val > 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return 0x0000ffff & j;
+}
+
+/*
+ * orion5x_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Orion5x Soc to addess different
+ * devices. Each window can be configured for size, BAR and remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int orion5x_config_adr_windows(void)
+{
+	struct orion5x_win_registers *winregs =
+		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
+
+	/* Window 0: PCIE MEM address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
+		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
+		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+	writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
+	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+
+	/* Window 1: PCIE IO address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
+		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
+		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+	writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
+	writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+	writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+
+	/* Window 2: PCI MEM address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
+		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
+		ORION5X_WIN_ENABLE), &winregs[2].ctrl);
+	writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
+
+	/* Window 3: PCI IO address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
+		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
+		ORION5X_WIN_ENABLE), &winregs[3].ctrl);
+	writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
+
+	/* Window 4: DEV_CS0 address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
+		ORION5X_WIN_ENABLE), &winregs[4].ctrl);
+	writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
+
+	/* Window 5: DEV_CS1 address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
+		ORION5X_WIN_ENABLE), &winregs[5].ctrl);
+	writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
+
+	/* Window 6: DEV_CS2 address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
+		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
+	writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
+
+	/* Window 7: BOOT Memory address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
+		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
+		ORION5X_WIN_ENABLE), &winregs[7].ctrl);
+	writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
+
+	return 0;
+}
+
+/*
+ * Orion5x identification is done through PCIE space.
+ */
+
+u32 orion5x_device_id(void)
+{
+	return readl(PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 orion5x_device_rev(void)
+{
+	return readl(PCIE_DEV_REV_OFF) & 0xff;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+
+/* Display device and revision IDs.
+ * This function must cover all known device/revision
+ * combinations, not only the one for which u-boot is
+ * compiled; this way, one can identify actual HW in
+ * case of a mismatch.
+ */
+int print_cpuinfo(void)
+{
+	char dev_str[] = "0x0000";
+	char rev_str[] = "0x00";
+	char *dev_name = NULL;
+	char *rev_name = NULL;
+
+	u32 dev = orion5x_device_id();
+	u32 rev = orion5x_device_rev();
+
+	if (dev == MV88F5181_DEV_ID) {
+		dev_name = "MV88F5181";
+		if (rev == MV88F5181_REV_B1)
+			rev_name = "B1";
+		else if (rev == MV88F5181L_REV_A1) {
+			dev_name = "MV88F5181L";
+			rev_name = "A1";
+		} else if (rev == MV88F5181L_REV_A0) {
+			dev_name = "MV88F5181L";
+			rev_name = "A0";
+		}
+	} else if (dev == MV88F5182_DEV_ID) {
+		dev_name = "MV88F5182";
+		if (rev == MV88F5182_REV_A2)
+			rev_name = "A2";
+	} else if (dev == MV88F5281_DEV_ID) {
+		dev_name = "MV88F5281";
+		if (rev == MV88F5281_REV_D2)
+			rev_name = "D2";
+		else if (rev == MV88F5281_REV_D1)
+			rev_name = "D1";
+		else if (rev == MV88F5281_REV_D0)
+			rev_name = "D0";
+	} else if (dev == MV88F6183_DEV_ID) {
+		dev_name = "MV88F6183";
+		if (rev == MV88F6183_REV_B0)
+			rev_name = "B0";
+	}
+	if (dev_name == NULL) {
+		sprintf(dev_str, "0x%04x", dev);
+		dev_name = dev_str;
+	}
+	if (rev_name == NULL) {
+		sprintf(rev_str, "0x%02x", rev);
+		rev_name = rev_str;
+	}
+
+	printf("SoC:   Orion5x %s-%s\n", dev_name, rev_name);
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	/* Enable and invalidate L2 cache in write through mode */
+	invalidate_l2_cache();
+
+	orion5x_config_adr_windows();
+
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	u32 temp;
+
+	/*CPU streaming & write allocate */
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 28);	/* disable wr alloc */
+	writefr_extra_feature_reg(temp);
+
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 29);	/* streaming disabled */
+	writefr_extra_feature_reg(temp);
+
+	/* L2Cache settings */
+	temp = readfr_extra_feature_reg();
+	/* Disable L2C pre fetch - Set bit 24 */
+	temp |= (1 << 24);
+	/* enable L2C - Set bit 22 */
+	temp |= (1 << 22);
+	writefr_extra_feature_reg(temp);
+
+	icache_enable();
+	/* Change reset vector to address 0x0 */
+	temp = get_cr();
+	set_cr(temp & ~CR_V);
+
+	/* Set CPIOs and MPPs - values provided by board
+	   include file */
+	writel(ORION5X_MPP_BASE+0x00, ORION5X_MPP0_7);
+	writel(ORION5X_MPP_BASE+0x04, ORION5X_MPP8_15);
+	writel(ORION5X_MPP_BASE+0x50, ORION5X_MPP16_23);
+	writel(ORION5X_GPIO_BASE+0x04, ORION5X_GPIO_OUT_ENABLE);
+
+	return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
new file mode 100644
index 0000000..c719798
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/orion5x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * orion5x_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 orion5x_sdram_bar(enum memory_bank bank)
+{
+	struct orion5x_ddr_addr_decode_registers *winregs =
+		(struct orion5x_ddr_addr_decode_registers *)
+		ORION5X_CPU_WIN_BASE;
+
+	u32 result = 0;
+	u32 enable = 0x01 & winregs[bank].size;
+
+	if ((!enable) || (bank > BANK3))
+		return 0;
+
+	result = winregs[bank].base;
+	return result;
+}
+
+int dram_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
+		gd->bd->bi_dram[i].size = get_ram_size(
+			(volatile long *) (gd->bd->bi_dram[i].start),
+			CONFIG_MAX_RAM_BANK_SIZE);
+	}
+	return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
new file mode 100644
index 0000000..b0e15f6
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
@@ -0,0 +1,293 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include "asm/arch/orion5x.h"
+
+/*
+ * Configuration values for SDRAM access setup
+ */
+
+#define SDRAM_CONFIG			0x3148400
+#define SDRAM_MODE			0x62
+#define SDRAM_CONTROL			0x4041000
+#define SDRAM_TIME_CTRL_LOW		0x11602220
+#define SDRAM_TIME_CTRL_HI		0x40c
+#define SDRAM_OPEN_PAGE_EN		0x0
+/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
+#define SDRAM_BANK0_SIZE		0x3ff0001
+#define SDRAM_ADDR_CTRL			0x10
+
+#define SDRAM_OP_NOP			0x05
+#define SDRAM_OP_SETMODE		0x03
+
+#define SDRAM_PAD_CTRL_WR_EN		0x80000000
+#define SDRAM_PAD_CTRL_TUNE_EN		0x00010000
+#define SDRAM_PAD_CTRL_DRVN_MASK	0x0000003f
+#define SDRAM_PAD_CTRL_DRVP_MASK	0x00000fc0
+
+/*
+ * For Guideline MEM-3 - Drive Strength value
+ */
+
+#define DDR1_PAD_STRENGTH_DEFAULT	0x00001000
+#define SDRAM_PAD_CTRL_DRV_STR_MASK	0x00003000
+
+/*
+ * For Guideline MEM-4 - DQS Reference Delay Tuning
+ */
+
+#define MSAR_ARMDDRCLCK_MASK		0x000000f0
+#define MSAR_ARMDDRCLCK_H_MASK		0x00000100
+
+#define MSAR_ARMDDRCLCK_333_167		0x00000000
+#define MSAR_ARMDDRCLCK_500_167		0x00000030
+#define MSAR_ARMDDRCLCK_667_167		0x00000060
+#define MSAR_ARMDDRCLCK_400_200_1	0x000001E0
+#define MSAR_ARMDDRCLCK_400_200		0x00000010
+#define MSAR_ARMDDRCLCK_600_200		0x00000050
+#define MSAR_ARMDDRCLCK_800_200		0x00000070
+
+#define FTDLL_DDR1_166MHZ		0x0047F001
+
+#define FTDLL_DDR1_200MHZ		0x0044D001
+
+/*
+ * Low-level init happens right after start.S has switched to SVC32,
+ * flushed and disabled caches and disabled MMU. We're still running
+ * from the boot chip select, so the first thing we should do is set
+ * up RAM for us to relocate into.
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+	/* Use 'r4 as the base for internal register accesses */
+	ldr     r4, =ORION5X_REGS_PHY_BASE
+
+	/* move internal registers from the default 0xD0000000
+	 * to their intended location, defined by SoC */
+	ldr	r3, =0xD0000000
+	add	r3, r3, #0x20000
+        str	r4, [r3, #0x80]
+
+	/* Use R3 as the base for DRAM registers */
+	add     r3, r4, #0x01000
+
+	/*DDR SDRAM Initialization Control */
+	ldr	r6, =0x00000001
+	str	r6, [r3, #0x480]
+
+	/* Use R3 as the base for PCI registers */
+	add     r3, r4, #0x31000
+
+	/* Disable arbiter */
+	ldr	r6, =0x00000030
+	str	r6, [r3, #0xd00]
+
+	/* Use R3 as the base for DRAM registers */
+	add     r3, r4, #0x01000
+
+	/* set all dram windows to 0 */
+	mov	r6, #0
+	str	r6, [r3, #0x504]
+	str	r6, [r3, #0x50C]
+	str	r6, [r3, #0x514]
+	str	r6, [r3, #0x51C]
+
+	/* 1) Configure SDRAM  */
+	ldr	r6, =SDRAM_CONFIG
+	str	r6, [r3, #0x400]
+
+	/* 2) Set SDRAM Control reg */
+	ldr	r6, =SDRAM_CONTROL
+	str	r6, [r3, #0x404]
+
+        /* 3) Write SDRAM address control register */
+	ldr	r6, =SDRAM_ADDR_CTRL
+	str	r6, [r3, #0x410]
+
+        /* 4) Write SDRAM bank 0 size register */
+	ldr	r6, =SDRAM_BANK0_SIZE
+	str	r6, [r3, #0x504]
+	/* keep other banks disabled */
+
+        /* 5) Write SDRAM open pages control register */
+	ldr	r6, =SDRAM_OPEN_PAGE_EN
+	str	r6, [r3, #0x414]
+
+        /* 6) Write SDRAM timing Low register */
+	ldr	r6, =SDRAM_TIME_CTRL_LOW
+	str	r6, [r3, #0x408]
+
+        /* 7) Write SDRAM timing High register */
+	ldr	r6, =SDRAM_TIME_CTRL_HI
+	str	r6, [r3, #0x40C]
+
+        /* 8) Write SDRAM mode register */
+        /* The CPU must not attempt to change the SDRAM Mode register setting */
+        /* prior to DRAM controller completion of the DRAM initialization     */
+        /* sequence. To guarantee this restriction, it is recommended that    */
+        /* the CPU sets the SDRAM Operation register to NOP command, performs */
+        /* read polling until the register is back in Normal operation value, */
+        /* and then sets SDRAM Mode register to its new value.                */
+
+	/* 8.1 write 'nop' to SDRAM operation */
+        ldr	r6, =SDRAM_OP_NOP
+	str	r6, [r3, #0x418]
+
+        /* 8.2 poll SDRAM operation until back in 'normal' mode.  */
+1:
+	ldr	r6, [r3, #0x418]
+	cmp	r6, #0
+	bne	1b
+
+        /* 8.3 Now its safe to write new value to SDRAM Mode register         */
+	ldr	r6, =SDRAM_MODE
+	str	r6, [r3, #0x41C]
+
+        /* 8.4 Set new mode */
+        ldr	r6, =SDRAM_OP_SETMODE
+	str	r6, [r3, #0x418]
+
+        /* 8.5 poll SDRAM operation until back in 'normal' mode.  */
+2:
+	ldr	r6, [r3, #0x418]
+	cmp	r6, #0
+	bne	2b
+
+        /* DDR SDRAM Address/Control Pads Calibration */
+	ldr	r6, [r3, #0x4C0]
+
+        /* Set Bit [31] to make the register writable                   */
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C0]
+
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength [22:17]     */
+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26    /* r1[5:0]<DrvN>  = r3[22:17]<LockN>   */
+        orr   r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN>      */
+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]       */
+	orr	r6, r6, r1
+	str	r6, [r3, #0x4C0]
+
+        /* DDR SDRAM Data Pads Calibration                         	*/
+	ldr	r6, [r3, #0x4C4]
+
+        /* Set Bit [31] to make the register writable                   */
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C4]
+
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+        /* Get the final N locked value of driving strength [22:17]     */
+        mov   r1, r6
+        mov   r1, r1, LSL #9
+        mov   r1, r1, LSR #26
+        orr   r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>  */
+
+        /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]       */
+	orr	r6, r6, r1
+
+	str	r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-3) Drive Strength Value         */
+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0             */
+
+        ldr     r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
+	ldr	r6, [r3, #0x4C0]
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C0]
+
+	/* Correct strength and disable writes again */
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+	orr	r6, r6, r1
+	str	r6, [r3, #0x4C0]
+
+	/* Enable writes to DDR SDRAM Data Pads Calibration register */
+	ldr	r6, [r3, #0x4C4]
+	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	str	r6, [r3, #0x4C4]
+
+	/* Correct strength and disable writes again */
+	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
+	orr	r6, r6, r1
+	str	r6, [r3, #0x4C4]
+
+        /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning   */
+        /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0             */
+
+        /* Get the "sample on reset" register for the DDR frequancy     */
+	ldr	r3, =0x10000
+        ldr	r6, [r3, #0x010]
+        ldr	r1, =MSAR_ARMDDRCLCK_MASK
+        and	r1, r6, r1
+
+        ldr	r6, =FTDLL_DDR1_166MHZ
+        cmp	r1, #MSAR_ARMDDRCLCK_333_167
+        beq	3f
+        cmp	r1, #MSAR_ARMDDRCLCK_500_167
+        beq	3f
+        cmp	r1, #MSAR_ARMDDRCLCK_667_167
+        beq	3f
+
+        ldr	r6, =FTDLL_DDR1_200MHZ
+        cmp	r1, #MSAR_ARMDDRCLCK_400_200_1
+        beq	3f
+        cmp	r1, #MSAR_ARMDDRCLCK_400_200
+        beq	3f
+        cmp	r1, #MSAR_ARMDDRCLCK_600_200
+        beq	3f
+        cmp	r1, #MSAR_ARMDDRCLCK_800_200
+        beq	3f
+
+        ldr	r6, =0
+
+3:
+	/* Use R3 as the base for DRAM registers */
+	add     r3, r4, #0x01000
+
+	ldr	r2, [r3, #0x484]
+	orr	r2, r2, r6
+	str	r2, [r3, #0x484]
+
+	/* Return to U-boot via saved link register */
+	mov pc, lr
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
new file mode 100644
index 0000000..115448f
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/orion5x/timer.c
@@ -0,0 +1,181 @@
+/*
+  * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/orion5x.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct orion5x_tmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct orion5x_tmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct orion5x_tmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct orion5x_tmr_registers *orion5x_tmr_regs =
+	(struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			(&orion5x_tmr_regs->ctrl)
+#define CNTMR_RELOAD_REG(tmrnum)	(&orion5x_tmr_regs->tmr[tmrnum].reload)
+#define CNTMR_VAL_REG(tmrnum)		(&orion5x_tmr_regs->tmr[tmrnum].val)
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL 			0xffffffff
+
+static inline ulong read_timer(void)
+{
+	return readl(CNTMR_VAL_REG(UBOOT_CNTR))
+	      / (CONFIG_SYS_TCLK / 1000);
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = read_timer();
+	timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+static inline ulong uboot_cntr_val(void)
+{
+	return readl(CNTMR_VAL_REG(UBOOT_CNTR));
+}
+
+void __udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = uboot_cntr_val();
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		while (uboot_cntr_val() < current)
+			;
+		while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
+			;
+	} else {
+		while (uboot_cntr_val() > (current - delayticks))
+			;
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
index 136b163..7d63c6b 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
@@ -37,8 +37,11 @@ COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o
 
+COBJS-$(CONFIG_EMIF4)	+= emif4.o
+COBJS-$(CONFIG_SDRC)	+= sdrc.o
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
 
 all:	 $(obj).depend $(LIB)
 
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/arm_cortexa8/omap3/board.c
index 7b78fa4..d2500ca 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/board.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/board.c
@@ -40,8 +40,6 @@
 
 extern omap3_sysinfo sysinfo;
 
-extern u32 is_mem_sdr(void);
-
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
@@ -233,7 +231,7 @@ void s_init(void)
 	per_clocks_enable();
 
 	if (!in_sdram)
-		sdrc_init();
+		mem_init();
 }
 
 /******************************************************************************
@@ -274,36 +272,6 @@ void watchdog_init(void)
 }
 
 /******************************************************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- *****************************************************************************/
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-	}
-
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/******************************************************************************
  * Dummy function to handle errors for EABI incompatibility
  *****************************************************************************/
 void abort(void)
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c b/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
new file mode 100644
index 0000000..fae5b11
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
@@ -0,0 +1,168 @@
+/*
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on mem.c and sdrc.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/emif4.h>
+
+extern omap3_sysinfo sysinfo;
+
+static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	return 0;
+}
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size;
+
+	/* TODO: Calculate the size based on EMIF4 configuration */
+	size = CONFIG_SYS_CS0_SIZE;
+
+	return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset = 0;
+
+	return offset;
+}
+
+/*
+ * do_emif4_init -
+ *  - Init the emif4 module for DDR access
+ *  - Early init routines, called from flash or SRAM.
+ */
+void do_emif4_init(void)
+{
+	unsigned int regval;
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, &emif4_base->ddr_phyctrl1);
+	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
+	writel(0, &emif4_base->ddr_phyctrl2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(&emif4_base->sdram_iodft_tlgc);
+	regval |= (1<<10);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/*Wait till that bit clears*/
+	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
+	/*Re-verify the DDR PHY status*/
+	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
+
+	regval |= (1<<0);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, &emif4_base->sdram_time1);
+	writel(regval, &emif4_base->sdram_time1_shdw);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, &emif4_base->sdram_time2);
+	writel(regval, &emif4_base->sdram_time2_shdw);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, &emif4_base->sdram_time3);
+	writel(regval, &emif4_base->sdram_time3_shdw);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, &emif4_base->sdram_pwr_mgmt);
+	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, &emif4_base->sdram_refresh_ctrl);
+	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, &emif4_base->sdram_config);
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
+		size1 = get_sdr_cs_size(CS1);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/*
+ * mem_init() -
+ *  - Initialize memory subsystem
+ */
+void mem_init(void)
+{
+	do_emif4_init();
+}
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/arm_cortexa8/omap3/mem.c
index dfb7e4c..bd914b0 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/mem.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/mem.c
@@ -79,26 +79,6 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {
 
 #endif
 
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- *  command line mem=xyz use all memory with out discontinuous support
- *  compiled in.  Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(CS0);
-	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
-	a_add_high = (size & 3) << 8;	/* set up low field */
-	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
-	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
  *             for a part. Helps in guessing which part
@@ -123,76 +103,6 @@ u32 mem_ok(u32 cs)
 		return 1;
 }
 
-/********************************************************
- *  sdrc_init() - init the sdrc chip selects CS0 and CS1
- *  - early init routines, called from flash or
- *  SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-	/* only init up first bank here */
-	do_sdrc_init(CS0, EARLY_INIT);
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- *  -code sets up SDRAM basic SDRC timings for CS0
- *  -optimal settings can be placed here, or redone after i2c
- *      inspection of board info
- *
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *      time depending on memory configuration from stack+global context
- **************************************************************************/
-
-void do_sdrc_init(u32 cs, u32 early)
-{
-	struct sdrc_actim *sdrc_actim_base;
-
-	if(cs)
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-	else
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-	if (early) {
-		/* reset sdrc controller */
-		writel(SOFTRESET, &sdrc_base->sysconfig);
-		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
-			      12000000);
-		writel(0, &sdrc_base->sysconfig);
-
-		/* setup sdrc to ball mux */
-		writel(SDRC_SHARING, &sdrc_base->sharing);
-
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
-		writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
-				&sdrc_base->power);
-
-		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
-		sdelay(0x20000);
-	}
-
-	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
-		RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
-		DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
-	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
-	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
-	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
-	writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
-	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
-	/*
-	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
-	 * Burst length = 4
-	 */
-	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
-
-	if (!mem_ok(cs))
-		writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
 {
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
new file mode 100644
index 0000000..96fd990c
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
@@ -0,0 +1,202 @@
+/*
+ * Functions related to OMAP3 SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c, also created
+ * generic init function (mem_init).
+ *
+ * Copyright (C) 2004-2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Original implementation by (mem.c, board.c) :
+ *      Sunil Kumar <sunilsaini05@gmail.com>
+ *      Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *      Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+
+extern omap3_sysinfo sysinfo;
+
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
+		return 1;
+	return 0;
+}
+
+/*
+ * make_cs1_contiguous -
+ *  - For es2 and above remap cs1 behind cs0 to allow command line
+ *    mem=xyz use all memory with out discontinuous support compiled in.
+ *    Could do it at the ATAG, but there really is two banks...
+ *  - Called as part of 2nd phase DDR init.
+ */
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(CS0);
+	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
+	a_add_high = (size & 3) << 8;	/* set up low field */
+	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
+	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size;
+
+	/* get ram size field */
+	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+	size &= 0x3FF;		/* remove unwanted bits */
+	size <<= 21;		/* multiply by 2 MiB to find size in MB */
+	return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset;
+
+	if (!cs)
+		return 0;
+
+	offset = readl(&sdrc_base->cs_cfg);
+	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+	return offset;
+}
+
+/*
+ * do_sdrc_init -
+ *  - Initialize the SDRAM for use.
+ *  - Sets up SDRC timings for CS0
+ *  - code called once in C-Stack only context for CS0 and a possible 2nd
+ *    time depending on memory configuration from stack+global context
+ */
+void do_sdrc_init(u32 cs, u32 early)
+{
+	struct sdrc_actim *sdrc_actim_base;
+
+	if (cs)
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+	else
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+	if (early) {
+		/* reset sdrc controller */
+		writel(SOFTRESET, &sdrc_base->sysconfig);
+		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+				12000000);
+		writel(0, &sdrc_base->sysconfig);
+
+		/* setup sdrc to ball mux */
+		writel(SDRC_SHARING, &sdrc_base->sharing);
+
+		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
+		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
+				&sdrc_base->power);
+
+		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
+		sdelay(0x20000);
+	}
+
+	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
+			RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
+			DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
+	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
+	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
+	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
+
+	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+	/*
+	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
+	 * Burst length = 4
+	 */
+	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+
+	if (!mem_ok(cs))
+		writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+		do_sdrc_init(CS1, NOT_EARLY);
+		make_cs1_contiguous();
+
+		size1 = get_sdr_cs_size(CS1);
+	}
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/*
+ * mem_init -
+ *  - Init the sdrc chip,
+ *  - Selects CS0 and CS1,
+ */
+void mem_init(void)
+{
+	/* only init up first bank here */
+	do_sdrc_init(CS0, EARLY_INIT);
+}
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
index 08fb32e..1df4401 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
@@ -32,7 +32,6 @@
 #include <i2c.h>
 
 extern omap3_sysinfo sysinfo;
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
@@ -104,46 +103,6 @@ u32 get_cpu_rev(void)
 	}
 }
 
-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
-	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
-		return 1;
-	return 0;
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 cs)
-{
-	u32 size;
-
-	/* get ram size field */
-	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
-	size &= 0x3FF;		/* remove unwanted bits */
-	size <<= 21;		/* multiply by 2 MiB to find size in MB */
-	return size;
-}
-
-/***********************************************************************
- * get_sdr_cs_offset() - get offset of cs from cs0 start
- ************************************************************************/
-u32 get_sdr_cs_offset(u32 cs)
-{
-	u32 offset;
-
-	if (!cs)
-		return 0;
-
-	offset = readl(&sdrc_base->cs_cfg);
-	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
-
-	return offset;
-}
-
 /***************************************************************************
  *  get_gpmc0_base() - Return current address hardware will be
  *     fetching from. The below effectively gives what is correct, its a bit
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 63ab0c5..3989fa6 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -140,7 +140,10 @@ stack_setup:
 #ifdef CONFIG_USE_IRQ
 	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif /* CONFIG_USE_IRQ */
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+	sub	r0, r0, #12		/* leave 3 words for abort-stack    */
+	bic	sp, r0, #7		/* NOTE: stack MUST be aligned to   */
+					/* 8 bytes in case we want to use   */
+					/* 64bit datatypes (eg. VSPRINTF64) */
 
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment	    */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 81cc8ab..3520cf8 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -398,6 +398,7 @@ struct davinci_syscfg_regs {
 #define DAVINCI_SYSCFG_SUSPSRC_EMAC		(1 << 5)
 #define DAVINCI_SYSCFG_SUSPSRC_I2C		(1 << 16)
 #define DAVINCI_SYSCFG_SUSPSRC_SPI0		(1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI1		(1 << 22)
 #define DAVINCI_SYSCFG_SUSPSRC_UART2		(1 << 20)
 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0		(1 << 27)
 
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index aa8de32..c072c27 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -215,6 +215,31 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
new file mode 100644
index 0000000..579da0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -0,0 +1,79 @@
+/*
+ * Auther:
+ *       Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+/*
+ * Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x8 << 12)
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x25 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0x7)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x50F)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+#endif /* endif _EMIF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 9439758..a78cf9f 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -270,4 +270,17 @@ enum {
 #define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE
 
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif	/* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34bd515..db7b42a 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -33,6 +33,7 @@ void per_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
@@ -46,8 +47,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h
new file mode 100644
index 0000000..22e2dd3
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirorion5x_ood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ORION5X_CPU_H
+#define _ORION5X_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
+
+#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
+		((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum orion5x_cpu_winen {
+	ORION5X_WIN_DISABLE,
+	ORION5X_WIN_ENABLE
+};
+
+enum orion5x_cpu_target {
+	ORION5X_TARGET_DRAM = 0,
+	ORION5X_TARGET_DEVICE = 1,
+	ORION5X_TARGET_PCI = 3,
+	ORION5X_TARGET_PCIE = 4,
+	ORION5X_TARGET_SASRAM = 9
+};
+
+enum orion5x_cpu_attrib {
+	ORION5X_ATTR_DRAM_CS0 = 0x0e,
+	ORION5X_ATTR_DRAM_CS1 = 0x0d,
+	ORION5X_ATTR_DRAM_CS2 = 0x0b,
+	ORION5X_ATTR_DRAM_CS3 = 0x07,
+	ORION5X_ATTR_PCI_MEM = 0x59,
+	ORION5X_ATTR_PCI_IO = 0x51,
+	ORION5X_ATTR_PCIE_MEM = 0x59,
+	ORION5X_ATTR_PCIE_IO = 0x51,
+	ORION5X_ATTR_SASRAM = 0x00,
+	ORION5X_ATTR_DEV_CS0 = 0x1e,
+	ORION5X_ATTR_DEV_CS1 = 0x1d,
+	ORION5X_ATTR_DEV_CS2 = 0x1b,
+	ORION5X_ATTR_BOOTROM = 0x0f
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define ORION5X_DEFADR_PCIE_MEM	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCIE_IO	0xf0000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_IO	(64*1024)
+
+#define ORION5X_DEFADR_PCI_MEM	0x98000000
+#define ORION5X_DEFSZ_PCI_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCI_IO	0xf0100000
+#define ORION5X_DEFSZ_PCI_IO	(64*1024)
+
+#define ORION5X_DEFADR_DEV_CS0	0xfa000000
+#define ORION5X_DEFSZ_DEV_CS0	(2*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS1	0xf8000000
+#define ORION5X_DEFSZ_DEV_CS1	(32*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS2	0xfa800000
+#define ORION5X_DEFSZ_DEV_CS2	(1*1024*1024)
+
+#define ORION5X_DEFADR_BOOTROM	0xFFF80000
+#define ORION5X_DEFSZ_BOOTROM	(512*1024)
+
+/*
+ * PCIE registers are used for SoC device ID and revision
+ */
+#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
+#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
+
+/*
+ * The following definitions are intended for identifying
+ * the real device and revision on which u-boot is running
+ * even if it was compiled only for a specific one. Thus,
+ * these constants must not be considered chip-specific.
+ */
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D0        4
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID        0x6183
+#define MV88F6183_REV_B0        3
+
+/*
+ * read feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r"
+			(val) : : "cc");
+	return val;
+}
+
+/*
+ * write feroceon core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r"
+			(val) : "cc");
+	isb();
+}
+
+/*
+ * AHB to Mbus Bridge Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ * Note: only windows 0 and 1 have remap capability.
+ */
+struct orion5x_win_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.4
+ */
+struct orion5x_cpu_registers {
+	u32 config;	/*0x20100 */
+	u32 ctrl_stat;	/*0x20104 */
+	u32 rstoutn_mask; /* 0x20108 */
+	u32 sys_soft_rst; /* 0x2010C */
+	u32 ahb_mbus_cause_irq; /* 0x20110 */
+	u32 ahb_mbus_mask_irq; /* 0x20114 */
+};
+
+/*
+ * DDR SDRAM Controller Address Decode Registers
+ * Source: 88F5182 User Manual, Appendix A, section A.5.1
+ */
+struct orion5x_ddr_addr_decode_registers {
+	u32 base;
+	u32 size;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+u32 orion5x_device_id(void);
+u32 orion5x_device_rev(void);
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+#endif /* __ASSEMBLY__ */
+#endif /* _ORION5X_CPU_H */
diff --git a/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/arch/arm/include/asm/arch-orion5x/mv88f5182.h
new file mode 100644
index 0000000..86ba08d
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/mv88f5182.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood 88F6182 support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88F5182 SOC.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_88F5182_H
+#define _CONFIG_88F5182_H
+
+/* SOC specific definitions */
+#define F88F5182_REGS_PHYS_BASE		0xf1000000
+#define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+#endif /* _CONFIG_88F5182_H */
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
new file mode 100644
index 0000000..4008c84
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Marvell's Orion SoC with Feroceon CPU core.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ORION5X_H
+#define _ASM_ARCH_ORION5X_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#if defined(CONFIG_FEROCEON)
+#include <asm/arch/cpu.h>
+
+/* SOC specific definations */
+#define ORION5X_REGISTER(x)			(ORION5X_REGS_PHY_BASE + x)
+
+/* Documented registers */
+#define ORION5X_TWSI_BASE			(ORION5X_REGISTER(0x11000))
+#define ORION5X_UART0_BASE			(ORION5X_REGISTER(0x12000))
+#define ORION5X_UART1_BASE			(ORION5X_REGISTER(0x12100))
+#define ORION5X_MPP_BASE			(ORION5X_REGISTER(0x10000))
+#define ORION5X_GPIO_BASE			(ORION5X_REGISTER(0x10100))
+#define ORION5X_CPU_WIN_BASE			(ORION5X_REGISTER(0x20000))
+#define ORION5X_CPU_REG_BASE			(ORION5X_REGISTER(0x20100))
+#define ORION5X_TIMER_BASE			(ORION5X_REGISTER(0x20300))
+#define ORION5X_REG_PCI_BASE			(ORION5X_REGISTER(0x30000))
+#define ORION5X_REG_PCIE_BASE			(ORION5X_REGISTER(0x40000))
+#define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
+#define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
+#define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
+
+#define CONFIG_MAX_RAM_BANK_SIZE		(64*1024*1024)
+
+/* include here SoC variants. 5181, 5281, 6183 should go here when
+   adding support for them, and this comment should then be updated. */
+#if defined(CONFIG_88F5182)
+#include <asm/arch/mv88f5182.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_FEROCEON */
+#endif /* _ASM_ARCH_ORION5X_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h
new file mode 100644
index 0000000..097f825
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/clock.h
@@ -0,0 +1,68 @@
+/*
+ * TNETV107X: Clock APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#define PSC_MDCTL_NEXT_SWRSTDISABLE	0x0
+#define PSC_MDCTL_NEXT_SYNCRST		0x1
+#define PSC_MDCTL_NEXT_DISABLE		0x2
+#define PSC_MDCTL_NEXT_ENABLE		0x3
+
+#define CONFIG_SYS_INT_OSC_FREQ		24000000
+
+#ifndef __ASSEMBLY__
+
+/* PLL identifiers */
+enum pll_type_e {
+	SYS_PLL,
+	TDM_PLL,
+	ETH_PLL
+};
+
+/* PLL configuration data */
+struct pll_init_data {
+	int pll;
+	int internal_osc;
+	unsigned long pll_freq;
+	unsigned long div_freq[10];
+};
+
+void init_plls(int num_pll, struct pll_init_data *config);
+int  lpsc_status(unsigned int mod);
+void lpsc_control(int mod, unsigned long state, int lrstz);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+static inline void clk_enable(unsigned int mod)
+{
+	lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1);
+}
+
+static inline void clk_disable(unsigned int mod)
+{
+	lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1);
+}
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
new file mode 100644
index 0000000..9969a01
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h
@@ -0,0 +1 @@
+#include <asm/arch-davinci/emif_defs.h>
diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h
new file mode 100644
index 0000000..94a94f9
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h
@@ -0,0 +1,173 @@
+/*
+ * TNETV107X: Hardware information
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sizes.h>
+
+#define ASYNC_EMIF_NUM_CS		4
+#define ASYNC_EMIF_MODE_NOR		0
+#define ASYNC_EMIF_MODE_NAND		1
+#define ASYNC_EMIF_MODE_ONENAND		2
+#define ASYNC_EMIF_PRESERVE		-1
+
+struct async_emif_config {
+	unsigned mode;
+	unsigned select_strobe;
+	unsigned extend_wait;
+	unsigned wr_setup;
+	unsigned wr_strobe;
+	unsigned wr_hold;
+	unsigned rd_setup;
+	unsigned rd_strobe;
+	unsigned rd_hold;
+	unsigned turn_around;
+	enum {
+		ASYNC_EMIF_8	= 0,
+		ASYNC_EMIF_16	= 1,
+		ASYNC_EMIF_32	= 2,
+	} width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+int wdt_start(unsigned long msecs);
+int wdt_stop(void);
+int wdt_kick(void);
+
+#endif
+
+/* Chip configuration unlock codes and registers */
+#define TNETV107X_KICK0		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x38)
+#define TNETV107X_KICK1		(TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c)
+#define TNETV107X_PINMUX(n)	(TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4)
+#define TNETV107X_KICK0_MAGIC	0x83e70b13
+#define TNETV107X_KICK1_MAGIC	0x95a4f1e0
+
+/* Module base addresses */
+#define TNETV107X_TPCC_BASE			0x01C00000
+#define TNETV107X_TPTC0_BASE			0x01C10000
+#define TNETV107X_TPTC1_BASE			0x01C10400
+#define TNETV107X_INTC_BASE			0x03000000
+#define TNETV107X_LCD_CONTROLLER_BASE		0x08030000
+#define TNETV107X_INTD_BASE			0x08038000
+#define TNETV107X_INTD_IPC_BASE			0x08038000
+#define TNETV107X_INTD_FAST_BASE		0x08039000
+#define TNETV107X_INTD_ASYNC_BASE		0x0803A000
+#define TNETV107X_INTD_SLOW_BASE		0x0803B000
+#define TNETV107X_PKA_BASE			0x08040000
+#define TNETV107X_RNG_BASE			0x08044000
+#define TNETV107X_TIMER0_BASE			0x08086500
+#define TNETV107X_TIMER1_BASE			0x08086600
+#define TNETV107X_WDT0_ARM_BASE			0x08086700
+#define TNETV107X_WDT1_DSP_BASE			0x08086800
+#define TNETV107X_CHIP_CONFIG_SYS_BASE		0x08087000
+#define TNETV107X_GPIO_BASE			0x08088000
+#define TNETV107X_UART1_BASE			0x08088400
+#define TNETV107X_TOUCHSCREEN_BASE		0x08088500
+#define TNETV107X_SDIO0_BASE			0x08088700
+#define TNETV107X_SDIO1_BASE			0x08088800
+#define TNETV107X_MDIO_BASE			0x08088900
+#define TNETV107X_KEYPAD_BASE			0x08088A00
+#define TNETV107X_SSP_BASE			0x08088C00
+#define TNETV107X_CLOCK_CONTROL_BASE		0x0808A000
+#define TNETV107X_PSC_BASE			0x0808B000
+#define TNETV107X_TDM0_BASE			0x08100000
+#define TNETV107X_TDM1_BASE			0x08100100
+#define TNETV107X_MCDMA_BASE			0x08108000
+#define TNETV107X_UART0_DMA_BASE		0x08108200
+#define TNETV107X_USBSS_BASE			0x08120000
+#define TNETV107X_VLYNQ_CONTROL_BASE		0x0810D000
+#define TNETV107X_ASYNC_EMIF_CNTRL_BASE		0x08200000
+#define TNETV107X_VLYNQ_MEM_MAP_BASE		0x0C000000
+#define TNETV107X_IMCOP_BASE			0x01CC0000
+#define TNETV107X_MBX_LITE_BASE			0x07000000
+#define TNETV107X_ETHSS_BASE			0x0803C000
+#define TNETV107X_CPSW_BASE			0x0803C000
+#define TNETV107X_SPF_BASE			0x0803C800
+#define TNETV107X_IOPU_ETHSS_BASE		0x0803D000
+#define TNETV107X_VTP_CNTRL_0			0x0803D800
+#define TNETV107X_VTP_CNTRL_1			0x0803D900
+#define TNETV107X_UART2_DMA_BASE		0x08108400
+#define TNETV107X_INTERNAL_MEMORY		0x20000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE	0x30000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE	0x40000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE	0x44000000
+#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE	0x48000000
+#define TNETV107X_DDR_EMIF_DATA_BASE		0x80000000
+#define TNETV107X_DDR_EMIF_CONTROL_BASE		0x90000000
+
+/* LPSC module definitions */
+#define TNETV107X_LPSC_ARM			0
+#define TNETV107X_LPSC_GEM			1
+#define TNETV107X_LPSC_DDR2_PHY			2
+#define TNETV107X_LPSC_TPCC			3
+#define TNETV107X_LPSC_TPTC0			4
+#define TNETV107X_LPSC_TPTC1			5
+#define TNETV107X_LPSC_RAM			6
+#define TNETV107X_LPSC_MBX_LITE			7
+#define TNETV107X_LPSC_LCD			8
+#define TNETV107X_LPSC_ETHSS			9
+#define TNETV107X_LPSC_AEMIF			10
+#define TNETV107X_LPSC_CHIP_CFG			11
+#define TNETV107X_LPSC_TSC			12
+#define TNETV107X_LPSC_ROM			13
+#define TNETV107X_LPSC_UART2			14
+#define TNETV107X_LPSC_PKTSEC			15
+#define TNETV107X_LPSC_SECCTL			16
+#define TNETV107X_LPSC_KEYMGR			17
+#define TNETV107X_LPSC_KEYPAD			18
+#define TNETV107X_LPSC_GPIO			19
+#define TNETV107X_LPSC_MDIO			20
+#define TNETV107X_LPSC_SDIO0			21
+#define TNETV107X_LPSC_UART0			22
+#define TNETV107X_LPSC_UART1			23
+#define TNETV107X_LPSC_TIMER0			24
+#define TNETV107X_LPSC_TIMER1			25
+#define TNETV107X_LPSC_WDT_ARM			26
+#define TNETV107X_LPSC_WDT_DSP			27
+#define TNETV107X_LPSC_SSP			28
+#define TNETV107X_LPSC_TDM0			29
+#define TNETV107X_LPSC_VLYNQ			30
+#define TNETV107X_LPSC_MCDMA			31
+#define TNETV107X_LPSC_USB0			32
+#define TNETV107X_LPSC_TDM1			33
+#define TNETV107X_LPSC_DEBUGSS			34
+#define TNETV107X_LPSC_ETHSS_RGMII		35
+#define TNETV107X_LPSC_SYSTEM			36
+#define TNETV107X_LPSC_IMCOP			37
+#define TNETV107X_LPSC_SPARE			38
+#define TNETV107X_LPSC_SDIO1			39
+#define TNETV107X_LPSC_USB1			40
+#define TNETV107X_LPSC_USBSS			41
+#define TNETV107X_LPSC_DDR2_EMIF1_VRST		42
+#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST	43
+#define TNETV107X_LPSC_MAX			44
+
+/* Interrupt controller */
+#define INTC_GLB_EN			(TNETV107X_INTC_BASE + 0x10)
+#define INTC_HINT_EN			(TNETV107X_INTC_BASE + 0x1500)
+#define INTC_EN_CLR0			(TNETV107X_INTC_BASE + 0x380)
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h
new file mode 100644
index 0000000..f16bc99
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/mux.h
@@ -0,0 +1,306 @@
+/*
+ * TNETV107X: Pinmux APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+struct pin_config {
+	unsigned char reg_index;
+	unsigned char mask_offset;
+	unsigned char mode;
+};
+
+#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \
+			{ reg, offset, mux_mode }
+
+int mux_select_pin(short index);
+int mux_select_pins(const short *pins);
+
+enum tnetv107x_pin_mux_index {
+	TNETV107X_PIN_ASR_A00,
+	TNETV107X_PIN_GPIO32,
+	TNETV107X_PIN_ASR_A01,
+	TNETV107X_PIN_GPIO33,
+	TNETV107X_PIN_ASR_A02,
+	TNETV107X_PIN_GPIO34,
+	TNETV107X_PIN_ASR_A03,
+	TNETV107X_PIN_GPIO35,
+	TNETV107X_PIN_ASR_A04,
+	TNETV107X_PIN_GPIO36,
+	TNETV107X_PIN_ASR_A05,
+	TNETV107X_PIN_GPIO37,
+	TNETV107X_PIN_ASR_A06,
+	TNETV107X_PIN_GPIO38,
+	TNETV107X_PIN_ASR_A07,
+	TNETV107X_PIN_GPIO39,
+	TNETV107X_PIN_ASR_A08,
+	TNETV107X_PIN_GPIO40,
+	TNETV107X_PIN_ASR_A09,
+	TNETV107X_PIN_GPIO41,
+	TNETV107X_PIN_ASR_A10,
+	TNETV107X_PIN_GPIO42,
+	TNETV107X_PIN_ASR_A11,
+	TNETV107X_PIN_BOOT_STRP_0,
+	TNETV107X_PIN_ASR_A12,
+	TNETV107X_PIN_BOOT_STRP_1,
+	TNETV107X_PIN_ASR_A13,
+	TNETV107X_PIN_GPIO43,
+	TNETV107X_PIN_ASR_A14,
+	TNETV107X_PIN_GPIO44,
+	TNETV107X_PIN_ASR_A15,
+	TNETV107X_PIN_GPIO45,
+	TNETV107X_PIN_ASR_A16,
+	TNETV107X_PIN_GPIO46,
+	TNETV107X_PIN_ASR_A17,
+	TNETV107X_PIN_GPIO47,
+	TNETV107X_PIN_ASR_A18,
+	TNETV107X_PIN_GPIO48,
+	TNETV107X_PIN_SDIO1_DATA3_0,
+	TNETV107X_PIN_ASR_A19,
+	TNETV107X_PIN_GPIO49,
+	TNETV107X_PIN_SDIO1_DATA2_0,
+	TNETV107X_PIN_ASR_A20,
+	TNETV107X_PIN_GPIO50,
+	TNETV107X_PIN_SDIO1_DATA1_0,
+	TNETV107X_PIN_ASR_A21,
+	TNETV107X_PIN_GPIO51,
+	TNETV107X_PIN_SDIO1_DATA0_0,
+	TNETV107X_PIN_ASR_A22,
+	TNETV107X_PIN_GPIO52,
+	TNETV107X_PIN_SDIO1_CMD_0,
+	TNETV107X_PIN_ASR_A23,
+	TNETV107X_PIN_GPIO53,
+	TNETV107X_PIN_SDIO1_CLK_0,
+	TNETV107X_PIN_ASR_BA_1,
+	TNETV107X_PIN_GPIO54,
+	TNETV107X_PIN_SYS_PLL_CLK,
+	TNETV107X_PIN_ASR_CS0,
+	TNETV107X_PIN_ASR_CS1,
+	TNETV107X_PIN_ASR_CS2,
+	TNETV107X_PIN_TDM_PLL_CLK,
+	TNETV107X_PIN_ASR_CS3,
+	TNETV107X_PIN_ETH_PHY_CLK,
+	TNETV107X_PIN_ASR_D00,
+	TNETV107X_PIN_GPIO55,
+	TNETV107X_PIN_ASR_D01,
+	TNETV107X_PIN_GPIO56,
+	TNETV107X_PIN_ASR_D02,
+	TNETV107X_PIN_GPIO57,
+	TNETV107X_PIN_ASR_D03,
+	TNETV107X_PIN_GPIO58,
+	TNETV107X_PIN_ASR_D04,
+	TNETV107X_PIN_GPIO59_0,
+	TNETV107X_PIN_ASR_D05,
+	TNETV107X_PIN_GPIO60_0,
+	TNETV107X_PIN_ASR_D06,
+	TNETV107X_PIN_GPIO61_0,
+	TNETV107X_PIN_ASR_D07,
+	TNETV107X_PIN_GPIO62_0,
+	TNETV107X_PIN_ASR_D08,
+	TNETV107X_PIN_GPIO63_0,
+	TNETV107X_PIN_ASR_D09,
+	TNETV107X_PIN_GPIO64_0,
+	TNETV107X_PIN_ASR_D10,
+	TNETV107X_PIN_SDIO1_DATA3_1,
+	TNETV107X_PIN_ASR_D11,
+	TNETV107X_PIN_SDIO1_DATA2_1,
+	TNETV107X_PIN_ASR_D12,
+	TNETV107X_PIN_SDIO1_DATA1_1,
+	TNETV107X_PIN_ASR_D13,
+	TNETV107X_PIN_SDIO1_DATA0_1,
+	TNETV107X_PIN_ASR_D14,
+	TNETV107X_PIN_SDIO1_CMD_1,
+	TNETV107X_PIN_ASR_D15,
+	TNETV107X_PIN_SDIO1_CLK_1,
+	TNETV107X_PIN_ASR_OE,
+	TNETV107X_PIN_BOOT_STRP_2,
+	TNETV107X_PIN_ASR_RNW,
+	TNETV107X_PIN_GPIO29_0,
+	TNETV107X_PIN_ASR_WAIT,
+	TNETV107X_PIN_GPIO30_0,
+	TNETV107X_PIN_ASR_WE,
+	TNETV107X_PIN_BOOT_STRP_3,
+	TNETV107X_PIN_ASR_WE_DQM0,
+	TNETV107X_PIN_GPIO31,
+	TNETV107X_PIN_LCD_PD17_0,
+	TNETV107X_PIN_ASR_WE_DQM1,
+	TNETV107X_PIN_ASR_BA0_0,
+	TNETV107X_PIN_VLYNQ_CLK,
+	TNETV107X_PIN_GPIO14,
+	TNETV107X_PIN_LCD_PD19_0,
+	TNETV107X_PIN_VLYNQ_RXD0,
+	TNETV107X_PIN_GPIO15,
+	TNETV107X_PIN_LCD_PD20_0,
+	TNETV107X_PIN_VLYNQ_RXD1,
+	TNETV107X_PIN_GPIO16,
+	TNETV107X_PIN_LCD_PD21_0,
+	TNETV107X_PIN_VLYNQ_TXD0,
+	TNETV107X_PIN_GPIO17,
+	TNETV107X_PIN_LCD_PD22_0,
+	TNETV107X_PIN_VLYNQ_TXD1,
+	TNETV107X_PIN_GPIO18,
+	TNETV107X_PIN_LCD_PD23_0,
+	TNETV107X_PIN_SDIO0_CLK,
+	TNETV107X_PIN_GPIO19,
+	TNETV107X_PIN_SDIO0_CMD,
+	TNETV107X_PIN_GPIO20,
+	TNETV107X_PIN_SDIO0_DATA0,
+	TNETV107X_PIN_GPIO21,
+	TNETV107X_PIN_SDIO0_DATA1,
+	TNETV107X_PIN_GPIO22,
+	TNETV107X_PIN_SDIO0_DATA2,
+	TNETV107X_PIN_GPIO23,
+	TNETV107X_PIN_SDIO0_DATA3,
+	TNETV107X_PIN_GPIO24,
+	TNETV107X_PIN_EMU0,
+	TNETV107X_PIN_EMU1,
+	TNETV107X_PIN_RTCK,
+	TNETV107X_PIN_TRST_N,
+	TNETV107X_PIN_TCK,
+	TNETV107X_PIN_TDI,
+	TNETV107X_PIN_TDO,
+	TNETV107X_PIN_TMS,
+	TNETV107X_PIN_TDM1_CLK,
+	TNETV107X_PIN_TDM1_RX,
+	TNETV107X_PIN_TDM1_TX,
+	TNETV107X_PIN_TDM1_FS,
+	TNETV107X_PIN_KEYPAD_R0,
+	TNETV107X_PIN_KEYPAD_R1,
+	TNETV107X_PIN_KEYPAD_R2,
+	TNETV107X_PIN_KEYPAD_R3,
+	TNETV107X_PIN_KEYPAD_R4,
+	TNETV107X_PIN_KEYPAD_R5,
+	TNETV107X_PIN_KEYPAD_R6,
+	TNETV107X_PIN_GPIO12,
+	TNETV107X_PIN_KEYPAD_R7,
+	TNETV107X_PIN_GPIO10,
+	TNETV107X_PIN_KEYPAD_C0,
+	TNETV107X_PIN_KEYPAD_C1,
+	TNETV107X_PIN_KEYPAD_C2,
+	TNETV107X_PIN_KEYPAD_C3,
+	TNETV107X_PIN_KEYPAD_C4,
+	TNETV107X_PIN_KEYPAD_C5,
+	TNETV107X_PIN_KEYPAD_C6,
+	TNETV107X_PIN_GPIO13,
+	TNETV107X_PIN_TEST_CLK_IN,
+	TNETV107X_PIN_KEYPAD_C7,
+	TNETV107X_PIN_GPIO11,
+	TNETV107X_PIN_SSP0_0,
+	TNETV107X_PIN_SCC_DCLK,
+	TNETV107X_PIN_LCD_PD20_1,
+	TNETV107X_PIN_SSP0_1,
+	TNETV107X_PIN_SCC_CS_N,
+	TNETV107X_PIN_LCD_PD21_1,
+	TNETV107X_PIN_SSP0_2,
+	TNETV107X_PIN_SCC_D,
+	TNETV107X_PIN_LCD_PD22_1,
+	TNETV107X_PIN_SSP0_3,
+	TNETV107X_PIN_SCC_RESETN,
+	TNETV107X_PIN_LCD_PD23_1,
+	TNETV107X_PIN_SSP1_0,
+	TNETV107X_PIN_GPIO25,
+	TNETV107X_PIN_UART2_CTS,
+	TNETV107X_PIN_SSP1_1,
+	TNETV107X_PIN_GPIO26,
+	TNETV107X_PIN_UART2_RD,
+	TNETV107X_PIN_SSP1_2,
+	TNETV107X_PIN_GPIO27,
+	TNETV107X_PIN_UART2_RTS,
+	TNETV107X_PIN_SSP1_3,
+	TNETV107X_PIN_GPIO28,
+	TNETV107X_PIN_UART2_TD,
+	TNETV107X_PIN_UART0_CTS,
+	TNETV107X_PIN_UART0_RD,
+	TNETV107X_PIN_UART0_RTS,
+	TNETV107X_PIN_UART0_TD,
+	TNETV107X_PIN_UART1_RD,
+	TNETV107X_PIN_UART1_TD,
+	TNETV107X_PIN_LCD_AC_NCS,
+	TNETV107X_PIN_LCD_HSYNC_RNW,
+	TNETV107X_PIN_LCD_VSYNC_A0,
+	TNETV107X_PIN_LCD_MCLK,
+	TNETV107X_PIN_LCD_PD16_0,
+	TNETV107X_PIN_LCD_PCLK_E,
+	TNETV107X_PIN_LCD_PD00,
+	TNETV107X_PIN_LCD_PD01,
+	TNETV107X_PIN_LCD_PD02,
+	TNETV107X_PIN_LCD_PD03,
+	TNETV107X_PIN_LCD_PD04,
+	TNETV107X_PIN_LCD_PD05,
+	TNETV107X_PIN_LCD_PD06,
+	TNETV107X_PIN_LCD_PD07,
+	TNETV107X_PIN_LCD_PD08,
+	TNETV107X_PIN_GPIO59_1,
+	TNETV107X_PIN_LCD_PD09,
+	TNETV107X_PIN_GPIO60_1,
+	TNETV107X_PIN_LCD_PD10,
+	TNETV107X_PIN_ASR_BA0_1,
+	TNETV107X_PIN_GPIO61_1,
+	TNETV107X_PIN_LCD_PD11,
+	TNETV107X_PIN_GPIO62_1,
+	TNETV107X_PIN_LCD_PD12,
+	TNETV107X_PIN_GPIO63_1,
+	TNETV107X_PIN_LCD_PD13,
+	TNETV107X_PIN_GPIO64_1,
+	TNETV107X_PIN_LCD_PD14,
+	TNETV107X_PIN_GPIO29_1,
+	TNETV107X_PIN_LCD_PD15,
+	TNETV107X_PIN_GPIO30_1,
+	TNETV107X_PIN_EINT0,
+	TNETV107X_PIN_GPIO08,
+	TNETV107X_PIN_EINT1,
+	TNETV107X_PIN_GPIO09,
+	TNETV107X_PIN_GPIO00,
+	TNETV107X_PIN_LCD_PD20_2,
+	TNETV107X_PIN_TDM_CLK_IN_2,
+	TNETV107X_PIN_GPIO01,
+	TNETV107X_PIN_LCD_PD21_2,
+	TNETV107X_PIN_24M_CLK_OUT_1,
+	TNETV107X_PIN_GPIO02,
+	TNETV107X_PIN_LCD_PD22_2,
+	TNETV107X_PIN_GPIO03,
+	TNETV107X_PIN_LCD_PD23_2,
+	TNETV107X_PIN_GPIO04,
+	TNETV107X_PIN_LCD_PD16_1,
+	TNETV107X_PIN_USB0_RXERR,
+	TNETV107X_PIN_GPIO05,
+	TNETV107X_PIN_LCD_PD17_1,
+	TNETV107X_PIN_TDM_CLK_IN_1,
+	TNETV107X_PIN_GPIO06,
+	TNETV107X_PIN_LCD_PD18,
+	TNETV107X_PIN_24M_CLK_OUT_2,
+	TNETV107X_PIN_GPIO07,
+	TNETV107X_PIN_LCD_PD19_1,
+	TNETV107X_PIN_USB1_RXERR,
+	TNETV107X_PIN_ETH_PLL_CLK,
+	TNETV107X_PIN_MDIO,
+	TNETV107X_PIN_MDC,
+	TNETV107X_PIN_AIC_MUTE_STAT_N,
+	TNETV107X_PIN_TDM0_CLK,
+	TNETV107X_PIN_AIC_HNS_EN_N,
+	TNETV107X_PIN_TDM0_FS,
+	TNETV107X_PIN_AIC_HDS_EN_STAT_N,
+	TNETV107X_PIN_TDM0_TX,
+	TNETV107X_PIN_AIC_HNF_EN_STAT_N,
+	TNETV107X_PIN_TDM0_RX,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
new file mode 100644
index 0000000..961b710
--- /dev/null
+++ b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h
@@ -0,0 +1,38 @@
+/*
+ * TNETV107X: NAND definitions
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	TNETV107X_ASYNC_EMIF_CNTRL_BASE
+
+#define	MASK_CLE		0x4000
+#define	MASK_ALE		0x2000
+
+#define NAND_READ_START		0x00
+#define NAND_READ_END		0x30
+#define NAND_STATUS		0x70
+
+extern void davinci_nand_init(struct nand_chip *nand);
+
+#endif
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile
new file mode 100644
index 0000000..df542dc
--- /dev/null
+++ b/board/LaCie/edminiv2/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= edminiv2.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk
new file mode 100644
index 0000000..3dec1aa
--- /dev/null
+++ b/board/LaCie/edminiv2/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00100000
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
new file mode 100644
index 0000000..54c0ffe
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
+ * which CFI does not properly detect, hence the LEGACY config.
+ */
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+	int sect;
+
+	if (base != CONFIG_SYS_FLASH_BASE)
+		return 0;
+
+	info->size = 0;
+	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	/* set each sector's start address and size based */
+	for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+		info->start[sect] = base+info->size;
+		info->size += sectsz[sect];
+	}
+	/* This flash must be accessed in 8-bits mode, no buffer. */
+	info->flash_id = 0x01000000;
+	info->portwidth = FLASH_CFI_8BIT;
+	info->chipwidth = FLASH_CFI_BY8;
+	info->buffer_size = 0;
+	/* timings are derived from the Macronix datasheet. */
+	info->erase_blk_tout = 1000;
+	info->write_tout = 10;
+	info->buffer_write_tout = 300;
+	/* Commands and addresses are for AMD mode 8-bit access. */
+	info->vendor = CFI_CMDSET_AMD_LEGACY;
+	info->cmd_reset = 0xF0;
+	info->interface = FLASH_CFI_X8;
+	info->legacy_unlock = 0;
+	info->ext_addr = 0;
+	info->addr_unlock1 = 0x00000aaa;
+	info->addr_unlock2 = 0x00000555;
+	/* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
+	info->manufacturer_id = 0x22;
+	info->device_id = 0xBA;
+	info->device_id2 = 0;
+	info->cfi_version = 0x3133;
+	info->cfi_offset = 0x0000;
+	info->name = "MX29LV400CB";
+
+	return 1;
+}
+#endif				/* CONFIG_SYS_FLASH_CFI */
+
+int board_init(void)
+{
+	/* arch number of board */
+	gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+	/* boot parameter start at 256th byte of RAM base */
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+	return 0;
+}
diff --git a/board/davinci/da830evm/Makefile b/board/davinci/da8xxevm/Makefile
index 02636fa..17cbe86 100644
--- a/board/davinci/da830evm/Makefile
+++ b/board/davinci/da8xxevm/Makefile
@@ -27,7 +27,11 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= da830evm.o
+COBJS-y	+= common.o
+COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= da830evm.o
+COBJS-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= da850evm.o
+
+COBJS   := $(COBJS-y)
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/davinci/da8xxevm/common.c b/board/davinci/da8xxevm/common.c
new file mode 100644
index 0000000..9cd5204c
--- /dev/null
+++ b/board/davinci/da8xxevm/common.c
@@ -0,0 +1,55 @@
+/*
+ * Miscellaneous DA8XX functions.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include "common.h"
+
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
+{
+	/*
+	 * Mask all IRQs by clearing the global enable and setting
+	 * the enable clear for all the 90 interrupts.
+	 */
+
+	writel(0, &davinci_aintc_regs->ger);
+
+	writel(0, &davinci_aintc_regs->hier);
+
+	writel(0xffffffff, &davinci_aintc_regs->ecr1);
+	writel(0xffffffff, &davinci_aintc_regs->ecr2);
+	writel(0xffffffff, &davinci_aintc_regs->ecr3);
+}
+#endif
+
+/*
+ * Enable PSC for various peripherals.
+ */
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+				    const int n_items)
+{
+	int i;
+
+	for (i = 0; i < n_items; i++)
+		lpsc_on(item[i].lpsc_no);
+
+	return 0;
+}
diff --git a/board/davinci/da8xxevm/common.h b/board/davinci/da8xxevm/common.h
new file mode 100644
index 0000000..7ae63a6
--- /dev/null
+++ b/board/davinci/da8xxevm/common.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __COMMON_H
+#define __COMMON_H
+
+struct lpsc_resource {
+	const int	lpsc_no;
+};
+
+void irq_init(void);
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+				    int n_items);
+
+#endif /* __COMMON_H */
diff --git a/board/davinci/da830evm/config.mk b/board/davinci/da8xxevm/config.mk
index 6da29a9..6da29a9 100644
--- a/board/davinci/da830evm/config.mk
+++ b/board/davinci/da8xxevm/config.mk
diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da8xxevm/da830evm.c
index 6385443..57506d6 100644
--- a/board/davinci/da830evm/da830evm.c
+++ b/board/davinci/da8xxevm/da830evm.c
@@ -41,6 +41,7 @@
 #include <asm/arch/emac_defs.h>
 #include <asm/io.h>
 #include "../common/misc.h"
+#include "common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -120,21 +121,18 @@ static const struct pinmux_resource pinmuxes[] = {
 #endif
 };
 
+static const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI0 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+};
+
 int board_init(void)
 {
 #ifndef CONFIG_USE_IRQ
-	/*
-	 * Mask all IRQs by clearing the global enable and setting
-	 * the enable clear for all the 90 interrupts.
-	 */
-
-	writel(0, &davinci_aintc_regs->ger);
-
-	writel(0, &davinci_aintc_regs->hier);
-
-	writel(0xffffffff, &davinci_aintc_regs->ecr1);
-	writel(0xffffffff, &davinci_aintc_regs->ecr2);
-	writel(0xffffffff, &davinci_aintc_regs->ecr3);
+	irq_init();
 #endif
 
 #ifdef CONFIG_NAND_DAVINCI
@@ -165,11 +163,8 @@ int board_init(void)
 	 * assuming here that the DSP bootloader has set the IOPU
 	 * such that PSC access is available to ARM
 	 */
-	lpsc_on(DAVINCI_LPSC_AEMIF);    /* NAND, NOR */
-	lpsc_on(DAVINCI_LPSC_SPI0);     /* Serial Flash */
-	lpsc_on(DAVINCI_LPSC_EMAC);     /* image download */
-	lpsc_on(DAVINCI_LPSC_UART2);    /* console */
-	lpsc_on(DAVINCI_LPSC_GPIO);
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
 
 	/* setup the SUSPSRC for ARM to control emulation suspend */
 	writel(readl(&davinci_syscfg_regs->suspsrc) &
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
new file mode 100644
index 0000000..959b2c6
--- /dev/null
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include "../common/misc.h"
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define pinmux	(&davinci_syscfg_regs->pinmux)
+
+/* SPI0 pin muxer settings */
+static const struct pinmux_config spi1_pins[] = {
+	{ pinmux[5], 1, 1 },
+	{ pinmux[5], 1, 2 },
+	{ pinmux[5], 1, 4 },
+	{ pinmux[5], 1, 5 }
+};
+
+/* UART pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+	{ pinmux[0], 4, 6 },
+	{ pinmux[0], 4, 7 },
+	{ pinmux[4], 2, 4 },
+	{ pinmux[4], 2, 5 }
+};
+
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+	{ pinmux[4], 2, 2 },
+	{ pinmux[4], 2, 3 }
+};
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+	PINMUX_ITEM(spi1_pins),
+#endif
+	PINMUX_ITEM(uart_pins),
+	PINMUX_ITEM(i2c_pins),
+};
+
+static const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+	irq_init();
+#endif
+
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/*
+	 * Power on required peripherals
+	 * ARM does not have access by default to PSC0 and PSC1
+	 * assuming here that the DSP bootloader has set the IOPU
+	 * such that PSC access is available to ARM
+	 */
+	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+		return 1;
+
+	/* setup the SUSPSRC for ARM to control emulation suspend */
+	writel(readl(&davinci_syscfg_regs->suspsrc) &
+	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+		 DAVINCI_SYSCFG_SUSPSRC_UART2),
+	       &davinci_syscfg_regs->suspsrc);
+
+	/* configure pinmux settings */
+	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+		return 1;
+
+	/* enable the console UART */
+	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+		DAVINCI_UART_PWREMU_MGMT_UTRST),
+	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+	return 0;
+}
diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
new file mode 100644
index 0000000..3a6b1a1
--- /dev/null
+++ b/board/logicpd/am3517evm/Makefile
@@ -0,0 +1,46 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= am3517evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
new file mode 100644
index 0000000..bbb6e83
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -0,0 +1,76 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_AM3517EVM();
+}
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
new file mode 100644
index 0000000..3d74ef1
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -0,0 +1,445 @@
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"AM3517EVM Board",
+	"NAND",
+};
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	/*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+	 /*sdrc_strben_dly1*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	/* WriteProtect */\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*CardDetect*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+	/*SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4)) \
+							/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk
new file mode 100644
index 0000000..f7a35ce
--- /dev/null
+++ b/board/logicpd/am3517evm/config.mk
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index 75e4330..355e9ea 100644
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -37,6 +37,10 @@
 #include <asm/mach-types.h>
 #include "pandora.h"
 
+#define TWL4030_BB_CFG_BBCHEN		(1 << 4)
+#define TWL4030_BB_CFG_BBSEL_3200MV	(3 << 2)
+#define TWL4030_BB_CFG_BBISEL_500UA	2
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -78,6 +82,11 @@ int misc_init_r(void)
 	writel(GPIO28, &gpio5_base->setdataout);
 	writel(GPIO4, &gpio6_base->setdataout);
 
+	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
+	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+		TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
+		TWL4030_BB_CFG_BBISEL_500UA, TWL4030_PM_RECEIVER_BB_CFG);
+
 	dieid_num_r();
 
 	return 0;
diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
new file mode 100644
index 0000000..dd5b02e
--- /dev/null
+++ b/board/ronetix/pm9g45/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y += pm9g45.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ronetix/pm9g45/config.mk b/board/ronetix/pm9g45/config.mk
new file mode 100644
index 0000000..7fe9d03
--- /dev/null
+++ b/board/ronetix/pm9g45/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x73f00000
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
new file mode 100644
index 0000000..3b4d9a3
--- /dev/null
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9g45_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t	*smc	= (at91_smc_t *) AT91_SMC_BASE;
+	at91_matrix_t	*matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->ccr[6]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+		&smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+		&smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+		&smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+		AT91_SMC_MODE_EXNW_DISABLE |
+		AT91_SMC_MODE_DBW_8 |
+		AT91_SMC_MODE_TDF_CYCLE(3),
+		&smc->cs[3].mode);
+
+	writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+	/* Configure RDY/BSY */
+	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+
+	/* Enable NandFlash */
+	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9g45_macb_hw_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pio_t	*pio	= (at91_pio_t *) AT91_PIO_BASE;
+
+	/*
+	 * PD2 enables the 50MHz oscillator for Ethernet PHY
+	 * 1 - enable
+	 * 0 - disable
+	 */
+	at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
+	at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
+
+	/* Enable clock */
+	writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA15) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA12) => PHY ADDR0
+	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* Enable Ctrlc */
+	console_init_f();
+
+	writel((1 << AT91SAM9G45_ID_PIOA) |
+		(1 << AT91SAM9G45_ID_PIOB) |
+		(1 << AT91SAM9G45_ID_PIOC) |
+		(1 << AT91SAM9G45_ID_PIODE), &pmc->pcer);
+
+	/* arch number of AT91SAM9M10G45EK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	pm9g45_nand_hw_init();
+#endif
+
+#ifdef CONFIG_MACB
+	pm9g45_macb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
+#endif
+	return rc;
+}
diff --git a/board/samsung/goni/Makefile b/board/samsung/goni/Makefile
new file mode 100644
index 0000000..9b4c886
--- /dev/null
+++ b/board/samsung/goni/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= goni.o onenand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/goni/config.mk b/board/samsung/goni/config.mk
new file mode 100644
index 0000000..0e9dd45
--- /dev/null
+++ b/board/samsung/goni/config.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (C) 2010 Samsung Electronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# On S5PC100 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x38000000 to 0x40000000 (128MiB)
+#
+# On S5PC110 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x40000000 to 0x50000000 (256MiB)
+#
+TEXT_BASE = 0x34800000
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
new file mode 100644
index 0000000..e512c59
--- /dev/null
+++ b/board/samsung/goni/goni.c
@@ -0,0 +1,55 @@
+/*
+ *  Copyright (C) 2008-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_GONI;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	puts("Board:\tGoni\n");
+	return 0;
+}
+#endif
diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S
new file mode 100644
index 0000000..4b72992
--- /dev/null
+++ b/board/samsung/goni/lowlevel_init.S
@@ -0,0 +1,585 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has S5PC100 GPIO base, 0xE0300000
+ * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
+ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r11, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r7, =S5PC100_GPIO_BASE
+	ldr	r8, =S5PC100_GPIO_BASE
+	/* Read CPU ID */
+	ldr	r2, =S5PC1XX_PRO_ID
+	ldr	r0, [r2]
+	mov	r1, #0x00010000
+	and	r0, r0, r1
+	cmp	r0, r5
+	beq	100f
+	ldr	r8, =S5PC110_GPIO_BASE
+100:
+	/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
+	cmp	r7, r8
+	beq	skip_check_didle			@ Support C110 only
+
+	ldr	r0, =S5PC110_RST_STAT
+	ldr	r1, [r0]
+	and	r1, r1, #0x000D0000
+	cmp	r1, #(0x1 << 19)			@ DEEPIDLE_WAKEUP
+	beq	didle_wakeup
+	cmp	r7, r8
+
+skip_check_didle:
+	addeq	r0, r8, #0x280				@ S5PC100_GPIO_J4
+	addne	r0, r8, #0x2C0				@ S5PC110_GPIO_J4
+	ldr	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 4)			@ 1 * 4-bit
+	orr	r1, r1, #(0x1 << 4)
+	str	r1, [r0, #0x0]				@ GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
+#ifdef CONFIG_ONENAND_IPL
+	orr	r1, r1, #(1 << 1)			@ 1 * 1-bit
+#else
+	bic	r1, r1, #(1 << 1)
+#endif
+	str	r1, [r0, #0x4]				@ GPIO_DAT_OFFSET
+
+	/* Don't setup at s5pc100 */
+	beq	100f
+
+	/*
+	 * Initialize Async Register Setting for EVT1
+	 * Because we are setting EVT1 as the default value of EVT0,
+	 * setting EVT0 as well does not make things worse.
+	 * Thus, for the simplicity, we set for EVT0, too
+	 *
+	 * The "Async Registers" are:
+	 *	0xE0F0_0000
+	 *	0xE1F0_0000
+	 *	0xF180_0000
+	 *	0xF190_0000
+	 *	0xF1A0_0000
+	 *	0xF1B0_0000
+	 *	0xF1C0_0000
+	 *	0xF1D0_0000
+	 *	0xF1E0_0000
+	 *	0xF1F0_0000
+	 *	0xFAF0_0000
+	 */
+	ldr     r0, =0xe0f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xe1f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1800000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1900000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1a00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1b00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1c00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1d00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1e00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xf1f00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	ldr     r0, =0xfaf00000
+	ldr     r1, [r0]
+	bic     r1, r1, #0x1
+	str     r1, [r0]
+
+	/*
+	 * Diable ABB block to reduce sleep current at low temperature
+	 * Note that it's hidden register setup don't modify it
+	 */
+	ldr	r0, =0xE010C300
+	ldr	r1, =0x00800000
+	str	r1, [r0]
+
+100:
+	/* IO retension release */
+	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
+	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
+	ldr	r1, [r0]
+	ldreq	r2, =(1 << 31)				@ IO_RET_REL
+	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+	orr	r1, r1, r2
+	/* Do not release retention here for S5PC110 */
+	streq	r1, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Disable Watchdog */
+	ldreq	r0, =S5PC100_WATCHDOG_BASE		@ 0xEA200000
+	ldrne	r0, =S5PC110_WATCHDOG_BASE		@ 0xE2700000
+	str	r5, [r0]
+
+	/* setting SRAM */
+	ldreq	r0, =S5PC100_SROMC_BASE
+	ldrne	r0, =S5PC110_SROMC_BASE
+	ldr	r1, =0x9
+	str	r1, [r0]
+#endif
+
+	/* S5PC100 has 3 groups of interrupt sources */
+	ldreq	r0, =S5PC100_VIC0_BASE			@ 0xE4000000
+	ldrne	r0, =S5PC110_VIC0_BASE			@ 0xF2000000
+	add	r1, r0, #0x00100000
+	add	r2, r0, #0x00200000
+
+	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
+	mvn	r3, #0x0
+	str	r3, [r0, #0x14]				@ INTENCLEAR
+	str	r3, [r1, #0x14]				@ INTENCLEAR
+	str	r3, [r2, #0x14]				@ INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Set all interrupts as IRQ */
+	str	r5, [r0, #0xc]				@ INTSELECT
+	str	r5, [r1, #0xc]				@ INTSELECT
+	str	r5, [r2, #0xc]				@ INTSELECT
+
+	/* Pending Interrupt Clear */
+	str	r5, [r0, #0xf00]			@ INTADDRESS
+	str	r5, [r1, #0xf00]			@ INTADDRESS
+	str	r5, [r2, #0xf00]			@ INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+	/* for UART */
+	bl	uart_asm_init
+
+	bl	internal_ram_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+	/* init system clock */
+	bl	system_clock_init
+
+	/* OneNAND Sync Read Support at S5PC110 only
+	 * RM[15]	: Sync Read
+	 * BRWL[14:12]	: 7 CLK
+	 * BL[11:9]	: Continuous
+	 * VHF[3]	: Very High Frequency Enable (Over 83MHz)
+	 * HF[2]	: High Frequency Enable (Over 66MHz)
+	 * WM[1]	: Sync Write
+	 */
+	cmp	r7, r8
+	ldrne	r1, =0xE006
+	ldrne	r0, =0xB001E442
+	strneh	r1, [r0]
+
+	/*
+	 * GCE[26]	: Gated Clock Enable
+	 * RPE[17]	: Enables Read Prefetch
+	 */
+	ldrne	r1, =((1 << 26) | (1 << 17) | 0xE006)
+	ldrne	r0, =0xB0600000
+	strne	r1, [r0, #0x100]			@ ONENAND_IF_CTRL
+	ldrne	r1, =0x1212
+	strne	r1, [r0, #0x108]
+
+	/* Board detection to set proper memory configuration */
+	cmp	r7, r8
+	moveq	r9, #1		/* r9 has 1Gib default at s5pc100 */
+	movne	r9, #2		/* r9 has 2Gib default at s5pc110 */
+
+	ldr	r2, =0xE0200200
+	ldr	r4, [r2, #0x48]
+
+	bic	r1, r4, #(0x3F << 4)	/* PULLUP_DISABLE: 3 * 2-bit */
+	bic	r1, r1, #(0x3 << 2)	/* PULLUP_DISABLE: 2 * 2-bit */
+	bic	r1, r1, #(0x3 << 14)	/* PULLUP_DISABLE: 2 * 2-bit */
+	str	r1, [r2, #0x48]
+	/* For write completion */
+	nop
+	nop
+
+	ldr	r3, [r2, #0x44]
+	and	r1, r3, #(0x7 << 2)
+	mov	r1, r1, lsr #2
+	cmp	r1, #0x5
+	moveq	r9, #3
+	cmp	r1, #0x6
+	moveq	r9, #1
+	cmp	r1, #0x7
+	moveq	r9, #2
+	and	r0, r3, #(0x1 << 1)
+	mov	r0, r0, lsr #1
+	orr	r1, r1, r0, lsl #3
+	cmp	r1, #0x8
+	moveq	r9, #3
+	and	r1, r3, #(0x7 << 2)
+	mov	r1, r1, lsr #2
+	and	r0, r3, #(0x1 << 7)
+	mov	r0, r0, lsr #7
+	orr	r1, r1, r0, lsl #3
+	cmp	r1, #0x9
+	moveq	r9, #3
+	str	r4, [r2, #0x48]		/* Restore PULLUP configuration */
+
+	bl	mem_ctrl_asm_init
+
+	/* Wakeup support. Don't know if it's going to be used, untested. */
+	ldreq	r0, =S5PC100_RST_STAT
+	ldrne	r0, =S5PC110_RST_STAT
+	ldr	r1, [r0]
+	biceq	r1, r1, #0xfffffff7
+	moveq	r2, #(1 << 3)
+	bicne	r1, r1, #0xfffeffff
+	movne	r2, #(1 << 16)
+	cmp	r1, r2
+	bne	1f
+wakeup:
+	/* turn off L2 cache */
+	bl	l2_cache_disable
+
+	cmp	r7, r8
+	ldreq	r0, =0xC100
+	ldrne	r0, =0xC110
+
+	/* invalidate L2 cache also */
+	bl	invalidate_dcache
+
+	/* turn on L2 cache */
+	bl	l2_cache_enable
+
+	cmp	r7, r8
+	/* Load return address and jump to kernel */
+	ldreq	r0, =S5PC100_INFORM0
+	ldrne	r0, =S5PC110_INFORM0
+
+	/* r1 = physical address of s5pc1xx_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel (sleep-s5pc1xx.S) */
+	mov	pc, r1
+	nop
+	nop
+#else
+	cmp	r7, r8
+	/* Clear wakeup status register */
+	ldreq	r0, =S5PC100_WAKEUP_STAT
+	ldrne	r0, =S5PC110_WAKEUP_STAT
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	/* IO retension release */
+	ldreq	r0, =S5PC100_OTHERS			@ 0xE0108200
+	ldrne	r0, =S5PC110_OTHERS			@ 0xE010E000
+	ldr	r1, [r0]
+	ldreq	r2, =(1 << 31)				@ IO_RET_REL
+	ldrne	r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+	orr	r1, r1, r2
+	str	r1, [r0]
+
+#endif
+	b	1f
+
+didle_wakeup:
+	/* Wait when APLL is locked */
+	ldr	r0, =0xE0100100			@ S5PC110_APLL_CON
+lockloop:
+	ldr	r1, [r0]
+	and	r1, r1, #(1 << 29)
+	cmp	r1, #(1 << 29)
+	bne	lockloop
+
+	ldr	r0, =S5PC110_INFORM0
+	ldr	r1, [r0]
+	mov	pc, r1
+	nop
+	nop
+	nop
+	nop
+	nop
+
+1:
+	mov	lr, r11
+	mov	pc, lr
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r0, =S5PC1XX_CLOCK_BASE		@ 0xE0100000
+
+	/* Check S5PC100 */
+	cmp	r7, r8
+	bne	110f
+100:
+	/* Set Lock Time */
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r0, #0x000]		@ S5PC100_APLL_LOCK
+	str	r1, [r0, #0x004]		@ S5PC100_MPLL_LOCK
+	str	r1, [r0, #0x008]		@ S5PC100_EPLL_LOCK
+	str	r1, [r0, #0x00C]		@ S5PC100_HPLL_LOCK
+
+	/* S5P_APLL_CON */
+	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
+	str	r1, [r0, #0x100]
+	/* S5P_MPLL_CON */
+	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+	str	r1, [r0, #0x104]
+	/* S5P_EPLL_CON */
+	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+	str	r1, [r0, #0x108]
+	/* S5P_HPLL_CON */
+	ldr	r1, =0x80600603		@ SDIV 3, PDIV 6, MDIV 96
+	str	r1, [r0, #0x10C]
+
+	ldr     r1, [r0, #0x300]
+	ldr     r2, =0x00003fff
+	bic     r1, r1, r2
+	ldr     r2, =0x00011301
+
+	orr	r1, r1, r2
+	str	r1, [r0, #0x300]
+	ldr     r1, [r0, #0x304]
+	ldr     r2, =0x00011110
+	orr     r1, r1, r2
+	str     r1, [r0, #0x304]
+	ldr     r1, =0x00000001
+	str     r1, [r0, #0x308]
+
+	/* Set Source Clock */
+	ldr	r1, =0x00001111			@ A, M, E, HPLL Muxing
+	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
+
+	b	200f
+110:
+	ldr	r0, =0xE010C000			@ S5PC110_PWR_CFG
+
+	/* Set OSC_FREQ value */
+	ldr	r1, =0xf
+	str	r1, [r0, #0x100]		@ S5PC110_OSC_FREQ
+
+	/* Set MTC_STABLE value */
+	ldr	r1, =0xffffffff
+	str	r1, [r0, #0x110]		@ S5PC110_MTC_STABLE
+
+	/* Set CLAMP_STABLE value */
+	ldr	r1, =0x3ff03ff
+	str	r1, [r0, #0x114]		@ S5PC110_CLAMP_STABLE
+
+	ldr	r0, =S5PC1XX_CLOCK_BASE		@ 0xE0100000
+
+	/* Set Clock divider */
+	ldr	r1, =0x14131330			@ 1:1:4:4, 1:4:5
+	str	r1, [r0, #0x300]
+	ldr	r1, =0x11110111			@ UART[3210]: MMC[3210]
+	str	r1, [r0, #0x310]
+
+	/* Set Lock Time */
+	ldr	r1, =0x2cf			@ Locktime : 30us
+	str	r1, [r0, #0x000]		@ S5PC110_APLL_LOCK
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r0, #0x008]		@ S5PC110_MPLL_LOCK
+	str	r1, [r0, #0x010]		@ S5PC110_EPLL_LOCK
+	str	r1, [r0, #0x020]		@ S5PC110_VPLL_LOCK
+
+	/* S5PC110_APLL_CON */
+	ldr	r1, =0x80C80601			@ 800MHz
+	str	r1, [r0, #0x100]
+	/* S5PC110_MPLL_CON */
+	ldr	r1, =0x829B0C01			@ 667MHz
+	str	r1, [r0, #0x108]
+	/* S5PC110_EPLL_CON */
+	ldr	r1, =0x80600602			@  96MHz VSEL 0 P 6 M 96 S 2
+	str	r1, [r0, #0x110]
+	/* S5PC110_VPLL_CON */
+	ldr	r1, =0x806C0603			@  54MHz
+	str	r1, [r0, #0x120]
+
+	/* Set Source Clock */
+	ldr	r1, =0x10001111			@ A, M, E, VPLL Muxing
+	str	r1, [r0, #0x200]		@ S5PC1XX_CLK_SRC0
+
+	/* OneDRAM(DMC0) clock setting */
+	ldr	r1, =0x01000000			@ ONEDRAM_SEL[25:24] 1 SCLKMPLL
+	str	r1, [r0, #0x218]		@ S5PC110_CLK_SRC6
+	ldr	r1, =0x30000000			@ ONEDRAM_RATIO[31:28] 3 + 1
+	str	r1, [r0, #0x318]		@ S5PC110_CLK_DIV6
+
+	/* XCLKOUT = XUSBXTI 24MHz */
+	add	r2, r0, #0xE000			@ S5PC110_OTHERS
+	ldr     r1, [r2]
+	orr	r1, r1, #(0x3 << 8)		@ CLKOUT[9:8] 3 XUSBXTI
+	str	r1, [r2]
+
+	/* CLK_IP0 */
+	ldr	r1, =0x8fefeeb			@ DMC[1:0] PDMA0[3] IMEM[5]
+	str	r1, [r0, #0x460]		@ S5PC110_CLK_IP0
+
+	/* CLK_IP1 */
+	ldr	r1, =0xe9fdf0f9			@ FIMD[0] USBOTG[16]
+						@ NANDXL[24]
+	str	r1, [r0, #0x464]		@ S5PC110_CLK_IP1
+
+	/* CLK_IP2 */
+	ldr	r1, =0xf75f7fc			@ CORESIGHT[8] MODEM[9]
+						@ HOSTIF[10] HSMMC0[16]
+						@ HSMMC2[18] VIC[27:24]
+	str	r1, [r0, #0x468]		@ S5PC110_CLK_IP2
+
+	/* CLK_IP3 */
+	ldr	r1, =0x8eff038c			@ I2C[8:6]
+						@ SYSTIMER[16] UART0[17]
+						@ UART1[18] UART2[19]
+						@ UART3[20] WDT[22]
+						@ PWM[23] GPIO[26] SYSCON[27]
+	str	r1, [r0, #0x46c]		@ S5PC110_CLK_IP3
+
+	/* CLK_IP4 */
+	ldr	r1, =0xfffffff1			@ CHIP_ID[0] TZPC[8:5]
+	str	r1, [r0, #0x470]		@ S5PC110_CLK_IP3
+
+200:
+	/* wait at least 200us to stablize all clock */
+	mov	r2, #0x10000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	mov	pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+internal_ram_init:
+	ldreq	r0, =0xE3800000
+	ldrne	r0, =0xF1500000
+	ldr	r1, =0x0
+	str	r1, [r0]
+
+	mov	pc, lr
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	/* set GPIO to enable UART0-UART4 */
+	mov	r0, r8
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x0]			@ S5PC100_GPIO_A0_OFFSET
+	ldr	r1, =0x00002222
+	str	r1, [r0, #0x20]			@ S5PC100_GPIO_A1_OFFSET
+
+	/* Check S5PC100 */
+	cmp	r7, r8
+	bne	110f
+
+	/* UART_SEL GPK0[5] at S5PC100 */
+	add	r0, r8, #0x2A0			@ S5PC100_GPIO_K0_OFFSET
+	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 20)		@ 20 = 5 * 4-bit
+	orr	r1, r1, #(0x1 << 20)		@ Output
+	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+	bic	r1, r1, #(0x3 << 10)		@ 10 = 5 * 2-bit
+	orr	r1, r1, #(0x2 << 10)		@ Pull-up enabled
+	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+
+	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+	orr	r1, r1, #(1 << 5)		@ 5 = 5 * 1-bit
+	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+
+	b	200f
+110:
+	/*
+	 * Note that the following address
+	 * 0xE020'0360 is reserved address at S5PC100
+	 */
+	/* UART_SEL MP0_5[7] at S5PC110 */
+	add	r0, r8, #0x360			@ S5PC110_GPIO_MP0_5_OFFSET
+	ldr	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
+	orr	r1, r1, #(0x1 << 28)		@ Output
+	str	r1, [r0, #0x0]			@ S5PC1XX_GPIO_CON_OFFSET
+
+	ldr	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
+	orr	r1, r1, #(0x2 << 14)		@ Pull-up enabled
+	str	r1, [r0, #0x8]			@ S5PC1XX_GPIO_PULL_OFFSET
+
+	ldr	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
+	str	r1, [r0, #0x4]			@ S5PC1XX_GPIO_DAT_OFFSET
+200:
+	mov	pc, lr
+#endif
diff --git a/board/samsung/goni/mem_setup.S b/board/samsung/goni/mem_setup.S
new file mode 100644
index 0000000..c4d2845
--- /dev/null
+++ b/board/samsung/goni/mem_setup.S
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	cmp	r7, r8
+
+	ldreq	r0, =S5PC100_DMC_BASE			@ 0xE6000000
+	ldrne	r0, =S5PC110_DMC0_BASE			@ 0xF0000000
+	ldrne	r6, =S5PC110_DMC1_BASE			@ 0xF1400000
+
+	/* DLL parameter setting */
+	ldr	r1, =0x50101000
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+	ldr	r1, =0x000000f4
+	str	r1, [r0, #0x01C]			@ PHYCONTROL1_OFFSET
+	strne	r1, [r6, #0x01C]			@ PHYCONTROL1_OFFSET
+	ldreq	r1, =0x0
+	streq	r1, [r0, #0x020]			@ PHYCONTROL2_OFFSET
+
+	/* DLL on */
+	ldr	r1, =0x50101002
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	/* DLL start */
+	ldr	r1, =0x50101003
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	mov	r2, #0x4000
+wait:	subs	r2, r2, #0x1
+	cmp	r2, #0x0
+	bne	wait
+
+	cmp	r7, r8
+	/* Force value locking for DLL off */
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	/* DLL off */
+	ldr	r1, =0x50101009
+	str	r1, [r0, #0x018]			@ PHYCONTROL0_OFFSET
+	strne	r1, [r6, #0x018]			@ PHYCONTROL0_OFFSET
+
+	/* auto refresh off */
+	ldr	r1, =0xff001010 | (1 << 7)
+	ldr	r2, =0xff001010 | (1 << 7)
+	str	r1, [r0, #0x000]			@ CONCONTROL_OFFSET
+	strne	r2, [r6, #0x000]			@ CONCONTROL_OFFSET
+
+	/*
+	 * Burst Length 4, 2 chips, 32-bit, LPDDR
+	 * OFF: dynamic self refresh, force precharge, dynamic power down off
+	 */
+	ldr	r1, =0x00212100
+	ldr	r2, =0x00212100
+	str	r1, [r0, #0x004]			@ MEMCONTROL_OFFSET
+	strne	r2, [r6, #0x004]			@ MEMCONTROL_OFFSET
+
+	/*
+	 * Note:
+	 * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only)
+	 * So finally Bank1 OneDRAM should address start at at 0x3000'0000
+	 */
+
+	/*
+	 * DMC0: CS0 : S5PC100/S5PC110
+	 * 0x30 -> 0x30000000
+	 * 0xf8 -> 0x37FFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	ldr	r3, =0x30f80222
+	ldr	r4, =0x40f00222
+swap_memory:
+	str	r3, [r0, #0x008]			@ MEMCONFIG0_OFFSET
+	str	r4, [r0, #0x00C]			@ dummy write
+
+	/*
+	 * DMC1: CS0 : S5PC110
+	 * 0x40 -> 0x40000000
+	 * 0xf8 -> 0x47FFFFFF (1Gib)
+	 * 0x40 -> 0x40000000
+	 * 0xf0 -> 0x4FFFFFFF (2Gib)
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits  - Col (1Gib)
+	 * [11:8 ] 3: 10 bits - Col (2Gib)
+	 * [ 7:4 ] 2: 14 bits - Row
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	/* Default : 2GiB */
+	ldr	r4, =0x40f01322				@ 2Gib: MCP B
+	ldr	r5, =0x50f81312				@ dummy: MCP D
+	cmp	r9, #1
+	ldreq	r4, =0x40f81222				@ 1Gib: MCP A
+	cmp	r9, #3
+	ldreq	r5, =0x50f81312				@ 2Gib + 1Gib: MCP D
+	cmp	r9, #4
+	ldreq	r5, =0x50f01312				@ 2Gib + 2Gib: MCP E
+
+	cmp	r7, r8
+	strne	r4, [r6, #0x008]			@ MEMCONFIG0_OFFSET
+	strne	r5, [r6, #0x00C]			@ MEMCONFIG1_OFFSET
+
+	/*
+	 * DMC0: CS1: S5PC100
+	 * 0x38 -> 0x38000000
+	 * 0xf8 -> 0x3fFFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	eoreq	r3, r3, #0x08000000
+	streq	r3, [r0, #0xc]				@ MEMCONFIG1_OFFSET
+
+	ldr	r1, =0x20000000
+	str	r1, [r0, #0x014]			@ PRECHCONFIG_OFFSET
+	strne	r1, [r0, #0x014]			@ PRECHCONFIG_OFFSET
+	strne	r1, [r6, #0x014]			@ PRECHCONFIG_OFFSET
+
+	/*
+	 * S5PC100:
+	 * DMC:  CS0: 166MHz
+	 *       CS1: 166MHz
+	 * S5PC110:
+	 * DMC0: CS0: 166MHz
+	 * DMC1: CS0: 200MHz
+	 *
+	 * 7.8us * 200MHz %LE %LONG1560(0x618)
+	 * 7.8us * 166MHz %LE %LONG1294(0x50E)
+	 * 7.8us * 133MHz %LE %LONG1038(0x40E),
+	 * 7.8us * 100MHz %LE %LONG780(0x30C),
+	 */
+	ldr	r1, =0x0000050E
+	str	r1, [r0, #0x030]			@ TIMINGAREF_OFFSET
+	ldrne	r1, =0x00000618
+	strne	r1, [r6, #0x030]			@ TIMINGAREF_OFFSET
+
+	ldr	r1, =0x14233287
+	str	r1, [r0, #0x034]			@ TIMINGROW_OFFSET
+	ldrne	r1, =0x182332c8
+	strne	r1, [r6, #0x034]			@ TIMINGROW_OFFSET
+
+	ldr	r1, =0x12130005
+	str	r1, [r0, #0x038]			@ TIMINGDATA_OFFSET
+	ldrne	r1, =0x13130005
+	strne	r1, [r6, #0x038]			@ TIMINGDATA_OFFSET
+
+	ldr	r1, =0x0E140222
+	str	r1, [r0, #0x03C]			@ TIMINGPOWER_OFFSET
+	ldrne	r1, =0x0E180222
+	strne	r1, [r6, #0x03C]			@ TIMINGPOWER_OFFSET
+
+	/* chip0 Deselect */
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 PALL */
+	ldr	r1, =0x01000000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 REFA */
+	ldr	r1, =0x05000000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+	/* chip0 REFA */
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 MRS */
+	ldr	r1, =0x00000032
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip0 EMRS */
+	ldr	r1, =0x00020020
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 Deselect */
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 PALL */
+	ldr	r1, =0x01100000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 REFA */
+	ldr	r1, =0x05100000
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+	/* chip1 REFA */
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 MRS */
+	ldr	r1, =0x00100032
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* chip1 EMRS */
+	ldr	r1, =0x00120020
+	str	r1, [r0, #0x010]			@ DIRECTCMD_OFFSET
+	strne	r1, [r6, #0x010]			@ DIRECTCMD_OFFSET
+
+	/* auto refresh on */
+	ldr	r1, =0xFF002030 | (1 << 7)
+	str	r1, [r0, #0x000]			@ CONCONTROL_OFFSET
+	strne	r1, [r6, #0x000]			@ CONCONTROL_OFFSET
+
+	/* PwrdnConfig */
+	ldr	r1, =0x00100002
+	str	r1, [r0, #0x028]			@ PWRDNCONFIG_OFFSET
+	strne	r1, [r6, #0x028]			@ PWRDNCONFIG_OFFSET
+
+	ldr	r1, =0x00212113
+	str	r1, [r0, #0x004]			@ MEMCONTROL_OFFSET
+	strne	r1, [r6, #0x004]			@ MEMCONTROL_OFFSET
+
+	/* Skip when S5PC110 */
+	bne	1f
+
+	/* Check OneDRAM access area at s5pc100 */
+	ldreq	r3, =0x38f80222
+	ldreq	r1, =0x37ffff00
+	str	r3, [r1]
+	ldr	r2, [r1]
+	cmp	r2, r3
+	beq	swap_memory
+1:
+	mov	pc, lr
+
+	.ltorg
diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c
new file mode 100644
index 0000000..8d3769b
--- /dev/null
+++ b/board/samsung/goni/onenand.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+#include <onenand_uboot.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+	this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+}
diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile
new file mode 100644
index 0000000..2446c2a
--- /dev/null
+++ b/board/ti/tnetv107xevm/Makefile
@@ -0,0 +1,49 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS		+= sdb_board.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+.PHONY: all
+
+all: $(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk
new file mode 100644
index 0000000..d24d49a
--- /dev/null
+++ b/board/ti/tnetv107xevm/config.mk
@@ -0,0 +1,20 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+TEXT_BASE = 0x83FC0000
diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c
new file mode 100644
index 0000000..3ed1cfd
--- /dev/null
+++ b/board/ti/tnetv107xevm/sdb_board.c
@@ -0,0 +1,149 @@
+/*
+ * TNETV107X-EVM: Board initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <linux/mtd/nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/arch/nand_defs.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
+	{			/* CS0 */
+		.mode		= ASYNC_EMIF_MODE_NAND,
+		.wr_setup	= 5,
+		.wr_strobe	= 5,
+		.wr_hold	= 2,
+		.rd_setup	= 5,
+		.rd_strobe	= 5,
+		.rd_hold	= 2,
+		.turn_around	= 5,
+		.width		= ASYNC_EMIF_8,
+	},
+	{			/* CS1 */
+		.mode		= ASYNC_EMIF_MODE_NOR,
+		.wr_setup	= 2,
+		.wr_strobe	= 27,
+		.wr_hold	= 4,
+		.rd_setup	= 2,
+		.rd_strobe	= 27,
+		.rd_hold	= 4,
+		.turn_around	= 2,
+		.width		= ASYNC_EMIF_PRESERVE,
+	},
+	{			/* CS2 */
+		.mode		= ASYNC_EMIF_MODE_NOR,
+		.wr_setup	= 2,
+		.wr_strobe	= 27,
+		.wr_hold	= 4,
+		.rd_setup	= 2,
+		.rd_strobe	= 27,
+		.rd_hold	= 4,
+		.turn_around	= 2,
+		.width		= ASYNC_EMIF_PRESERVE,
+	},
+	{			/* CS3 */
+		.mode		= ASYNC_EMIF_MODE_NOR,
+		.wr_setup	= 1,
+		.wr_strobe	= 90,
+		.wr_hold	= 3,
+		.rd_setup	= 1,
+		.rd_strobe	= 26,
+		.rd_hold	= 3,
+		.turn_around	= 1,
+		.width		= ASYNC_EMIF_8,
+	},
+};
+
+static struct pll_init_data pll_config[] = {
+	{
+		.pll			= ETH_PLL,
+		.internal_osc		= 1,
+		.pll_freq		= 500000000,
+		.div_freq = {
+			5000000, 50000000, 125000000, 250000000, 25000000,
+		},
+	},
+};
+
+static const short sdio1_pins[] = {
+	TNETV107X_PIN_SDIO1_CLK_1,	TNETV107X_PIN_SDIO1_CMD_1,
+	TNETV107X_PIN_SDIO1_DATA0_1,	TNETV107X_PIN_SDIO1_DATA1_1,
+	TNETV107X_PIN_SDIO1_DATA2_1,	TNETV107X_PIN_SDIO1_DATA3_1,
+	-1
+};
+
+static const short uart1_pins[] = {
+	TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
+};
+
+static const short ssp_pins[] = {
+	TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
+	TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
+	TNETV107X_PIN_SSP1_3, -1
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+	__raw_writel(0, INTC_GLB_EN);		/* Global disable       */
+	__raw_writel(0, INTC_HINT_EN);		/* Disable host ints    */
+	__raw_writel(0, INTC_EN_CLR0 + 0);	/* Clear enable         */
+	__raw_writel(0, INTC_EN_CLR0 + 4);	/* Clear enable         */
+	__raw_writel(0, INTC_EN_CLR0 + 8);	/* Clear enable         */
+#endif
+
+	gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	init_plls(ARRAY_SIZE(pll_config), pll_config);
+
+	init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
+
+	mux_select_pin(TNETV107X_PIN_ASR_CS3);
+	mux_select_pins(sdio1_pins);
+	mux_select_pins(uart1_pins);
+	mux_select_pins(ssp_pins);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+
+	return 0;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index e54673e..6efde75 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -227,6 +227,7 @@ KAREF		powerpc	ppc4xx		karef		sandburst
 grsim		sparc	leon3		-		gaisler
 imx31_litekit	arm	arm1136		-		logicpd		mx31
 omap2420h4	arm	arm1136		-		ti		omap24xx
+tnetv107x_evm	arm	arm1176		tnetv107xevm	ti		tnetv107x
 armadillo	arm	arm720t
 modnet50	arm	arm720t
 lpc2292sodimm	arm	arm720t		-		-		lpc2292
@@ -238,8 +239,13 @@ smdk2400	arm	arm920t		-		samsung		s3c24x0
 smdk2410	arm	arm920t		-		samsung		s3c24x0
 voiceblue	arm	arm925t
 omap1510inn	arm	arm925t		-		ti
-at91cap9adk	arm	arm926ejs	-		atmel		at91
 afeb9260	arm	arm926ejs	-		-		at91
+at91cap9adk	arm	arm926ejs	-		atmel		at91
+davinci_dvevm	arm	arm926ejs	dvevm		davinci		davinci
+davinci_sffsdr	arm	arm926ejs	sffsdr		davinci		davinci
+davinci_sonata	arm	arm926ejs	sonata		davinci		davinci
+da830evm	arm	arm926ejs	da8xxevm	davinci		davinci
+da850evm	arm	arm926ejs	da8xxevm	davinci		davinci
 guruplug	arm	arm926ejs	-		Marvell		kirkwood
 mv88f6281gtw_ge	arm	arm926ejs	-		Marvell		kirkwood
 openrd_base	arm	arm926ejs	-		Marvell		kirkwood
@@ -247,10 +253,11 @@ sheevaplug	arm	arm926ejs	-		Marvell		kirkwood
 imx27lite	arm	arm926ejs	imx27lite	logicpd		mx27
 magnesium	arm	arm926ejs	imx27lite	logicpd		mx27
 omap5912osk	arm	arm926ejs	-		ti		omap
-omap3_zoom1	arm	arm_cortexa8	zoom1		logicpd		omap3
-omap3_zoom2	arm	arm_cortexa8	zoom2		logicpd		omap3
+edminiv2	arm	arm926ejs	-		LaCie		orion5x
 omap3_overo	arm	arm_cortexa8	overo		-		omap3
 omap3_pandora	arm	arm_cortexa8	pandora		-		omap3
+omap3_zoom1	arm	arm_cortexa8	zoom1		logicpd		omap3
+omap3_zoom2	arm	arm_cortexa8	zoom2		logicpd		omap3
 omap3_beagle	arm	arm_cortexa8	beagle		ti		omap3
 omap3_evm	arm	arm_cortexa8	evm		ti		omap3
 omap3_sdp3430	arm	arm_cortexa8	sdp3430		ti		omap3
@@ -354,3 +361,8 @@ grsim_leon2	sparc	leon2		-		gaisler
 gr_cpci_ax2000	sparc	leon3		-		gaisler
 gr_ep2s60	sparc	leon3		-		gaisler
 gr_xc3s_1500	sparc	leon3		-		gaisler
+davinci_dm355evm arm	arm926ejs	dm355evm	davinci		davinci
+davinci_dm365evm arm	arm926ejs	dm365evm	davinci		davinci
+davinci_dm6467evm arm	arm926ejs	dm6467evm	davinci		davinci
+davinci_schmoogie arm	arm926ejs	schmoogie	davinci		davinci
+davinci_dm355leopard arm arm926ejs	dm355leopard	davinci		davinci
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 0439477..a1bcddc 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -96,7 +96,7 @@ void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
 		value |= PULL_MODE(gpio, mode);
 		break;
 	default:
-		return;
+		break;
 	}
 
 	writel(value, &bank->pull);
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 8eda95c..1073ac0 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -30,6 +30,9 @@
 #ifdef CONFIG_KIRKWOOD
 #include <asm/arch/kirkwood.h>
 #endif
+#ifdef CONFIG_ORION5X
+#include <asm/arch/orion5x.h>
+#endif
 
 #if defined (CONFIG_SERIAL_MULTI)
 #include <serial.h>
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 60ba007..08f837b 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -113,7 +113,8 @@ int spi_claim_bus(struct spi_slave *slave)
 	writel(0, &ds->regs->lvl);
 
 	/* enable SPI */
-	writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
+	writel((readl(&ds->regs->gcr1) |
+		SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
 
 	return 0;
 }
@@ -131,12 +132,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 {
 	struct davinci_spi_slave *ds = to_davinci_spi(slave);
 	unsigned int	len, data1_reg_val = readl(&ds->regs->dat1);
-	int		ret, i;
+	unsigned int	i_cnt = 0, o_cnt = 0, buf_reg_val;
 	const u8	*txp = dout; /* dout can be NULL for read operation */
 	u8		*rxp = din;  /* din can be NULL for write operation */
 
-	ret = 0;
-
 	if (bitlen == 0)
 		/* Finish any previously submitted transfers */
 		goto out;
@@ -159,41 +158,51 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 	readl(&ds->regs->buf);
 
 	/* keep writing and reading 1 byte until done */
-	for (i = 0; i < len; i++) {
-		/* wait till TXFULL is asserted */
-		while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK);
-
-		/* write the data */
-		data1_reg_val &= ~0xFFFF;
-		if (txp) {
-			data1_reg_val |= *txp;
-			txp++;
+	while ((i_cnt < len) || (o_cnt < len)) {
+		/* read RX buffer and flags */
+		buf_reg_val = readl(&ds->regs->buf);
+
+		/* if data is available */
+		if ((i_cnt < len) &&
+			(buf_reg_val & SPIBUF_RXEMPTY_MASK) == 0) {
+			/*
+			 * If there is no read buffer simply
+			 * ignore the read character
+			 */
+			if (rxp)
+				*rxp++ = buf_reg_val & 0xFF;
+			/* increment read words count */
+			i_cnt++;
 		}
 
 		/*
-		 * Write to DAT1 is required to keep the serial transfer going.
-		 * We just terminate when we reach the end.
+		 * if the tx buffer is empty and there
+		 * is still data to transmit
 		 */
-		if ((i == (len - 1)) && (flags & SPI_XFER_END)) {
-			/* clear CS hold */
-			writel(data1_reg_val &
-				~(1 << SPIDAT1_CSHOLD_SHIFT), &ds->regs->dat1);
-		} else {
-			/* enable CS hold */
-			data1_reg_val |= ((1 << SPIDAT1_CSHOLD_SHIFT) |
+		if ((o_cnt < len) &&
+			((buf_reg_val & SPIBUF_TXFULL_MASK) == 0)) {
+			/* write the data */
+			data1_reg_val &= ~0xFFFF;
+			if (txp)
+				data1_reg_val |= *txp++;
+			/*
+			 * Write to DAT1 is required to keep
+			 * the serial transfer going.
+			 * We just terminate when we reach the end.
+			 */
+			if ((o_cnt == (len - 1)) && (flags & SPI_XFER_END)) {
+				/* clear CS hold */
+				writel(data1_reg_val &
+						~(1 << SPIDAT1_CSHOLD_SHIFT),
+						&ds->regs->dat1);
+			} else {
+				/* enable CS hold and write TX register */
+				data1_reg_val |= ((1 << SPIDAT1_CSHOLD_SHIFT) |
 					(slave->cs << SPIDAT1_CSNR_SHIFT));
-			writel(data1_reg_val, &ds->regs->dat1);
-		}
-
-		/* read the data - wait for data availability */
-		while (readl(&ds->regs->buf) & SPIBUF_RXEMPTY_MASK);
-
-		if (rxp) {
-			*rxp = readl(&ds->regs->buf) & 0xFF;
-			rxp++;
-		} else {
-			/* simply drop the read character */
-			readl(&ds->regs->buf);
+				writel(data1_reg_val, &ds->regs->dat1);
+			}
+			/* increment written words count */
+			o_cnt++;
 		}
 	}
 	return 0;
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
new file mode 100644
index 0000000..513d005
--- /dev/null
+++ b/include/configs/am3517_evm.h
@@ -0,0 +1,296 @@
+/*
+ * am3517_evm.h - Default configuration for AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on omap3_evm_config.h
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR		1	/* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+#undef CONFIG_CMD_NET
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
new file mode 100644
index 0000000..357715d
--- /dev/null
+++ b/include/configs/da850evm.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* reserved for initial data */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		25000
+#define CONFIG_SYS_I2C_SLAVE		10 /* Bogus, master-only in U-Boot */
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"DA850-evm > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		\
+	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 7d1332f..1076de6 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
new file mode 100644
index 0000000..c3d95a0
--- /dev/null
+++ b/include/configs/edminiv2.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_EDMINIV2_H
+#define _CONFIG_EDMINIV2_H
+
+/*
+ * Version number information
+ */
+
+#define CONFIG_IDENT_STRING	" EDMiniV2"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MARVELL		1
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+#define CONFIG_FEROCEON		1	/* CPU Core subversion */
+#define CONFIG_ORION5X		1	/* SOC Family Name */
+#define CONFIG_88F5182		1	/* SOC Name */
+#define CONFIG_MACH_EDMINIV2	1	/* Machine type */
+
+/*
+ * CLKs configurations
+ */
+
+#define CONFIG_SYS_HZ		1000
+
+/*
+ * Board-specific values for Orion5x MPP low level init:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ *   MPP16 to MPP19, mode 0 for others
+ */
+
+#define ORION5X_MPP0_7		0x00000003
+#define ORION5X_MPP8_15		0x55550000
+#define ORION5X_MPP16_23	0x00000000
+
+/*
+ * Board-specific values for Orion5x GPIO low level init:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - Last GPIO is 26, further bits are supposed to be 0.
+ * Enable mask has ones for INPUT, 0 for OUTPUT.
+ * Default is LED ON.
+ */
+
+#define ORION5X_GPIO_OUT_ENABLE	0x03fcffff
+#define ORION5X_GPIO_OUT_VALUE	0x03fcffff
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
+
+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_MAX_FLASH_BANKS	1  /* max num of flash banks       */
+#define CONFIG_SYS_MAX_FLASH_SECT	11 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE		0xfff80000
+#define CONFIG_SYS_FLASH_SECTSZ \
+	{16384, 8192, 8192, 32768, \
+	 65536, 65536, 65536, 65536, 65536, 65536, 65536}
+
+/* auto boot */
+#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_PROMPT	"EDMiniV2> "	/* Command Prompt */
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
+/*
+ * Commands configuration - using default command set for now
+ */
+#include <config_cmd_default.h>
+/*
+ * Disabling some default commands for staggered bring-up
+ */
+#undef CONFIG_CMD_BOOTD	/* no bootd since no net */
+#undef CONFIG_CMD_NET	/* no net since no eth */
+#undef CONFIG_CMD_NFS	/* no NFS since no net */
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SECT_SIZE		0x2000	/* 16K */
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x4000	/* env starts here */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_STACKSIZE		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00800000
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x007fffff
+#define CONFIG_SYS_RESET_ADDRESS	0xffff0000
+#define CONFIG_SYS_MAXARGS		16
+
+#endif /* _CONFIG_EDMINIV2_H */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 08d79ac..e018b21 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -37,6 +37,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 0d99f7d..af7c65a 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_EVM	1	/* working with EVM */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
@@ -151,7 +153,7 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 
@@ -306,7 +308,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index a43500b..b441831 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -29,6 +29,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO	1	/* working with overo */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 945c053..9eba003 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -32,6 +32,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index b4919db..d4482d3 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index ae7ebf9..1e88dc0 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index c88c732..be9daf4 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -39,6 +39,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */
 
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
new file mode 100644
index 0000000..690f119
--- /dev/null
+++ b/include/configs/pm9g45.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the PM9G45 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core */
+#define CONFIG_PM9G45		1	/* It's an Ronetix PM9G45 */
+#define CONFIG_AT91SAM9G45	1	/* It's an Atmel AT91SAM9G45 SoC */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO	1
+#define CONFIG_ATMEL_USART	1
+#define CONFIG_USART3		1	/* USART 3 is DBGU */
+
+#define CONFIG_SYS_USE_NANDFLASH	1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define	CONFIG_RED_LED		AT91_PIO_PORTD, 31 /* this is the user1 led */
+#define	CONFIG_GREEN_LED	AT91_PIO_PORTD, 0 /* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+#define CONFIG_CMD_JFFS2		1
+#define CONFIG_JFFS2_CMDLINE		1
+#define CONFIG_JFFS2_NAND		1
+#define CONFIG_JFFS2_DEV		"nand0" /* NAND dev jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition */
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x70000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 megs */
+
+/* NOR flash, not available */
+#define CONFIG_SYS_NO_FLASH		1
+#undef CONFIG_CMD_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MAX_CHIPS		1
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 3
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_MULTI		1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00700000 /* _UHP_OHCI_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE	PHYS_SDRAM + 0xE00000
+
+#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM + 0x2000000 /* load addr */
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		CONFIG_AT91SAM9G45_LCD_BASE
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"fbcon=rotate:3 console=tty0 " \
+				"console=ttyS0,115200 " \
+				"root=/dev/mtdblock4 " \
+				"mtdparts=atmel_nand:128k(bootstrap)ro," \
+				"256k(uboot)ro,1664k(env)," \
+				"2M(linux)ro,-(root) rw " \
+				"rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
+					0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE		(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
new file mode 100644
index 0000000..171ec94
--- /dev/null
+++ b/include/configs/s5p_goni.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG Universal (s5pc100) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5PC1XX		1	/* which is in a S5PC1XX Family */
+#define CONFIG_S5PC110		1	/* which is in a S5PC110 */
+#define CONFIG_MACH_GONI	1	/* working with Goni */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/* input clock of PLL: has 24MHz input clock at S5PC110 */
+#define CONFIG_SYS_CLK_FREQ_C110	24000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for */
+						/* initial data */
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL2			1	/* use SERIAL2 */
+#define CONFIG_SERIAL_MULTI		1
+#define CONFIG_BAUDRATE			115200
+
+/* It should define before config_cmd_default.h */
+#define CONFIG_SYS_NO_FLASH		1
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
+#define MTDIDS_DEFAULT		"onenand0=samsung-onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=samsung-onenand:1m(bootloader)"\
+				",256k(params)"\
+				",2816k(config)"\
+				",8m(csa)"\
+				",7m(kernel)"\
+				",1m(log)"\
+				",12m(modem)"\
+				",60m(qboot)"\
+				",-(UBI)\0"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC2,115200n8\0"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext2" \
+		" ${console} ${meminfo}"
+
+#define CONFIG_COMMON_BOOT	"${console} ${meminfo} ${mtdparts}"
+
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \
+		" rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x100000;" \
+			" onenand write 0x32008000 0x0 0x100000\0"
+
+#define CONFIG_UBI_MTD	" ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6"
+
+#define CONFIG_UBIFS_OPTION	"rootflags=bulk_read,no_chk_data_crc"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0xc00000 0x600000;" \
+		"onenand write 0x31008000 0xc00000 0x600000\0" \
+	"updateu=" \
+		"onenand erase 0x01560000 0x1eaa0000;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"onenand read 0x30007FC0 0xc00000 0x600000;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock} " \
+		"rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \
+		"${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; run bootk\0" \
+	"tftpboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \
+		"bootm 0x30007FC0\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		" initrd=0x33000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"set bootargs root=${mmcblk} rootfstype=${rootfstype}" \
+		CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+	"verify=n\0" \
+	"rootfstype=cramfs\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"mtdparts=" MTDPARTS_DEFAULT \
+	"meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
+	"mmcblk=/dev/mmcblk1p1\0" \
+	"bootblock=9\0" \
+	"ubiblock=8\0" \
+	"ubi=enabled\0" \
+	"opts=always_resume=1"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT	"Goni # "
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4000000)
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE	(256 << 10)	/* 256 KiB */
+
+/* Goni has 3 banks of DRAM, but swap the bank */
+#define CONFIG_NR_DRAM_BANKS	3
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* OneDRAM Bank #0 */
+#define PHYS_SDRAM_1_SIZE	(80 << 20)		/* 80 MB in Bank #0 */
+#define PHYS_SDRAM_2		0x40000000		/* mDDR DMC1 Bank #1 */
+#define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in Bank #1 */
+#define PHYS_SDRAM_3		0x50000000		/* mDDR DMC2 Bank #2 */
+#define PHYS_SDRAM_3_SIZE	(128 << 20)		/* 128 MB in Bank #2 */
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(256 << 10)	/* 256 KiB, 0x40000 */
+#define CONFIG_ENV_ADDR			(1 << 20)	/* 1 MB, 0x100000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xB0000000
+
+#define CONFIG_DOS_PARTITION		1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index f04feae..624fe04 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -40,6 +40,12 @@
 #define CONFIG_S3C64XX		1	/* in a SAMSUNG S3C64XX Family  */
 #define CONFIG_SMDK6400		1	/* on a SAMSUNG SMDK6400 Board  */
 
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_PERIPORT_REMAP
+#define CONFIG_PERIPORT_BASE	0x70000000
+#define CONFIG_PERIPORT_SIZE	0x13
+
 #define CONFIG_SYS_SDRAM_BASE	0x50000000
 
 /* input clock of PLL: SMDK6400 has 12MHz input clock */
@@ -61,8 +67,6 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
 /*
  * Size of malloc() pool
  */
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
new file mode 100644
index 0000000..454e9b2
--- /dev/null
+++ b/include/configs/tnetv107x_evm.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+
+/* Architecture, CPU, etc */
+#define CONFIG_ARM1176
+#define CONFIG_TNETV107X
+#define CONFIG_TNETV107X_EVM
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_UBOOT_BASE		TEXT_BASE
+#define CONFIG_DISABLE_TCM
+#define CONFIG_PERIPORT_REMAP
+#define CONFIG_PERIPORT_BASE		0x2000000
+#define CONFIG_PERIPORT_SIZE		0x10
+#define CONFIG_SYS_CLK_FREQ		clk_get_rate(TNETV107X_LPSC_ARM)
+
+#define CONFIG_SYS_TIMERBASE		TNETV107X_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get_rate(TNETV107X_LPSC_TIMER0)
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_PLL_SYS_EXT_FREQ		25000000
+#define CONFIG_PLL_TDM_EXT_FREQ		19200000
+#define CONFIG_PLL_ETH_EXT_FREQ		25000000
+
+/* Memory Info */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 1*1024*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define PHYS_SDRAM_1			TNETV107X_DDR_EMIF_DATA_BASE
+#define PHYS_SDRAM_1_SIZE		0x04000000
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 16*1024*1024)
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_STACKSIZE		(256*1024)
+
+/* Serial Driver Info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		TNETV107X_UART1_BASE
+#define CONFIG_SYS_NS16550_CLK		clk_get_rate(TNETV107X_LPSC_UART1)
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Flash and environment info */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE			(SZ_128K)
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_1BIT_ECC
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BASE		TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
+#define CONFIG_SYS_CLE_MASK		0x10
+#define CONFIG_SYS_ALE_MASK		0x8
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_JFFS2_NAND
+#define NAND_MAX_CHIPS			1
+#define CONFIG_ENV_OFFSET		0x180000
+#define DEF_BOOTM			""
+
+/*
+ * davinci_nand is a bit of a misnomer since this particular EMIF block is
+ * commonly used across multiple TI devices.  Unfortunately, this misnomer
+ * (amongst others) carries forward into the kernel too.  Consequently, if we
+ * use a different device name here, the mtdparts variable won't be usable as
+ * a kernel command-line argument.
+ */
+#define MTDIDS_DEFAULT			"nand0=davinci_nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=davinci_nand.0:"	\
+						"1536k(uboot)ro,"	\
+						"128k(params)ro,"	\
+						"4m(kernel),"		\
+						"-(filesystem)"
+
+/* General U-Boot configuration */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_SYS_PROMPT		"U-Boot > "
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_MEMTEST_START +	\
+					 0x700000)
+#define LINUX_BOOT_PARAM_ADDR		(CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS			"mem=32M console=ttyS1,115200n8 " \
+					"root=/dev/mmcblk0p1 rw noinitrd"
+#define CONFIG_BOOTCOMMAND		""
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_JFFS2
+
+#endif /* __CONFIG_H */