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| author | John Schmoller <jschmoller@xes-inc.com> | 2010-12-02 11:43:10 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-12-13 09:32:15 -0600 |
| commit | 9fd84915a92058b775fcc8fad4ab4e59fe51cf17 (patch) | |
| tree | 4c08894e72fa0a94d71365391ac9d8db226795f6 | |
| parent | 72c96a6802d9b1c949785d1d152f8bc8666c753d (diff) | |
| download | u-boot-imx-9fd84915a92058b775fcc8fad4ab4e59fe51cf17.zip u-boot-imx-9fd84915a92058b775fcc8fad4ab4e59fe51cf17.tar.gz u-boot-imx-9fd84915a92058b775fcc8fad4ab4e59fe51cf17.tar.bz2 | |
fsl_upm: Add MxMR/MDR synchronization
According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):
"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."
The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | drivers/mtd/nand/fsl_upm.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c index 7cb99cb..c33e278 100644 --- a/drivers/mtd/nand/fsl_upm.c +++ b/drivers/mtd/nand/fsl_upm.c @@ -21,6 +21,7 @@ static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) { clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); + (void)in_be32(upm->mxmr); } static void fsl_upm_end_pattern(struct fsl_upm *upm) @@ -35,6 +36,7 @@ static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, void __iomem *io_addr, u32 mar) { out_be32(upm->mar, mar); + (void)in_be32(upm->mar); switch (width) { case 8: out_8(io_addr, 0x0); |