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| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2010-06-23 19:32:28 +0530 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-06-29 21:01:07 +0200 |
| commit | d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a (patch) | |
| tree | 4a029912084daeb20457c7007cbeec4af881d498 | |
| parent | cdc6363f423900645265563d705a0a5a964ae40c (diff) | |
| download | u-boot-imx-d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a.zip u-boot-imx-d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a.tar.gz u-boot-imx-d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a.tar.bz2 | |
85xx/p1_p2_rdb: Modify the CLK_CTRL value for DDR at 667MHz
Use a slighly larger value of CLK_CTRL for DDR at 667MHz
which fixes random crashes while linux booting.
Applicable for both NAND and NOR boot.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index fccc4f8..15b46b0 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -76,7 +76,7 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 #define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 #define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000 +#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 #define CONFIG_SYS_DDR_MODE_1_667 0x00040852 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 |