Patch by Vincent Dubey, 24 Sep 2004:

Add support for xaeniax board

10 files changed, 1603 insertions, 1 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 1d4a093..077e208 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Patch by Vincent Dubey, 24 Sep 2004:
+  Add support for xaeniax board
+
 * Add comment about non-GPL character of standalone applications to
   COPYING file
 
diff --git a/MAKEALL b/MAKEALL
index 131dc37..6d96dcb 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -149,7 +149,11 @@ LIST_ARM9="	\
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="cerf250 cradle csb226 innokom lubbock wepep250 xm250 xsengine"
+LIST_pxa="	\
+	cerf250		cradle		csb226		innokom		\
+	lubbock		wepep250	xaeniax		xm250		\
+	xsengine							\
+"
 
 LIST_ixp="ixdp425"
 
diff --git a/Makefile b/Makefile
index c693b6a..963bf58 100644
--- a/Makefile
+++ b/Makefile
@@ -1316,6 +1316,9 @@ logodl_config	:	unconfig
 wepep250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa wepep250
 
+xaeniax_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa xaeniax
+
 xm250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xm250
 
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
new file mode 100644
index 0000000..da5a5ba
--- /dev/null
+++ b/board/xaeniax/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= xaeniax.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/xaeniax/config.mk b/board/xaeniax/config.mk
new file mode 100644
index 0000000..45079a0
--- /dev/null
+++ b/board/xaeniax/config.mk
@@ -0,0 +1,2 @@
+TEXT_BASE = 0xa3FB0000
+#TEXT_BASE = 0
diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c
new file mode 100644
index 0000000..9874a14
--- /dev/null
+++ b/board/xaeniax/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW    FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/xaeniax/memsetup.S b/board/xaeniax/memsetup.S
new file mode 100644
index 0000000..5c43b85
--- /dev/null
+++ b/board/xaeniax/memsetup.S
@@ -0,0 +1,424 @@
+ /*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/memsetup.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc  p15,0,\reg,c2,c0,0
+	mov  \reg,\reg
+	sub  pc,pc,#4
+	.endm
+
+
+.globl memsetup
+memsetup:
+
+	mov	 r10, lr
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr	r0,=GPSR0
+	ldr	r1,=CFG_GPSR0_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPSR1
+	ldr	r1,=CFG_GPSR1_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPSR2
+	ldr	r1,=CFG_GPSR2_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPCR0
+	ldr	r1,=CFG_GPCR0_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPCR1
+	ldr	r1,=CFG_GPCR1_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPCR2
+	ldr	r1,=CFG_GPCR2_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPDR0
+	ldr	r1,=CFG_GPDR0_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPDR1
+	ldr	r1,=CFG_GPDR1_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPDR2
+	ldr	r1,=CFG_GPDR2_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR0_L
+	ldr	r1,=CFG_GAFR0_L_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR0_U
+	ldr	r1,=CFG_GAFR0_U_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR1_L
+	ldr	r1,=CFG_GAFR1_L_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR1_U
+	ldr	r1,=CFG_GAFR1_U_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR2_L
+	ldr	r1,=CFG_GAFR2_L_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR2_U
+	ldr	r1,=CFG_GAFR2_U_VAL
+	str	r1,[r0]
+
+	ldr	r0,=PSSR		/* enable GPIO pins */
+	ldr	r1,=CFG_PSSR_VAL
+	str	r1,[r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+mem_init:
+
+	ldr	r1,=MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr     r2,=CFG_MSC0_VAL
+	str     r2,[r1, #MSC0_OFFSET]
+	ldr     r2,[r1, #MSC0_OFFSET]	/* read back to ensure data latches */
+
+	/* MSC1: nCS(2,3)                                                   */
+	ldr     r2,=CFG_MSC1_VAL
+	str     r2,[r1, #MSC1_OFFSET]
+	ldr     r2,[r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr     r2,=CFG_MSC2_VAL
+	str     r2,[r1, #MSC2_OFFSET]
+	ldr     r2,[r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr     r2,=CFG_MECR_VAL
+	str     r2,[r1, #MECR_OFFSET]
+	ldr	r2,[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr     r2,=CFG_MCMEM0_VAL
+	str     r2,[r1, #MCMEM0_OFFSET]
+	ldr	r2,[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr     r2,=CFG_MCMEM1_VAL
+	str     r2,[r1, #MCMEM1_OFFSET]
+	ldr	r2,[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr     r2,=CFG_MCATT0_VAL
+	str     r2,[r1, #MCATT0_OFFSET]
+	ldr	r2,[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr     r2,=CFG_MCATT1_VAL
+	str     r2,[r1, #MCATT1_OFFSET]
+	ldr	r2,[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr     r2,=CFG_MCIO0_VAL
+	str     r2,[r1, #MCIO0_OFFSET]
+	ldr	r2,[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr     r2,=CFG_MCIO1_VAL
+	str     r2,[r1, #MCIO1_OFFSET]
+	ldr	r2,[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	@ get the mdrefr settings
+	ldr     r4,=CFG_MDREFR_VAL
+
+	@ write back mdrefr
+	str     r4,[r1, #MDREFR_OFFSET]
+	ldr     r4,[r1, #MDREFR_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	@ set K1RUN for bank 0
+	@
+	orr   r4,  r4,  #MDREFR_K1RUN
+
+	@ write back mdrefr
+	@
+	str     r4,  [r1, #MDREFR_OFFSET]
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic     r4,  r4,  #MDREFR_SLFRSH
+
+	@ write back mdrefr
+	@
+	str     r4,  [r1, #MDREFR_OFFSET]
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@ if E0PIN is also used:	 #(MDREFR_E1PIN|MDREFR_E0PIN)
+	orr     r4,  r4, #(MDREFR_E1PIN)
+
+	@ write back mdrefr
+	@
+	str     r4,  [r1, #MDREFR_OFFSET]
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+
+	/* Step 4d:							*/
+	/* fetch platform value of mdcnfg				*/
+	@
+	ldr     r2,  =CFG_MDCNFG_VAL
+
+	@ disable all sdram banks
+	@
+	bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+	bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+	@ program banks 0/1 for bus width
+	@
+	bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
+
+	@ write initial value of mdcnfg, w/o enabling sdram banks
+	@
+	str     r2,  [r1, #MDCNFG_OFFSET]
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/* get memory controller base address                               */
+	ldr     r1,  =MEMC_BASE
+
+	@fetch current mdcnfg value
+	@
+	ldr     r3,  [r1, #MDCNFG_OFFSET]
+
+	@enable sdram bank 0 if installed (must do for any populated bank)
+	@
+	orr     r3,  r3,  #MDCNFG_DE0
+
+	@write back mdcnfg, enabling the sdram bank(s)
+	@
+	str     r3,  [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2,	=CFG_MDMRS_VAL
+	str     r2,	[r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2,  =ICLR
+	str     r1,  [r2]
+
+	ldr     r1,  =CFG_ICMR_VAL /* mask all interrupts at the controller */
+	ldr     r2,  =ICMR
+	str     r1,  [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1,  =CKEN
+	mov     r2,  #0
+	str     r2,  [r1]
+
+
+	/* default value						    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1,  =CCCR
+	str     r2,  [r1]
+
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
+	ldr     r1,  =OSCC
+	mov     r2,  #OSCC_OON
+	str     r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+#endif
+
+	@ Turn on needed clocks
+	@
+test:
+	ldr     r1,  =CKEN
+	ldr     r2,  =CFG_CKEN_VAL
+	str     r2,  [r1]
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size ?*/
+	ldr	r1, =DRAM_SIZE
+	str	r8, [r1]
+
+	/* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End memsetup                                                     */
+	/* ---------------------------------------------------------------- */
+
+endmemsetup:
+
+	mov     pc, lr
diff --git a/board/xaeniax/u-boot.lds b/board/xaeniax/u-boot.lds
new file mode 100644
index 0000000..58c371d
--- /dev/null
+++ b/board/xaeniax/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
new file mode 100644
index 0000000..26fb312
--- /dev/null
+++ b/board/xaeniax/xaeniax.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2004
+ * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of xaeniax */
+	gd->bd->bi_arch_number = 585;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	/*	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
+	/*	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
+	/*	gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
+	/*	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
+	/*	gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
+	/*	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
+
+	return 0;
+}
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
new file mode 100644
index 0000000..569788a
--- /dev/null
+++ b/include/configs/xaeniax.h
@@ -0,0 +1,555 @@
+/*
+ * (C) Copyright 2004
+ * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the xaeniax board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL		/* undef for developing */
+
+/*
+#undef CONFIG_INIT_CRITICAL
+*/
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
+#define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
+
+
+#define BOARD_LATE_INIT		1
+
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_DIAG | CFG_CMD_SDRAM & ~CONFIG_CMD_DTT)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.68.201
+#define CONFIG_SERVERIP		192.168.68.62
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND	"bootm 0x00100000"
+#define CONFIG_BOOTARGS		"console=ttyS1,115200"
+#define CONFIG_CMDLINE_TAG1				/* enable passing of ATAGs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1			/* which serial port to use */
+#endif
+
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are
+ * used for the RAM copy of the uboot code
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory	*/
+#define CFG_HUSH_PARSER		1
+
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks (partition) of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* FIXME */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x40000			/* Total Size of Environment Sector	*/
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * SMSC91C111 Network Card
+ */
+#define CONFIG_DRIVER_SMC91111		1
+#define CONFIG_SMC91111_BASE		0x0C00030  /* chip select 3         */
+#define CONFIG_SMC_USE_32_BIT		1          /* 32 bit bus  */
+#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
+#undef  CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
+
+/*
+ * GPIO settings
+ */
+
+/*
+ * GP05 == nUSBReset  is 1
+ * GP10 == CFReset   is 1
+ * GP13 == nCFDataEnable is 1
+ * GP14 == nCFAddrEnable is 1
+ * GP15 == nCS1      is 1
+ * GP21 == ComBrdReset is 1
+ * GP24 == SFRM      is 1
+ * GP25 == TXD       is 1
+ * GP31 == SYNC      is 1
+ * GP33 == nCS5      is 1
+ * GP39 == FFTXD     is 1
+ * GP41 == RTS       is 1
+ * GP43 == BTTXD     is 1
+ * GP45 == BTRTS     is 1
+ * GP47 == TXD       is 1
+ * GP48 == nPOE      is 1
+ * GP49 == nPWE      is 1
+ * GP50 == nPIOR     is 1
+ * GP51 == nPIOW     is 1
+ * GP52 == nPCE[1]   is 1
+ * GP53 == nPCE[2]   is 1
+ * GP54 == nPSKTSEL  is 1
+ * GP55 == nPREG     is 1
+ * GP78 == nCS2      is 1
+ * GP79 == nCS3      is 1
+ * GP80 == nCS4      is 1
+ * GP82 == NSSPSFRM  is 1
+ * GP83 == NSSPTXD   is 1
+ */
+#define CFG_GPSR0_VAL		0x8320E420
+#define CFG_GPSR1_VAL		0x00FFAA82
+#define CFG_GPSR2_VAL		0x000DC000
+
+/*
+ * GP03 == LANReset  is 0
+ * GP06 == USBWakeUp  is 0
+ * GP11 == USBControl is 0
+ * GP12 == Buzzer     is 0
+ * GP16 == PWM0       is 0
+ * GP17 == PWM1       is 0
+ * GP23 == SCLK      is 0
+ * GP30 == SDATA_OUT is 0
+ * GP81 == NSSPCLK   is 0
+ */
+#define CFG_GPCR0_VAL		0x40C31868
+#define CFG_GPCR1_VAL		0x00000000
+#define CFG_GPCR2_VAL		0x00020000
+
+/*
+ * GP00 == CPUWakeUpUSB is input
+ * GP01 == GP reset is input
+ * GP02 == LANInterrupt is input
+ * GP03 == LANReset     is output
+ * GP04 == USBInterrupt is input
+ * GP05 == nUSBReset    is output
+ * GP06 == USBWakeUp    is output
+ * GP07 == CFReady/nBusy is input
+ * GP08 == nCFCardDetect1 is input
+ * GP09 == nCFCardDetect2 is input
+ * GP10 == nCFReset   is output
+ * GP11 == USBControl is output
+ * GP12 == Buzzer     is output
+ * GP13 == CFDataEnable is output
+ * GP14 == CFAddressEnable is output
+ * GP15 == nCS1      is output
+ * GP16 == PWM0      is output
+ * GP17 == PWM1      is output
+ * GP18 == RDY       is input
+ * GP19 == ReaderReady is input
+ * GP20 == ReaderReset is input
+ * GP21 == ComBrdReset is output
+ * GP23 == SCLK      is output
+ * GP24 == SFRM      is output
+ * GP25 == TXD       is output
+ * GP26 == RXD       is input
+ * GP27 == EXTCLK    is input
+ * GP28 == BITCLK    is output
+ * GP29 == SDATA_IN0 is input
+ * GP30 == SDATA_OUT is output
+ * GP31 == SYNC      is output
+ * GP32 == SYSSCLK   is output
+ * GP33 == nCS5      is output
+ * GP34 == FFRXD     is input
+ * GP35 == CTS       is input
+ * GP36 == DCD       is input
+ * GP37 == DSR       is input
+ * GP38 == RI        is input
+ * GP39 == FFTXD     is output
+ * GP40 == DTR       is output
+ * GP41 == RTS       is output
+ * GP42 == BTRXD     is input
+ * GP43 == BTTXD     is output
+ * GP44 == BTCTS     is input
+ * GP45 == BTRTS     is output
+ * GP46 == RXD       is input
+ * GP47 == TXD       is output
+ * GP48 == nPOE      is output
+ * GP49 == nPWE      is output
+ * GP50 == nPIOR     is output
+ * GP51 == nPIOW     is output
+ * GP52 == nPCE[1]   is output
+ * GP53 == nPCE[2]   is output
+ * GP54 == nPSKTSEL  is output
+ * GP55 == nPREG     is output
+ * GP56 == nPWAIT    is input
+ * GP57 == nPIOS16   is input
+ * GP58 == LDD[0]    is output
+ * GP59 == LDD[1]    is output
+ * GP60 == LDD[2]    is output
+ * GP61 == LDD[3]    is output
+ * GP62 == LDD[4]    is output
+ * GP63 == LDD[5]    is output
+ * GP64 == LDD[6]    is output
+ * GP65 == LDD[7]    is output
+ * GP66 == LDD[8]    is output
+ * GP67 == LDD[9]    is output
+ * GP68 == LDD[10]   is output
+ * GP69 == LDD[11]   is output
+ * GP70 == LDD[12]   is output
+ * GP71 == LDD[13]   is output
+ * GP72 == LDD[14]   is output
+ * GP73 == LDD[15]   is output
+ * GP74 == LCD_FCLK  is output
+ * GP75 == LCD_LCLK  is output
+ * GP76 == LCD_PCLK  is output
+ * GP77 == LCD_ACBIAS is output
+ * GP78 == nCS2      is output
+ * GP79 == nCS3      is output
+ * GP80 == nCS4      is output
+ * GP81 == NSSPCLK   is output
+ * GP82 == NSSPSFRM  is output
+ * GP83 == NSSPTXD   is output
+ * GP84 == NSSPRXD   is input
+ */
+#define CFG_GPDR0_VAL		0xD3E3FC68
+#define CFG_GPDR1_VAL		0xFCFFAB83
+#define CFG_GPDR2_VAL		0x000FFFFF
+
+/*
+ * GP01 == GP reset is AF01
+ * GP15 == nCS1     is AF10
+ * GP16 == PWM0     is AF10
+ * GP17 == PWM1     is AF10
+ * GP18 == RDY      is AF01
+ * GP23 == SCLK     is AF10
+ * GP24 == SFRM     is AF10
+ * GP25 == TXD      is AF10
+ * GP26 == RXD      is AF01
+ * GP27 == EXTCLK   is AF01
+ * GP28 == BITCLK   is AF01
+ * GP29 == SDATA_IN0 is AF10
+ * GP30 == SDATA_OUT is AF01
+ * GP31 == SYNC     is AF01
+ * GP32 == SYSCLK   is AF01
+ * GP33 == nCS5  is AF10
+ * GP34 == FFRXD is AF01
+ * GP35 == CTS   is AF01
+ * GP36 == DCD   is AF01
+ * GP37 == DSR   is AF01
+ * GP38 == RI    is AF01
+ * GP39 == FFTXD is AF10
+ * GP40 == DTR   is AF10
+ * GP41 == RTS   is AF10
+ * GP42 == BTRXD is AF01
+ * GP43 == BTTXD is AF10
+ * GP44 == BTCTS is AF01
+ * GP45 == BTRTS is AF10
+ * GP46 == RXD   is AF10
+ * GP47 == TXD   is AF01
+ * GP48 == nPOE  is AF10
+ * GP49 == nPWE  is AF10
+ * GP50 == nPIOR is AF10
+ * GP51 == nPIOW is AF10
+ * GP52 == nPCE[1] is AF10
+ * GP53 == nPCE[2] is AF10
+ * GP54 == nPSKTSEL is AF10
+ * GP55 == nPREG   is AF10
+ * GP56 == nPWAIT  is AF01
+ * GP57 == nPIOS16 is AF01
+ * GP58 == LDD[0]  is AF10
+ * GP59 == LDD[1]  is AF10
+ * GP60 == LDD[2]  is AF10
+ * GP61 == LDD[3]  is AF10
+ * GP62 == LDD[4]  is AF10
+ * GP63 == LDD[5]  is AF10
+ * GP64 == LDD[6]  is AF10
+ * GP65 == LDD[7]  is AF10
+ * GP66 == LDD[8]  is AF10
+ * GP67 == LDD[9]  is AF10
+ * GP68 == LDD[10] is AF10
+ * GP69 == LDD[11] is AF10
+ * GP70 == LDD[12] is AF10
+ * GP71 == LDD[13] is AF10
+ * GP72 == LDD[14] is AF10
+ * GP73 == LDD[15] is AF10
+ * GP74 == LCD_FCLK is AF10
+ * GP75 == LCD_LCLK is AF10
+ * GP76 == LCD_PCLK is AF10
+ * GP77 == LCD_ACBIAS is AF10
+ * GP78 == nCS2     is AF10
+ * GP79 == nCS3     is AF10
+ * GP80 == nCS4     is AF10
+ * GP81 == NSSPCLK  is AF01
+ * GP82 == NSSPSFRM is AF01
+ * GP83 == NSSPTXD  is AF01
+ * GP84 == NSSPRXD  is AF10
+ */
+#define CFG_GAFR0_L_VAL		0x80000004
+#define CFG_GAFR0_U_VAL		0x595A801A
+#define CFG_GAFR1_L_VAL		0x699A9559
+#define CFG_GAFR1_U_VAL		0xAAA5AAAA
+#define CFG_GAFR2_L_VAL		0xAAAAAAAA
+#define CFG_GAFR2_U_VAL		0x00000256
+
+/*
+ * clock settings
+ */
+/* RDH = 1
+ * PH  = 0
+ * VFS = 0
+ * BFS = 0
+ * SSS = 0
+ */
+#define CFG_PSSR_VAL		0x00000030
+
+#define CFG_CKEN_VAL            0x00000080  /*  */
+#define CFG_ICMR_VAL            0x00000000  /* No interrupts enabled        */
+
+
+/*
+ * Memory settings
+ *
+ * This is the configuration for nCS0/1 -> flash banks
+ * configuration for nCS1 :
+ * [31]    0    -
+ * [30:28] 000  -
+ * [27:24] 0000 -
+ * [23:20] 0000 -
+ * [19]    0    -
+ * [18:16] 000  -
+ * configuration for nCS0:
+ * [15]    0    - Slower Device
+ * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
+ * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 010  - burst OF 4 ROM or FLASH
+*/
+#define CFG_MSC0_VAL		0x000023D2
+
+/* This is the configuration for nCS2/3 -> USB controller, LAN
+ * configuration for nCS3: LAN
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
+ * [19]    0    - 32 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS2: USB
+ * [15]    1    - Faster Device
+ * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC1_VAL		0x1224A264
+
+/* This is the configuration for nCS4/5 -> LAN
+ * configuration for nCS5:
+ * [31]    0    -
+ * [30:28] 000  -
+ * [27:24] 0000 -
+ * [23:20] 0000 -
+ * [19]    0    -
+ * [18:16] 000  -
+ * configuration for nCS4: LAN
+ * [15]    1    - Faster Device
+ * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC2_VAL		0x00001224
+
+/* MDCNFG: SDRAM Configuration Register
+ *
+ * [31:29]   000 - reserved
+ * [28]      0	 - no SA1111 compatiblity mode
+ * [27]      0   - latch return data with return clock
+ * [26]      0   - alternate addressing for pair 2/3
+ * [25:24]   00  - timings
+ * [23]      0   - internal banks in lower partition 2/3 (not used)
+ * [22:21]   00  - row address bits for partition 2/3 (not used)
+ * [20:19]   00  - column address bits for partition 2/3 (not used)
+ * [18]      0   - SDRAM partition 2/3 width is 32 bit
+ * [17]      0   - SDRAM partition 3 disabled
+ * [16]      0   - SDRAM partition 2 disabled
+ * [15:13]   000 - reserved
+ * [12]      0	 - no SA1111 compatiblity mode
+ * [11]      1   - latch return data with return clock
+ * [10]      0   - no alternate addressing for pair 0/1
+ * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
+ * [7]       1   - 4 internal banks in lower partition pair
+ * [06:05]   10  - 13 row address bits for partition 0/1
+ * [04:03]   01  - 9 column address bits for partition 0/1
+ * [02]      0   - SDRAM partition 0/1 width is 32 bit
+ * [01]      0   - disable SDRAM partition 1
+ * [00]      1   - enable  SDRAM partition 0
+ */
+/* use the configuration above but disable partition 0 */
+#define CFG_MDCNFG_VAL		0x00000AC9
+
+/* MDREFR: SDRAM Refresh Control Register
+ *
+ * [32:26] 0     - reserved
+ * [25]    0     - K2FREE: not free running
+ * [24]    0     - K1FREE: not free running
+ * [23]    0     - K0FREE: not free running
+ * [22]    0     - SLFRSH: self refresh disabled
+ * [21]    0     - reserved
+ * [20]    1     - APD: auto power down
+ * [19]    0     - K2DB2: SDCLK2 is MemClk
+ * [18]    0     - K2RUN: disable SDCLK2
+ * [17]    0     - K1DB2: SDCLK1 is MemClk
+ * [16]    1     - K1RUN: enable SDCLK1
+ * [15]    1     - E1PIN: SDRAM clock enable
+ * [14]    0     - K0DB2: SDCLK0 is MemClk
+ * [13]    0     - K0RUN: disable SDCLK0
+ * [12]    0     - E0PIN: disable SDCKE0
+ * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
+ */
+#define CFG_MDREFR_VAL		0x00138018 /* mh: was 0x00118018 */
+
+/* MDMRS: Mode Register Set Configuration Register
+ *
+ * [31]      0       - reserved
+ * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
+ * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
+ * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
+ * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
+ * [15]      0       - reserved
+ * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
+ * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
+ * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
+ * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
+ */
+#define CFG_MDMRS_VAL		0x00320032
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000000
+#define CFG_MCMEM0_VAL		0x00010504
+#define CFG_MCMEM1_VAL		0x00010504
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00010504
+#define CFG_MCIO0_VAL		0x00004715
+#define CFG_MCIO1_VAL		0x00004715
+
+
+#endif	/* __CONFIG_H */