Phytec Phycore-i.MX31 support

This patch adds support for the Phytec Phycore-i.MX31 board

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

8 files changed, 481 insertions, 0 deletions

diff --git a/MAKEALL b/MAKEALL
index 1eabcc7..f7b5fdb 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -504,6 +504,7 @@ LIST_ARM11="		\
 	omap2420h4	\
 	apollon		\
 	imx31_litekit	\
+	imx31_phycore	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 9c29241..9fa8b63 100644
--- a/Makefile
+++ b/Makefile
@@ -2601,6 +2601,9 @@ apollon_config		: unconfig
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
+imx31_phycore_config	: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+
 #========================================================================
 # i386
 #========================================================================
diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile
new file mode 100644
index 0000000..de37cca
--- /dev/null
+++ b/board/imx31_phycore/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= imx31_phycore.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/imx31_phycore/config.mk b/board/imx31_phycore/config.mk
new file mode 100644
index 0000000..d34dc02
--- /dev/null
+++ b/board/imx31_phycore/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x87f00000
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
new file mode 100644
index 0000000..85fdc25
--- /dev/null
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -0,0 +1,73 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
+	__REG(CSCR_L(0)) = 0x10000d03;
+	__REG(CSCR_A(0)) = 0x00720900;
+
+	__REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
+	__REG(CSCR_L(1)) = 0x444a4541;
+	__REG(CSCR_A(1)) = 0x44443302;
+
+	__REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
+	__REG(CSCR_L(4)) = 0x22252521;
+	__REG(CSCR_A(4)) = 0x22220a00;
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+
+	/* setup pins for I2C2 (for EEPROM, RTC) */
+	mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
+	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
+
+	gd->bd->bi_arch_number = 447;		/* board id for linux */
+	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: Phytec phyCore i.MX31\n");
+	return 0;
+}
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
new file mode 100644
index 0000000..b0a5389
--- /dev/null
+++ b/board/imx31_phycore/lowlevel_init.S
@@ -0,0 +1,105 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	REG	CCM_CCMR, 0x074B0BF5
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	REG	CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) |	\
+			PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |		\
+			PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |		\
+			PDR0_MCU_PODF(0)
+
+	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
+
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
+
+	REG	0x43FAC26C, 0 /* SDCLK */
+	REG	0x43FAC270, 0 /* CAS */
+	REG	0x43FAC274, 0 /* RAS */
+	REG	0x43FAC27C, 0x1000 /* CS2 	CSD0) */
+	REG	0x43FAC284, 0 /* DQM3 */
+		/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */
+	REG	0x43FAC288, 0
+	REG	0x43FAC28C, 0
+	REG	0x43FAC290, 0
+	REG	0x43FAC294, 0
+	REG	0x43FAC298, 0
+	REG	0x43FAC29C, 0
+	REG	0x43FAC2A0, 0
+	REG	0x43FAC2A4, 0
+	REG	0x43FAC2A8, 0
+	REG	0x43FAC2AC, 0
+	REG	0x43FAC2B0, 0
+	REG	0x43FAC2B4, 0
+	REG	0x43FAC2B8, 0
+	REG	0x43FAC2BC, 0
+	REG	0x43FAC2C0, 0
+	REG	0x43FAC2C4, 0
+	REG	0x43FAC2C8, 0
+	REG	0x43FAC2CC, 0
+	REG	0x43FAC2D0, 0
+	REG	0x43FAC2D4, 0
+	REG	0x43FAC2D8, 0
+	REG	0x43FAC2DC, 0
+	REG	0xB8001010, 0x00000004
+	REG	0xB8001004, 0x006ac73a
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0xDEADBEEF
diff --git a/board/imx31_phycore/u-boot.lds b/board/imx31_phycore/u-boot.lds
new file mode 100644
index 0000000..1460adc
--- /dev/null
+++ b/board/imx31_phycore/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
new file mode 100644
index 0000000..647b05b
--- /dev/null
+++ b/include/configs/imx31_phycore.h
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
+#define CONFIG_MX31		1    /* in a mx31 */
+#define CONFIG_MX31_HCLK_FREQ	26000000
+#define CONFIG_MX31_CLK32	32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+#endif
+
+#define CONFIG_CMDLINE_TAG		1    /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
+#define CFG_GBL_DATA_SIZE	128  /* num bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_HARD_I2C		1
+#define CONFIG_I2C_MXC		1
+#define CFG_I2C_MX31_PORT2	1
+#define CFG_I2C_SPEED		100000
+#define CFG_I2C_SLAVE		0xfe
+
+#define CONFIG_MX31_UART	1
+#define CFG_MX31_UART1		1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#define CONFIG_BOOTDELAY	3
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)"
+
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.23.168
+#define CONFIG_SERVERIP		192.168.23.2
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
+	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
+		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
+	"bootargs_flash=setenv bootargs $(bootargs) "			\
+		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
+	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"bootcmd=run bootcmd_net\0"			       		\
+	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " 	\
+		"tftpboot 0x80000000 $(uimage); bootm\0"		\
+	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; "	\
+		"bootm 0x80000000\0"					\
+	"unlock=yes\0"							\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"prg_uboot=tftpboot 0x80000000 $(uboot); " 			\
+		"protect off 0xa0000000 +0x20000; "			\
+		"erase 0xa0000000 +0x20000; "				\
+		"cp.b 0x80000000 0xa0000000 $(filesize)\0" 		\
+	"prg_kernel=tftpboot 0x80000000 $(uimage); "			\
+		"erase 0xa0040000 +0x180000; "				\
+		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
+	"prg_jffs2=tftpboot 0x80000000 $(jffs2); " 			\
+		"erase 0xa01c0000 0xa1ffffff; "				\
+		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"
+
+#define CONFIG_DRIVER_SMC911X		1
+#define CONFIG_DRIVER_SMC911X_BASE	0xa8000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_PROMPT		"uboot> "
+#define CFG_CBSIZE		256  /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16          /* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0  /* memtest works on */
+#define CFG_MEMTEST_END		0x10000
+
+#define CFG_LOAD_ADDR		0 /* default load address */
+
+#define CFG_HZ			32000
+
+#define CONFIG_CMDLINE_EDITING	1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below  */
+#define CONFIG_STACKSIZE	(128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		0x80000000
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE		0xa0000000
+#define CFG_MAX_FLASH_BANKS	1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	259 /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */
+
+#define	CFG_ENV_IS_IN_EEPROM		1
+#define CFG_ENV_OFFSET			0x00	/* environment starts here */
+#define CFG_ENV_SIZE			4096
+#define CFG_I2C_EEPROM_ADDR		0x52
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start */
+#define CFG_I2C_EEPROM_ADDR_LEN		2 /* length of byte address */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(100*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV	"nor0"
+
+#endif /* __CONFIG_H */