Patch by Kurt Stremerch, 28 May 2004:

Add support for Exys XSEngine board

Some code cleanup.

15 files changed, 1177 insertions, 6 deletions

diff --git a/CHANGELOG b/CHANGELOG
index c0fcb96..bf6a9ff 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Patch by Kurt Stremerch, 28 May 2004:
+  Add support for Exys XSEngine board
+
 * Patch by Martin Krause, 27 May 2004:
   Fix a MPC5xxx I2C timing issue in i2c_probe().
 
diff --git a/CREDITS b/CREDITS
index 8a6afc7..3d22e67 100644
--- a/CREDITS
+++ b/CREDITS
@@ -319,6 +319,10 @@ N: Robert Schwebel
 E: r.schwebel@pengutronix.de
 D: Support for csb226, logodl and innokom boards (PXA2xx)
 
+N: Kurt Stremerch
+E: kurt@exys.be
+D: Support for Exys XSEngine board
+
 N: Rob Taylor
 E: robt@flyingpig.com
 D: Port to MBX860T and Sandpoint8240
diff --git a/MAKEALL b/MAKEALL
index 7590103..4f8fa8e 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -149,7 +149,7 @@ LIST_ARM9="	\
 ## Xscale Systems
 #########################################################################
 
-LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250"
+LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250 xsengine"
 
 LIST_ixp="ixdp425"
 
diff --git a/Makefile b/Makefile
index 4b9596d..cf8ecb7 100644
--- a/Makefile
+++ b/Makefile
@@ -1166,6 +1166,9 @@ wepep250_config	:	unconfig
 xm250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xm250
 
+xsengine_config :	unconfig
+	@./mkconfig $(@:_config=) arm pxa xsengine
+
 #========================================================================
 # i386
 #========================================================================
diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c
index ab1dabe..2072dce 100644
--- a/board/omap1610inn/omap1610innovator.c
+++ b/board/omap1610inn/omap1610innovator.c
@@ -102,8 +102,8 @@ void flash__init (void)
 
 #ifdef CONFIG_CS_AUTOBOOT
 	 /* Check swapping of CS0 and CS3, set flash base accordingly */
-        omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
-			                PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
+	omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
+					PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
 #endif
 	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
 	/* Turn off write protection for flash devices. */
diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile
new file mode 100644
index 0000000..df931e3
--- /dev/null
+++ b/board/xsengine/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= xsengine.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M --disassemble-all $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/xsengine/config.mk b/board/xsengine/config.mk
new file mode 100644
index 0000000..148c519
--- /dev/null
+++ b/board/xsengine/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xA3F80000
diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c
new file mode 100644
index 0000000..ac14bfe
--- /dev/null
+++ b/board/xsengine/flash.c
@@ -0,0 +1,565 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#if defined CFG_JFFS_CUSTOM_PART
+#include <jffs2/jffs2.h>
+#endif
+
+#define SWAP(x)               __swab32(x)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Functions */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#if defined CFG_JFFS_CUSTOM_PART
+
+/*
+ * jffs2_part_info - get information about a JFFS2 partition
+ *
+ * @part_num: number of the partition you want to get info about
+ * @return:   struct part_info* in case of success, 0 if failure
+ */
+
+static struct part_info part;
+static int current_part = -1;
+
+struct part_info* jffs2_part_info(int part_num) {
+	void *jffs2_priv_saved = part.jffs2_priv;
+
+	printf("jffs2_part_info: part_num=%i\n",part_num);
+
+	if (current_part == part_num)
+		return &part;
+
+	/* u-boot partition                                                 */
+	if(part_num==0){
+		memset(&part, 0, sizeof(part));
+
+		part.offset=(char*)0x00000000;
+		part.size=256*1024;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		printf("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* primary OS+firmware partition                                    */
+	if(part_num==1){
+		memset(&part, 0, sizeof(part));
+
+		part.offset=(char*)0x00040000;
+		part.size=1024*1024;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		printf("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* secondary OS+firmware partition                                  */
+	if(part_num==2){
+		memset(&part, 0, sizeof(part));
+
+		part.offset=(char*)0x00140000;
+		part.size=8*1024*1024;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		printf("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	if (current_part == part_num) {
+		part.usr_priv = &current_part;
+		part.jffs2_priv = jffs2_priv_saved;
+		return &part;
+	}
+
+	printf("jffs2_part_info: end of partition table\n");
+	return 0;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
+	flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV128U:	printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV320U:	printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV320B:	printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		debug ("Manufacturer: AMD\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		debug ("Manufacturer: FUJITSU\n");
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		debug ("Manufacturer: *** unknown ***\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+
+	case AMD_ID_MIRROR:
+		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+			addr[14], addr[15]);
+		switch(addr[14]) {
+		case AMD_ID_LV128U_2:
+			if (addr[15] != AMD_ID_LV128U_3) {
+				debug ("Chip: AMLV128U -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV128U\n");
+				info->flash_id += FLASH_AMLV128U;
+				info->sector_count = 256;
+				info->size = 0x02000000;
+			}
+			break;				/* => 32 MB	*/
+		case AMD_ID_LV640U_2:
+			if (addr[15] != AMD_ID_LV640U_3) {
+				debug ("Chip: AMLV640U -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV640U\n");
+				info->flash_id += FLASH_AMLV640U;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+			}
+			break;				/* => 16 MB	*/
+		case AMD_ID_LV320B_2:
+			if (addr[15] != AMD_ID_LV320B_3) {
+				debug ("Chip: AMLV320B -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV320B\n");
+				info->flash_id += FLASH_AMLV320B;
+				info->sector_count = 71;
+				info->size = 0x00800000;
+			}
+			break;				/* =>  8 MB	*/
+		default:
+			debug ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			break;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	switch (value) {
+	case AMD_ID_MIRROR:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		/* only known types here - no default */
+		case FLASH_AMLV128U:
+		case FLASH_AMLV640U:
+		case FLASH_AMLV320U:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 0x20000;
+			}
+			break;
+		case FLASH_AMLV320B:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				/*
+				 * The first 8 sectors are 8 kB,
+				 * all the other ones  are 64 kB
+				 */
+				base += (i < 8)
+					?  2 * ( 8 << 10)
+					:  2 * (64 << 10);
+			}
+			break;
+		}
+		break;
+
+	default:
+		return (0);
+		break;
+	}
+
+#if 0
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+#endif
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 100000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	ulong rev;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/xsengine/memsetup.S b/board/xsengine/memsetup.S
new file mode 100644
index 0000000..b947118
--- /dev/null
+++ b/board/xsengine/memsetup.S
@@ -0,0 +1,221 @@
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+.globl memsetup
+memsetup:
+
+   mov      r10, lr
+
+/* ---- GPIO INITIALISATION ---- */
+/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
+
+   /* General purpose set registers */
+   ldr      r0,   =GPSR0
+   ldr      r1,   =CFG_GPSR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPSR1
+   ldr      r1,   =CFG_GPSR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPSR2
+   ldr      r1,   =CFG_GPSR2_VAL
+   str      r1,   [r0]
+
+   /* General purpose clear registers */
+   ldr      r0,   =GPCR0
+   ldr      r1,   =CFG_GPCR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPCR1
+   ldr      r1,   =CFG_GPCR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPCR2
+   ldr      r1,   =CFG_GPCR2_VAL
+   str      r1,   [r0]
+
+   /* General rising edge registers */
+   ldr      r0,   =GRER0
+   ldr      r1,   =CFG_GRER0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GRER1
+   ldr      r1,   =CFG_GRER1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GRER2
+   ldr      r1,   =CFG_GRER2_VAL
+   str      r1,   [r0]
+
+   /* General falling edge registers */
+   ldr      r0,   =GFER0
+   ldr      r1,   =CFG_GFER0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GFER1
+   ldr      r1,   =CFG_GFER1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GFER2
+   ldr      r1,   =CFG_GFER2_VAL
+   str      r1,   [r0]
+
+   /* General edge detect registers */
+   ldr      r0,   =GPDR0
+   ldr      r1,   =CFG_GPDR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR1
+   ldr      r1,   =CFG_GPDR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR2
+   ldr      r1,   =CFG_GPDR2_VAL
+   str      r1,   [r0]
+
+   /* General alternate function registers */
+   ldr      r0,   =GAFR0_L		/* [0:15] */
+   ldr      r1,   =CFG_GAFR0_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR0_U		/* [31:16] */
+   ldr      r1,   =CFG_GAFR0_U_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR1_L		/* [47:32] */
+   ldr      r1,   =CFG_GAFR1_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR1_U		/* [63:48] */
+   ldr      r1,   =CFG_GAFR1_U_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR2_L		/* [79:64] */
+   ldr      r1,   =CFG_GAFR2_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR2_U		/* [80] */
+   ldr      r1,   =CFG_GAFR2_U_VAL
+   str      r1,   [r0]
+
+   /* General purpose direction registers */
+   ldr      r0,   =GPDR0
+   ldr      r1,   =CFG_GPDR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR1
+   ldr      r1,   =CFG_GPDR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR2
+   ldr      r1,   =CFG_GPDR2_VAL
+   str      r1,   [r0]
+
+   /* Power manager sleep status */
+   ldr      r0,   =PSSR
+   ldr      r1,   =CFG_PSSR_VAL
+   str      r1,   [r0]
+
+/* ---- MEMORY INITIALISATION ---- */
+/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
+/* pause for 200 uSecs- allow internal clocks to settle */
+   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300  	/* really 0x2E1 is about 200usec, so 0x300 should be plenty */
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+mem_init:
+/* get memory controller base address */
+   ldr     r1,  =MEMC_BASE
+
+/* ---- FLASH INITIALISATION ---- */
+/* Write MSC0 and read back to ensure data change is accepted by cpu */
+   ldr     r2,   =CFG_MSC0_VAL
+   str     r2,   [r1, #MSC0_OFFSET]
+   ldr     r2,   [r1, #MSC0_OFFSET]
+
+/* ---- SDRAM INITIALISATION ---- */
+/* get the MDREFR settings */
+   ldr     r2,  =CFG_MDREFR_VAL
+   str     r2,  [r1, #MDREFR_OFFSET]
+
+/* fetch platform value of MDCNFG */
+   ldr     r2,  =CFG_MDCNFG_VAL
+
+/* disable all sdram banks */
+   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+/* write initial value of MDCNFG, w/o enabling sdram banks */
+   str     r2,  [r1, #MDCNFG_OFFSET]
+
+/* pause for 200 uSecs */
+   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300  	/* about 200 usec */
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+/* Access memory *not yet enabled* for CBR refresh cycles (8) */
+/* CBR is generated for all banks */
+
+   ldr     r2, =CFG_DRAM_BASE
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+
+/* get memory controller base address */
+   ldr     r2,  =MEMC_BASE
+
+/* Enable SDRAM bank 0 in MDCNFG register */
+   ldr     r2,  [r1, #MDCNFG_OFFSET]
+   orr     r2,  r2,  #MDCNFG_DE0
+   str     r2,  [r1, #MDCNFG_OFFSET]
+
+/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
+   ldr     r2,  =CFG_MDMRS_VAL
+   str     r2,  [r1, #MDMRS_OFFSET]
+
+/* ---- INTERRUPT INITIALISATION ---- */
+/* Disable (mask) all interrupts at the interrupt controller */
+/* clear the interrupt level register (use IRQ, not FIQ) */
+   mov     r1, #0
+   ldr     r2,  =ICLR
+   str     r1,  [r2]
+
+/* Set interrupt mask register */
+   ldr     r1,  =CFG_ICMR_VAL
+   ldr     r2,  =ICMR
+   str     r1,  [r2]
+
+/* ---- CLOCK INITIALISATION ---- */
+/* Disable the peripheral clocks, and set the core clock */
+
+/* Turn Off ALL on-chip peripheral clocks for re-configuration */
+   ldr     r1,  =CKEN
+   mov     r2,  #0
+   str     r2,  [r1]
+
+/* set core clocks */
+   ldr     r2,  =CFG_CCCR_VAL
+   ldr     r1,  =CCCR
+   str     r2,  [r1]
+
+#ifdef ENABLE32KHZ
+/* enable the 32Khz oscillator for RTC and PowerManager */
+   ldr     r1,  =OSCC
+   mov     r2,  #OSCC_OON
+   str     r2,  [r1]
+
+/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL has settled. */
+60:
+   ldr     r2, [r1]
+   ands    r2, r2, #1
+   beq     60b
+#endif
+
+/* Turn on needed clocks */
+   ldr     r1,  =CKEN
+   ldr     r2,  =CFG_CKEN_VAL
+   str     r2,  [r1]
+
+   mov   pc, r10
diff --git a/board/xsengine/u-boot.lds b/board/xsengine/u-boot.lds
new file mode 100644
index 0000000..e0b0514
--- /dev/null
+++ b/board/xsengine/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
new file mode 100644
index 0000000..c33b6f0
--- /dev/null
+++ b/board/xsengine/xsengine.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number */
+	gd->bd->bi_arch_number = 532;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_post_init (void)
+{
+	setenv ("stdout", "serial");
+	setenv ("stderr", "serial");
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/drivers/smc91111.h b/drivers/smc91111.h
index b373452..0b6dfeb 100644
--- a/drivers/smc91111.h
+++ b/drivers/smc91111.h
@@ -76,6 +76,16 @@ typedef unsigned long int 		dword;
 
 #ifdef CONFIG_PXA250
 
+#ifdef CONFIG_XSENGINE
+#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
+#define SMC_inb(p)	({ \
+	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
+	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
+	if (__p & 2) __v >>= 8; \
+	else __v &= 0xff; \
+	__v; })
+#else
 #define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
 #define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 #define SMC_inb(p)	({ \
@@ -84,9 +94,16 @@ typedef unsigned long int 		dword;
 	if (__p & 1) __v >>= 8; \
 	else __v &= 0xff; \
 	__v; })
+#endif
 
+#ifdef CONFIG_XSENGINE
+#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#else
 #define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
 #define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#endif
+
 #define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
 				word __w = SMC_inw((r)&~1);  \
 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
@@ -191,7 +208,11 @@ typedef unsigned long int 		dword;
 
 #if defined(CONFIG_SMC_USE_32_BIT)
 
+#ifdef CONFIG_XSENGINE
+#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#else
 #define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
+#endif
 
 #define SMC_insl(r,b,l) 	({	int __i ;  \
 					dword *__b2;  \
@@ -202,8 +223,11 @@ typedef unsigned long int 		dword;
 					};  \
 				})
 
+#ifdef CONFIG_XSENGINE
+#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#else
 #define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-
+#endif
 #define SMC_outsl(r,b,l)	({	int __i; \
 					dword *__b2; \
 					__b2 = (dword *) b; \
diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h
index b2b0fe7..94af0b2 100644
--- a/include/configs/omap1610h2.h
+++ b/include/configs/omap1610h2.h
@@ -150,7 +150,7 @@
 #define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */
 
 #ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */
-				
+
 #ifndef __ASSEMBLY__
 extern unsigned long omap_flash_base;		/* set in flash__init */
 #endif
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
index cbf828c..94fbac6 100644
--- a/include/configs/omap1610inn.h
+++ b/include/configs/omap1610inn.h
@@ -155,7 +155,7 @@
 #define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */
 
 #ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */
-				
+
 #ifndef __ASSEMBLY__
 extern unsigned long omap_flash_base;		/* set in flash__init */
 #endif
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
new file mode 100644
index 0000000..87d2c94
--- /dev/null
+++ b/include/configs/xsengine.h
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL				/* undef for developing */
+
+/* High Level Configuration Options */
+#define CONFIG_PXA250			1		/* This is an PXA250 CPU    */
+#define CONFIG_XSENGINE			1
+#define CONFIG_MMC			1
+#define BOARD_POST_INIT			1
+#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
+#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+
+#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
+#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */
+
+#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
+#define CFG_DRAM_BASE			0xa0000000
+#define CFG_DRAM_SIZE			0x04000000
+
+/* FLASH organization */
+#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
+#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
+#define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_JFFS2_NUM_BANKS		1
+#define CFG_JFFS2_FIRST_BANK		0
+#define CFG_JFFS_CUSTOM_PART		1
+
+/* Environment settings */
+#define CONFIG_ENV_OVERWRITE
+#define CFG_ENV_IS_IN_FLASH             1
+#define CFG_ENV_ADDR                    (PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector (after monitor)*/
+#define CFG_ENV_SECT_SIZE               PHYS_FLASH_SECT_SIZE		/* Size of the Environment Sector */
+#define CFG_ENV_SIZE                    0x4000				/* 16kB Total Size of Environment Sector */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT		(75*CFG_HZ) 	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(50*CFG_HZ) 	/* Timeout for Flash Write */
+
+/* Size of malloc() pool */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
+
+/* Hardware drivers */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE		0x04000300
+#define CONFIG_SMC_USE_32_BIT 		1
+
+/* select serial console configuration */
+#define CONFIG_FFUART			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ETHADDR			FF:FF:FF:FF:FF:FF
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_IPADDR			192.168.1.50
+#define CONFIG_SERVERIP			192.168.1.2
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
+#define CONFIG_CMDLINE_TAG
+
+/* Miscellaneous configurable options */
+#define CFG_HUSH_PARSER			1
+#define CFG_PROMPT_HUSH_PS2		"> "
+#define CFG_LONGHELP								/* undef to save memory	*/
+#define CFG_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
+#define CFG_CBSIZE			256					/* Console I/O Buffer Size */
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) 	/* Print Buffer Size */
+#define CFG_MAXARGS			16					/* max number of command args */
+#define CFG_BARGSIZE			CFG_CBSIZE				/* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START		0xA0400000				/* memtest works on     */
+#define CFG_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
+#undef  CFG_CLKS_IN_HZ          						/* everything, incl board info, in Hz */
+#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
+#define CFG_MMC_BASE			0xF0000000
+#define CFG_LOAD_ADDR           	0xA0000000				/* load kernel to this address   */
+
+/* Stack sizes - The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+#ifdef  CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#endif
+
+/* GP set register */
+#define CFG_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CFG_GPSR1_VAL			0x00020000	/* nPWE */
+#define CFG_GPSR2_VAL			0x0000C000	/* CS2, CS3 */
+
+/* GP clear register */
+#define CFG_GPCR0_VAL			0x00000000
+#define CFG_GPCR1_VAL			0x00000000
+#define CFG_GPCR2_VAL			0x00000000
+
+/* GP direction register */
+#define CFG_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CFG_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
+#define CFG_GPDR2_VAL			0x0000C000  	/* CS2, CS3 */
+
+/* GP rising edge detect register */
+#define CFG_GRER0_VAL			0x00000000
+#define CFG_GRER1_VAL			0x00000000
+#define CFG_GRER2_VAL			0x00000000
+
+/* GP falling edge detect register */
+#define CFG_GFER0_VAL			0x00000000
+#define CFG_GFER1_VAL			0x00000000
+#define CFG_GFER2_VAL			0x00000000
+
+/* GP alternate function register */
+#define CFG_GAFR0_L_VAL			0x80000000	/* CS1 */
+#define CFG_GAFR0_U_VAL			0x00000010	/* RDY */
+#define CFG_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
+#define CFG_GAFR1_U_VAL			0x00000008	/* nPWE */
+#define CFG_GAFR2_L_VAL			0xA0000000  	/* CS2, CS3 */
+#define CFG_GAFR2_U_VAL			0x00000000
+
+#define CFG_PSSR_VAL			0x00000020	/* Power manager sleep status */
+#define CFG_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
+#define CFG_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
+#define CFG_ICMR_VAL			0x00000000	/* No interrupts enabled        */
+
+/* Memory settings */
+#define CFG_MSC0_VAL			0x25F425F0
+
+/* MDCNFG: SDRAM Configuration Register */
+#define CFG_MDCNFG_VAL			0x000009C9
+
+/* MDREFR: SDRAM Refresh Control Register */
+#define CFG_MDREFR_VAL			0x00018018
+
+/* MDMRS: Mode Register Set Configuration Register */
+#define CFG_MDMRS_VAL			0x00220022
+
+#endif	/* __CONFIG_H */