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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-10-16 21:58:49 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-17 10:50:41 +0200 |
| commit | 42653b826adb319a1df06e24ef26096b2a5d9d2a (patch) | |
| tree | 528e1ff4e00b995a1c0900c044ce6eb29e34b0ec | |
| parent | c794c670f72cf20ca30573b2433151474cdca42a (diff) | |
| download | u-boot-imx-42653b826adb319a1df06e24ef26096b2a5d9d2a.zip u-boot-imx-42653b826adb319a1df06e24ef26096b2a5d9d2a.tar.gz u-boot-imx-42653b826adb319a1df06e24ef26096b2a5d9d2a.tar.bz2 | |
Revert "85xx: Using proper I2C source clock divider for MPC8544"
This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159.
The fix introduced by this patch is not correct. The problem is
that the documentation is not correct for the MPC8544 with regards
to which bit in PORDEVSR2 is for the SEC_CFG.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | cpu/mpc85xx/speed.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 70dfad0..485ba20 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -102,9 +102,9 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 2; - else gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ gd->i2c1_clk = sys_info.freqSystemBus / 2; |