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| author | Adrian Alonso <adrian.alonso@nxp.com> | 2016-08-25 13:28:34 -0500 |
|---|---|---|
| committer | Adrian Alonso <adrian.alonso@nxp.com> | 2016-09-15 13:59:27 -0500 |
| commit | ffc7bc56e76f9293e2f613bc82ed2e5d08ecb189 (patch) | |
| tree | 27ca5179e5315a31889968a64f4787b0c2eca865 | |
| parent | e644db282762ea8ea6398b8fecc1160034acf80e (diff) | |
| download | u-boot-imx-ffc7bc56e76f9293e2f613bc82ed2e5d08ecb189.zip u-boot-imx-ffc7bc56e76f9293e2f613bc82ed2e5d08ecb189.tar.gz u-boot-imx-ffc7bc56e76f9293e2f613bc82ed2e5d08ecb189.tar.bz2 | |
MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividers
Adjust ahb/axi clock root podf dividers to be divided by 1
to allow ahb/axi clock root to be 24Mhz when sourced
from osc_clk.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(Cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)
| -rw-r--r-- | board/freescale/mx6qarm2/mt128x64mx32.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg index 1d2e0e3..0f9940d 100644 --- a/board/freescale/mx6qarm2/mt128x64mx32.cfg +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -44,7 +44,7 @@ CSF CONFIG_CSF_SIZE #ifdef CONFIG_MX6DQ_POP_LPDDR2 /* set ddr to 400Mhz */ DATA 4 0x020C4018 0x21324 -DATA 4 0x020C4014 0x2018900 +DATA 4 0x020C4014 0x2018100 CHECK_BITS_CLR 4 0x020C4048 0x3F DATA 4 0x020C4018 0x61324 DATA 4 0x020C4014 0x18900 |