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author | Nitin Garg <nitin.garg@freescale.com> | 2015-03-31 20:37:36 -0500 |
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committer | Ye Li <ye.li@nxp.com> | 2016-03-25 16:08:28 +0800 |
commit | f20a65847577ff40dc7e3739a0bb69926885c734 (patch) | |
tree | f86b003ac56df8b113db3343315aac060aa20358 | |
parent | 1c27c9ecf80b3cc63a7c9751ebfd11755f847b1d (diff) | |
download | u-boot-imx-f20a65847577ff40dc7e3739a0bb69926885c734.zip u-boot-imx-f20a65847577ff40dc7e3739a0bb69926885c734.tar.gz u-boot-imx-f20a65847577ff40dc7e3739a0bb69926885c734.tar.bz2 |
MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
-rw-r--r-- | README | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/start.S | 6 | ||||
-rw-r--r-- | include/configs/mx6_common.h | 1 |
3 files changed, 8 insertions, 0 deletions
@@ -645,6 +645,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_773022 CONFIG_ARM_ERRATA_774769 CONFIG_ARM_ERRATA_794072 + CONFIG_ARM_ERRATA_845369 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index b180944..e3e8b7f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -9,6 +9,7 @@ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> * Copyright (c) 2003 Kshitij <kshitij@ti.com> * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> + * Copyright (C) 2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -163,6 +164,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 21 @ set bit #21 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_845369 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 22 @ set bit #22 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov r5, lr @ Store my Caller mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index a228618..cf1e826 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -13,6 +13,7 @@ #define CONFIG_ARM_ERRATA_751472 #define CONFIG_ARM_ERRATA_794072 #define CONFIG_ARM_ERRATA_761320 +#define CONFIG_ARM_ERRATA_845369 #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 |