ARM: IXP: Remove the IXP architecture support

The architecture is unmaintained and dead, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michael Schwingen <michael@schwingen.org>
Cc: Tom Rini <trini@ti.com>

13 files changed, 0 insertions, 1547 deletions

diff --git a/MAKEALL b/MAKEALL
index 562071a..63838ce 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -398,8 +398,6 @@ LIST_at91="$(targets_by_soc at91)"
 
 LIST_pxa="$(targets_by_cpu pxa)"
 
-LIST_ixp="$(targets_by_cpu ixp)"
-
 #########################################################################
 ## SPEAr Systems
 #########################################################################
diff --git a/README b/README
index 176de61..8ea097d 100644
--- a/README
+++ b/README
@@ -141,7 +141,6 @@ Directory Hierarchy:
 	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
       /arm926ejs	Files specific to ARM 926 CPUs
       /arm1136		Files specific to ARM 1136 CPUs
-      /ixp		Files specific to Intel XScale IXP CPUs
       /pxa		Files specific to Intel XScale PXA CPUs
       /sa1100		Files specific to Intel StrongARM SA1100 CPUs
     /lib		Architecture specific library files
diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile
deleted file mode 100644
index 4e66523..0000000
--- a/arch/arm/cpu/ixp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y	= start.o
-
-obj-y	+= cpu.o
-obj-$(CONFIG_USE_IRQ)	+= interrupts.o
-obj-y	+= timer.o
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
deleted file mode 100644
index 894861f..0000000
--- a/arch/arm/cpu/ixp/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-BIG_ENDIAN = y
-
-PLATFORM_RELFLAGS += -mbig-endian
-
-PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
-
-PLATFORM_LDFLAGS += -EB
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c
deleted file mode 100644
index 4387c18..0000000
--- a/arch/arm/cpu/ixp/cpu.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/arch/ixp425.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-	unsigned long id;
-	int speed = 0;
-
-	asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
-	puts("CPU:   Intel IXP425 at ");
-	switch ((id & 0x000003f0) >> 4) {
-	case 0x1c:
-		speed = 533;
-		break;
-
-	case 0x1d:
-		speed = 400;
-		break;
-
-	case 0x1f:
-		speed = 266;
-		break;
-	}
-
-	if (speed)
-		printf("%d MHz\n", speed);
-	else
-		puts("unknown revision\n");
-
-	return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * just disable everything that can disturb booting linux
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I-cache */
-	cache_flush();
-
-	return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-/* FIXME */
-/*
-void pci_init(void)
-{
-	return;
-}
-*/
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_IXP4XX_NPE
-	npe_initialize(bis);
-#endif
-	return 0;
-}
diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c
deleted file mode 100644
index 7694c6a..0000000
--- a/arch/arm/cpu/ixp/interrupts.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/proc-armv/ptrace.h>
-
-struct _irq_handler {
-	void                *m_data;
-	void (*m_func)( void *data);
-};
-
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-
-static void default_isr(void *data)
-{
-	printf("default_isr():  called for IRQ %d, Interrupt Status=%x PR=%x\n",
-	       (int)data, *IXP425_ICIP, *IXP425_ICIH);
-}
-
-static int next_irq(void)
-{
-	return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	int irq = next_irq();
-
-	IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
-}
-
-void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
-{
-	if (irq >= N_IRQS || !handle_irq)
-		return;
-
-	IRQ_HANDLER[irq].m_data = data;
-	IRQ_HANDLER[irq].m_func = handle_irq;
-}
-
-int arch_interrupt_init (void)
-{
-	int i;
-
-	/* install default interrupt handlers */
-	for (i = 0; i < N_IRQS; i++)
-		irq_install_handler(i, default_isr, (void *)i);
-
-	/* configure interrupts for IRQ mode */
-	*IXP425_ICLR = 0x00000000;
-
-	return (0);
-}
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
deleted file mode 100644
index 82c868a..0000000
--- a/arch/arm/cpu/ixp/start.S
+++ /dev/null
@@ -1,430 +0,0 @@
-/* vi: set ts=8 sw=8 noet: */
-/*
- *  u-boot - Startup Code for XScale IXP
- *
- * Copyright (C) 2003	Kyle Harris <kharris@nexus-tech.net>
- *
- * Based on startup code example contained in the
- * Intel IXP4xx Programmer's Guide and past u-boot Start.S
- * samples.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/arch/ixp425.h>
-
-#define MMU_Control_M  0x001    /* Enable MMU */
-#define MMU_Control_A  0x002    /* Enable address alignment faults */
-#define MMU_Control_C  0x004    /* Enable cache */
-#define MMU_Control_W  0x008    /* Enable write-buffer */
-#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
-#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
-#define MMU_Control_L  0x040    /* Compatability: */
-#define MMU_Control_B  0x080    /* Enable Big-Endian */
-#define MMU_Control_S  0x100    /* Enable system protection */
-#define MMU_Control_R  0x200    /* Enable ROM protection */
-#define MMU_Control_I  0x1000   /* Enable Instruction cache */
-#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
-	/* Delay a bit */
-	.macro DELAY_FOR cycles, reg0
-	ldr     \reg0, =\cycles
-	subs    \reg0, \reg0, #1
-	subne   pc,  pc, #0xc
-	.endm
-
-	/* wait for coprocessor write complete */
-	.macro CPWAIT reg
-	mrc  p15,0,\reg,c2,c0,0
-	mov  \reg,\reg
-	sub  pc,pc,#4
-	.endm
-
-.globl _start
-_start:
-	ldr	pc, _reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_reset:                 .word reset
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * - relocate armboot to ram
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/* disable mmu, set big-endian */
-	mov	r0, #0xf8
-	mcr	p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* disable write buffer coalescing */
-	mrc	p15, 0, r0, c1, c0, 1
-	orr	r0, r0, #1
-	mcr	p15, 0, r0, c1, c0, 1
-	CPWAIT	r0
-
-	/* set EXP CS0 to the optimum timing */
-	ldr	r1, =CONFIG_SYS_EXP_CS0
-	ldr     r2, =IXP425_EXP_CS0
-	str     r1, [r2]
-
-	/* make sure flash is visible at 0 */
-	mov	r1, #CONFIG_SYS_SDR_CONFIG
-	ldr     r2, =IXP425_SDR_CONFIG
-	str     r1, [r2]
-
-	/* disable refresh cycles */
-	mov	r1, #0
-	ldr     r3, =IXP425_SDR_REFRESH
-	str	r1, [r3]
-
-	/* send nop command */
-	mov	r1, #3
-	ldr	r4, =IXP425_SDR_IR
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* set SDRAM internal refresh val */
-	ldr	r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
-	str     r1, [r3]
-	DELAY_FOR 0x4000, r0
-
-	/* send precharge-all command to close all open banks */
-	mov     r1, #2
-	str     r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* provide 8 auto-refresh cycles */
-	mov     r1, #4
-	mov     r5, #8
-111:    str	r1, [r4]
-	DELAY_FOR 0x100, r0
-	subs	r5, r5, #1
-	bne	111b
-
-	/* set mode register in sdram */
-	mov	r1, #CONFIG_SYS_SDR_MODE_CONFIG
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* send normal operation command */
-	mov	r1, #6
-	str	r1, [r4]
-	DELAY_FOR 0x4000, r0
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
-
-	/* remove flash mirror at 0x00000000 */
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	bic     r1, r1, #0x80000000
-	str     r1, [r2]
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* enable I cache */
-	mrc     p15, 0, r0, c1, c0, 0
-	orr     r0, r0, #MMU_Control_I
-	mcr     p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
-	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	bx	lr
-
-/****************************************************************************/
-/*									    */
-/* Interrupt handling							    */
-/*									    */
-/****************************************************************************/
-
-/* IRQ stack frame							    */
-
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-
-	/* use bad_save_user_regs for abort/prefetch/undef/swi ...	    */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	    */
-	add	r8, sp, #S_PC
-
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r4}			/* get pc, cpsr, old_r0	    */
-	add	r0, sp, #S_FRAME_SIZE		/* restore sp_SVC	    */
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}			/* save sp_SVC, lr_SVC, pc, cpsr, old_r */
-	mov	r0, sp
-	.endm
-
-
-	/* use irq_save_user_regs / irq_restore_user_regs for		     */
-	/* IRQ/FIQ handling						     */
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			/* Calling r0-r12	     */
-	add	r8, sp, #S_PC
-	stmdb	r8, {sp, lr}^			/* Calling SP, LR	     */
-	str	lr, [r8, #0]			/* Save calling PC	     */
-	mrs	r6, spsr
-	str	r6, [r8, #4]			/* Save CPSR		     */
-	str	r0, [r8, #8]			/* Save OLD_R0		     */
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str	lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-
-/****************************************************************************/
-/*									    */
-/* exception handlers							    */
-/*									    */
-/****************************************************************************/
-
-	.align	5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	irq_save_user_regs		/* someone ought to write a more    */
-	bl	do_fiq			/* effiction fiq_save_user_regs	    */
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-/****************************************************************************/
-/*                                                                          */
-/* Reset function: Use Watchdog to reset                                    */
-/*                                                                          */
-/****************************************************************************/
-
-	.align	5
-.globl reset_cpu
-
-reset_cpu:
-	ldr	r1, =0x482e
-	ldr     r2, =IXP425_OSWK
-	str     r1, [r2]
-	ldr	r1, =0x0fff
-	ldr     r2, =IXP425_OSWT
-	str     r1, [r2]
-	ldr	r1, =0x5
-	ldr     r2, =IXP425_OSWE
-	str     r1, [r2]
-	b	reset_endless
-
-reset_endless:
-	b	reset_endless
diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c
deleted file mode 100644
index 38e2e28..0000000
--- a/arch/arm/cpu/ixp/timer.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
- * 33.333MHz crystal).
- */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_IXP425_TIMER_CLK);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_IXP425_TIMER_CLK;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_IXP425_TIMER_CLK + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-
-unsigned long long get_ticks(void)
-{
-	ulong now = readl(IXP425_OSTS_B);
-
-	if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
-		/* rollover of timestamp timer register */
-		gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
-		writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
-	} else {
-		/* move stamp forward with absolut diff ticks */
-		gd->arch.timestamp += (now - gd->arch.lastinc);
-	}
-	gd->arch.lastinc = now;
-	return gd->arch.timestamp;
-}
-
-
-void reset_timer_masked(void)
-{
-	/* capture current timestamp counter */
-	gd->arch.lastinc = readl(IXP425_OSTS_B);
-	/* start "advancing" time stamp from 0 */
-	gd->arch.timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-
-	tmp = get_ticks() + us_to_tick(usec);
-
-	while (get_ticks() < tmp)
-		;
-}
-
-int timer_init(void)
-{
-	writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
-	return 0;
-}
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
deleted file mode 100644
index 676ae2c..0000000
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		*(.__image_copy_start)
-		arch/arm/cpu/ixp/start.o(.text*)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h
deleted file mode 100644
index c2e9c82..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
- * include/asm-arm/arch-ixp425/ixp425.h
- *
- * Register definitions for IXP425
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP425_H_
-#define _ASM_ARM_IXP425_H_
-
-#define BIT(x)	(1<<(x))
-
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-#ifdef UBOOT_REG_FIX
-# undef	io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-#  define io_p2v(PhAdd)    (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-#  define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
-
-/*
- *
- * IXP425 Memory map:
- *
- * Phy		Phy Size	Map Size	Virt		Description
- * =========================================================================
- *
- * 0x00000000	0x10000000					SDRAM 1
- *
- * 0x10000000	0x10000000					SDRAM 2
- *
- * 0x20000000	0x10000000					SDRAM 3
- *
- * 0x30000000	0x10000000					SDRAM 4
- *
- * The above four are aliases to the same memory location  (0x00000000)
- *
- * 0x48000000	 0x4000000					PCI Memory
- *
- * 0x50000000	0x10000000			Not Mapped	EXP BUS
- *
- * 0x6000000	0x00004000	    0x4000	0xFFFEB000	QMgr
- *
- * 0xC0000000	     0x100	    0x1000	0xFFFDD000	PCI CFG
- *
- * 0xC4000000	     0x100          0x1000	0xFFFDE000	EXP CFG
- *
- * 0xC8000000	    0xC000          0xC000	0xFFFDF000	PERIPHERAL
- *
- * 0xCC000000	     0x100	    0x1000	Not Mapped	SDRAM CFG
- */
-
-/*
- * SDRAM
- */
-#define IXP425_SDRAM_BASE		(0x00000000)
-#define IXP425_SDRAM_BASE_ALT		(0x10000000)
-
-
-/*
- * PCI Configuration space
- */
-#define IXP425_PCI_CFG_BASE_PHYS	(0xC0000000)
-#define IXP425_PCI_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP425_EXP_CFG_BASE_PHYS	(0xC4000000)
-#define IXP425_EXP_CFG_REGION_SIZE	(0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP425_PERIPHERAL_BASE_PHYS	(0xC8000000)
-#define IXP425_PERIPHERAL_REGION_SIZE	(0x0000C000)
-
-/*
- * SDRAM configuration registers
- */
-#define IXP425_SDRAM_CFG_BASE_PHYS	(0xCC000000)
-
-/*
- * Q Manager space .. not static mapped
- */
-#define IXP425_QMGR_BASE_PHYS		(0x60000000)
-#define IXP425_QMGR_REGION_SIZE		(0x00004000)
-
-/*
- * Expansion BUS
- *
- * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
- * Exp Bus config registers:
- *
- * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
- * and The expansion bus to IXP425_EXP_BUS_BASE2
- */
-#define IXP425_EXP_BUS_BASE1_PHYS	(0x00000000)
-#define IXP425_EXP_BUS_BASE2_PHYS	(0x50000000)
-
-#define IXP425_EXP_BUS_BASE_PHYS	IXP425_EXP_BUS_BASE2_PHYS
-
-#define IXP425_EXP_BUS_REGION_SIZE	(0x08000000)
-#define IXP425_EXP_BUS_CSX_REGION_SIZE	(0x01000000)
-
-#define IXP425_EXP_BUS_CS0_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-
-#define IXP425_FLASH_WRITABLE	(0x2)
-#define IXP425_FLASH_DEFAULT	(0xbcd23c40)
-#define IXP425_FLASH_WRITE	(0xbcd23c42)
-
-#define IXP425_EXP_CS0_OFFSET	0x00
-#define IXP425_EXP_CS1_OFFSET   0x04
-#define IXP425_EXP_CS2_OFFSET   0x08
-#define IXP425_EXP_CS3_OFFSET   0x0C
-#define IXP425_EXP_CS4_OFFSET   0x10
-#define IXP425_EXP_CS5_OFFSET   0x14
-#define IXP425_EXP_CS6_OFFSET   0x18
-#define IXP425_EXP_CS7_OFFSET   0x1C
-#define IXP425_EXP_CFG0_OFFSET	0x20
-#define IXP425_EXP_CFG1_OFFSET	0x24
-#define IXP425_EXP_CFG2_OFFSET	0x28
-#define IXP425_EXP_CFG3_OFFSET	0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
-
-#define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
-#define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2      IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
-#define IXP425_EXP_CS3      IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
-#define IXP425_EXP_CS4      IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
-#define IXP425_EXP_CS5      IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6      IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
-#define IXP425_EXP_CS7      IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-
-#define IXP425_EXP_CFG0     IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1     IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
-#define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
-
-/*
- * SDRAM Controller registers.
- */
-#define IXP425_SDR_CONFIG_OFFSET	0x00
-#define IXP425_SDR_REFRESH_OFFSET	0x04
-#define IXP425_SDR_IR_OFFSET		0x08
-
-#define IXP425_SDRAM_REG(x)	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
-
-#define IXP425_SDR_CONFIG	IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR		IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
-
-/*
- * UART registers
- */
-#define IXP425_UART1		0
-#define IXP425_UART2		0x1000
-
-#define IXP425_UART_RBR_OFFSET	0x00
-#define IXP425_UART_THR_OFFSET	0x00
-#define IXP425_UART_DLL_OFFSET	0x00
-#define IXP425_UART_IER_OFFSET	0x04
-#define IXP425_UART_DLH_OFFSET	0x04
-#define IXP425_UART_IIR_OFFSET	0x08
-#define IXP425_UART_FCR_OFFSET	0x00
-#define IXP425_UART_LCR_OFFSET	0x0c
-#define IXP425_UART_MCR_OFFSET	0x10
-#define IXP425_UART_LSR_OFFSET	0x14
-#define IXP425_UART_MSR_OFFSET	0x18
-#define IXP425_UART_SPR_OFFSET	0x1c
-#define IXP425_UART_ISR_OFFSET	0x20
-
-#define IXP425_UART_CFG_BASE_PHYS	(0xc8000000)
-
-#define RBR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
-#define THR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
-#define DLL(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
-#define IER(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
-#define DLH(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
-#define IIR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
-#define FCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
-#define LCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
-#define MCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
-#define LSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
-#define MSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
-#define SPR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
-#define ISR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
-
-#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
-#define IER_UUE		(1 << 6)	/* UART Unit Enable */
-#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
-#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
-#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
-#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
-#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
-#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
-#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
-#define IIR_TOD		(1 << 3)	/* Time Out Detected */
-#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
-#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
-#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
-
-#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
-#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
-#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
-#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
-#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1	(0)
-#define FCR_ITL_8	(FCR_ITL1)
-#define FCR_ITL_16	(FCR_ITL2)
-#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
-#define LCR_SB		(1 << 6)	/* Set Break */
-#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
-#define LCR_EPS		(1 << 4)	/* Even Parity Select */
-#define LCR_PEN		(1 << 3)	/* Parity Enable */
-#define LCR_STB		(1 << 2)	/* Stop Bit */
-#define LCR_WLS1	(1 << 1)	/* Word Length Select */
-#define LCR_WLS0	(1 << 0)	/* Word Length Select */
-
-#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
-#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
-#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
-#define LSR_BI		(1 << 4)	/* Break Interrupt */
-#define LSR_FE		(1 << 3)	/* Framing Error */
-#define LSR_PE		(1 << 2)	/* Parity Error */
-#define LSR_OE		(1 << 1)	/* Overrun Error */
-#define LSR_DR		(1 << 0)	/* Data Ready */
-
-#define MCR_LOOP	(1 << 4)	*/
-#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
-#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
-#define MCR_RTS		(1 << 1)	/* Request to Send */
-#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
-
-#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
-#define MSR_RI		(1 << 6)	/* Ring Indicator */
-#define MSR_DSR		(1 << 5)	/* Data Set Ready */
-#define MSR_CTS		(1 << 4)	/* Clear To Send */
-#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
-#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
-#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
-#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
-
-#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
-/*
- * Peripheral Space Registers
- */
-#define IXP425_UART1_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP425_UART2_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP425_PMU_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP425_INTC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP425_GPIO_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP425_TIMER_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP425_NPEA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP425_NPEB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP425_NPEC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP425_EthA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP425_EthB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP425_USB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-
-/*
- * UART Register Definitions , Offsets only as there are 2 UARTS.
- *   IXP425_UART1_BASE , IXP425_UART2_BASE.
- */
-
-#undef  UART_NO_RX_INTERRUPT
-
-#define IXP425_UART_XTAL        14745600
-
-/*
- * Constants to make it easy to access  Interrupt Controller registers
- */
-#define IXP425_ICPR_OFFSET	0x00 /* Interrupt Status */
-#define IXP425_ICMR_OFFSET	0x04 /* Interrupt Enable */
-#define IXP425_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP425_ICIP_OFFSET      0x0C /* IRQ Status */
-#define IXP425_ICFP_OFFSET	0x10 /* FIQ Status */
-#define IXP425_ICHR_OFFSET	0x14 /* Interrupt Priority */
-#define IXP425_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
-#define IXP425_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
-
-#define N_IRQS			32
-#define IXP425_TIMER_2_IRQ	11
-
-/*
- * Interrupt Controller Register Definitions.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
-
-#define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
-#define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
-#define IXP425_ICLR     IXP425_INTC_REG(IXP425_ICLR_OFFSET)
-#define IXP425_ICIP     IXP425_INTC_REG(IXP425_ICIP_OFFSET)
-#define IXP425_ICFP     IXP425_INTC_REG(IXP425_ICFP_OFFSET)
-#define IXP425_ICHR     IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH     IXP425_INTC_REG(IXP425_ICIH_OFFSET)
-#define IXP425_ICFH     IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP425_GPIO_GPOUTR_OFFSET       0x00
-#define IXP425_GPIO_GPOER_OFFSET        0x04
-#define IXP425_GPIO_GPINR_OFFSET        0x08
-#define IXP425_GPIO_GPISR_OFFSET        0x0C
-#define IXP425_GPIO_GPIT1R_OFFSET	0x10
-#define IXP425_GPIO_GPIT2R_OFFSET	0x14
-#define IXP425_GPIO_GPCLKR_OFFSET	0x18
-#define IXP425_GPIO_GPDBSELR_OFFSET	0x1C
-
-/*
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
-
-#define IXP425_GPIO_GPOUTR	IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
-#define IXP425_GPIO_GPOER       IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
-#define IXP425_GPIO_GPINR       IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
-#define IXP425_GPIO_GPISR       IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
-#define IXP425_GPIO_GPIT1R      IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
-#define IXP425_GPIO_GPIT2R      IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
-#define IXP425_GPIO_GPCLKR      IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
-#define IXP425_GPIO_GPDBSELR    IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
-
-#define IXP425_GPIO_GPITR(line)	(((line) >= 8) ? \
-				IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
-
-/*
- * Macros to make it easy to access the GPIO registers
- */
-#define GPIO_OUTPUT_ENABLE(line)	*IXP425_GPIO_GPOER &= ~(1 << (line))
-#define GPIO_OUTPUT_DISABLE(line)	*IXP425_GPIO_GPOER |= (1 << (line))
-#define GPIO_OUTPUT_SET(line)		*IXP425_GPIO_GPOUTR |= (1 << (line))
-#define GPIO_OUTPUT_CLEAR(line)		*IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line)				\
-	*IXP425_GPIO_GPITR(line) =				\
-			(*IXP425_GPIO_GPITR(line) &		\
-			~(0x7 << (((line) & 0x7) * 3))) |	\
-			(0x1 << (((line) & 0x7) * 3))		\
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP425_OSTS_OFFSET	0x00  /* Continious TimeStamp */
-#define IXP425_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
-#define IXP425_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
-#define IXP425_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
-#define IXP425_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
-#define IXP425_OSWT_OFFSET	0x14  /* Watchdog Timer */
-#define IXP425_OSWE_OFFSET	0x18  /* Watchdog Enable */
-#define IXP425_OSWK_OFFSET	0x1C  /* Watchdog Key */
-#define IXP425_OSST_OFFSET	0x20  /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
-
-/* _B to avoid collision: also defined in npe/include/... */
-#define IXP425_OSTS_B	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
-#define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
-#define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)
-#define IXP425_OSRT2	IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
-#define IXP425_OSWT	IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
-#define IXP425_OSWE	IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
-#define IXP425_OSWK	IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
-#define IXP425_OSST	IXP425_TIMER_REG(IXP425_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions
- */
-#define IXP425_OST_ENABLE              BIT(0)
-#define IXP425_OST_ONE_SHOT            BIT(1)
-/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK         (0x3)
-#define IXP425_OST_DISABLED            (0x0)
-#define IXP425_OSST_TIMER_1_PEND       BIT(0)
-#define IXP425_OSST_TIMER_2_PEND       BIT(1)
-#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
-#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
-#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET            0x00
-#define PCI_NP_CBE_OFFSET           0x04
-#define PCI_NP_WDATA_OFFSET         0x08
-#define PCI_NP_RDATA_OFFSET         0x0c
-#define PCI_CRP_AD_CBE_OFFSET       0x10
-#define PCI_CRP_WDATA_OFFSET        0x14
-#define PCI_CRP_RDATA_OFFSET        0x18
-#define PCI_CSR_OFFSET              0x1c
-#define PCI_ISR_OFFSET              0x20
-#define PCI_INTEN_OFFSET            0x24
-#define PCI_DMACTRL_OFFSET          0x28
-#define PCI_AHBMEMBASE_OFFSET       0x2c
-#define PCI_AHBIOBASE_OFFSET        0x30
-#define PCI_PCIMEMBASE_OFFSET       0x34
-#define PCI_AHBDOORBELL_OFFSET      0x38
-#define PCI_PCIDOORBELL_OFFSET      0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET  0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
-
-#define PCI_NP_AD               IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE              IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA            IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA            IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE          IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA           IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA           IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR                 IXP425_PCI_CSR(PCI_CSR_OFFSET)
-#define PCI_ISR                 IXP425_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN               IXP425_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL             IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE          IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE           IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE          IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL         IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL         IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST		BIT(0)
-#define PCI_CSR_ARBEN		BIT(1)
-#define PCI_CSR_ADS		BIT(2)
-#define PCI_CSR_PDS		BIT(3)
-#define PCI_CSR_ABE		BIT(4)
-#define PCI_CSR_DBT		BIT(5)
-#define PCI_CSR_ASE		BIT(8)
-#define PCI_CSR_IC		BIT(15)
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE		BIT(0)
-#define PCI_ISR_PFE		BIT(1)
-#define PCI_ISR_PPE		BIT(2)
-#define PCI_ISR_AHBE		BIT(3)
-#define PCI_ISR_APDC		BIT(4)
-#define PCI_ISR_PADC		BIT(5)
-#define PCI_ISR_ADB		BIT(6)
-#define PCI_ISR_PDB		BIT(7)
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE		BIT(0)
-#define PCI_INTEN_PFE		BIT(1)
-#define PCI_INTEN_PPE		BIT(2)
-#define PCI_INTEN_AHBE		BIT(3)
-#define PCI_INTEN_APDC		BIT(4)
-#define PCI_INTEN_PADC		BIT(5)
-#define PCI_INTEN_ADB		BIT(6)
-#define PCI_INTEN_PDB		BIT(7)
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP425_PCI_NP_CBE_BESL	4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD		0x2
-#define NP_CMD_IOWRITE		0x3
-#define NP_CMD_CONFIGREAD	0xa
-#define NP_CMD_CONFIGWRITE	0xb
-#define NP_CMD_MEMREAD		0x6
-#define	NP_CMD_MEMWRITE		0x7
-
-#if 0
-#ifndef __ASSEMBLY__
-extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
-extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
-extern void ixp425_pci_init(void *);
-#endif
-#endif
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL         20
-#define CRP_AD_CBE_WRITE        BIT(16)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS   */
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h
deleted file mode 100644
index f499883..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425pci.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * IXP PCI Init
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _IXP425PCI_H
-#define _IXP425PCI_H
-
-#define OK	0
-#define ERROR	-1
-
-struct pci_controller;
-extern void pci_ixp_init(struct pci_controller *hose);
-
-/* Mask definitions*/
-#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
-
-#define PCI_NP_CBE_BESL	 (4)
-#define PCI_NP_AD_FUNCSL (8)
-
-/*Register addressing definitions for PCI controller configuration
-  and status registers*/
-
-#define PCI_CSR_BASE (0xC0000000)
-/*
-#define PCI_NP_AD_OFFSET       (0x00)
-#define PCI_NP_CBE_OFFSET      (0x04)
-#define PCI_NP_WDATA_OFFSET    (0x08)
-#define PCI_NP_RDATA_OFFSET    (0x0C)
-#define PCI_CRP_OFFSET	       (0x10)
-#define PCI_CRP_WDATA_OFFSET   (0x14)
-#define PCI_CRP_RDATA_OFFSET   (0x18)
-#define PCI_CSR_OFFSET	       (0x1C)
-#define PCI_ISR_OFFSET	       (0x20)
-#define PCI_INTEN_OFFSET       (0x24)
-#define PCI_DMACTRL_OFFSET     (0x28)
-#define PCI_AHBMEMBASE_OFFSET  (0x2C)
-#define PCI_AHBIOBASE_OFFSET   (0x30)
-#define PCI_PCIMEMBASE_OFFSET  (0x34)
-#define PCI_AHBDOORBELL_OFFSET (0x38)
-#define PCI_PCIDOORBELL_OFFSET (0x3C)
-#define PCI_ATPDMA0_AHBADDR    (0x40)
-#define PCI_ATPDMA0_PCIADDR    (0x44)
-#define PCI_ATPDMA0_LENADDR    (0x48)
-#define PCI_ATPDMA1_AHBADDR    (0x4C)
-#define PCI_ATPDMA1_PCIADDR    (0x50)
-#define PCI_ATPDMA1_LENADDR    (0x54)
-#define PCI_PTADMA0_AHBADDR    (0x58)
-#define PCI_PTADMA0_PCIADDR    (0x5C)
-#define PCI_PTADMA0_LENADDR    (0x60)
-#define PCI_PTADMA1_AHBADDR    (0x64)
-#define PCI_PTADMA1_PCIADDR    (0x68)
-#define PCI_PTADMA1_LENADDR    (0x6C)
-*/
-/*Non prefetch registers bit definitions*/
-/*
-#define NP_CMD_INTACK	   (0x0)
-#define NP_CMD_SPECIAL	   (0x1)
-#define NP_CMD_IOREAD	   (0x2)
-#define NP_CMD_IOWRITE	   (0x3)
-#define NP_CMD_MEMREAD	   (0x6)
-#define NP_CMD_MEMWRITE	   (0x7)
-#define NP_CMD_CONFIGREAD  (0xa)
-#define NP_CMD_CONFIGWRITE (0xb)
-*/
-
-/*Configuration Port register bit definitions*/
-#define PCI_CRP_WRITE BIT(16)
-
-/*ISR (Interrupt status) Register bit definitions*/
-#define PCI_ISR_PSE   BIT(0)
-#define PCI_ISR_PFE   BIT(1)
-#define PCI_ISR_PPE   BIT(2)
-#define PCI_ISR_AHBE  BIT(3)
-#define PCI_ISR_APDC  BIT(4)
-#define PCI_ISR_PADC  BIT(5)
-#define PCI_ISR_ADB   BIT(6)
-#define PCI_ISR_PDB   BIT(7)
-
-/*INTEN (Interrupt Enable) Register bit definitions*/
-#define PCI_INTEN_PSE	BIT(0)
-#define PCI_INTEN_PFE	BIT(1)
-#define PCI_INTEN_PPE	BIT(2)
-#define PCI_INTEN_AHBE	BIT(3)
-#define PCI_INTEN_APDC	BIT(4)
-#define PCI_INTEN_PADC	BIT(5)
-#define PCI_INTEN_ADB	BIT(6)
-#define PCI_INTEN_PDB	BIT(7)
-
-/*PCI configuration regs.*/
-
-#define PCI_CFG_VENDOR_ID	0x00
-#define PCI_CFG_DEVICE_ID	0x02
-#define PCI_CFG_COMMAND		0x04
-#define PCI_CFG_STATUS		0x06
-#define PCI_CFG_REVISION	0x08
-#define PCI_CFG_PROGRAMMING_IF	0x09
-#define PCI_CFG_SUBCLASS	0x0a
-#define PCI_CFG_CLASS		0x0b
-#define PCI_CFG_CACHE_LINE_SIZE 0x0c
-#define PCI_CFG_LATENCY_TIMER	0x0d
-#define PCI_CFG_HEADER_TYPE	0x0e
-#define PCI_CFG_BIST		0x0f
-#define PCI_CFG_BASE_ADDRESS_0	0x10
-#define PCI_CFG_BASE_ADDRESS_1	0x14
-#define PCI_CFG_BASE_ADDRESS_2	0x18
-#define PCI_CFG_BASE_ADDRESS_3	0x1c
-#define PCI_CFG_BASE_ADDRESS_4	0x20
-#define PCI_CFG_BASE_ADDRESS_5	0x24
-#define PCI_CFG_CIS		0x28
-#define PCI_CFG_SUB_VENDOR_ID	0x2c
-#define PCI_CFG_SUB_SYSTEM_ID	0x2e
-#define PCI_CFG_EXPANSION_ROM	0x30
-#define PCI_CFG_RESERVED_0	0x34
-#define PCI_CFG_RESERVED_1	0x38
-#define PCI_CFG_DEV_INT_LINE	0x3c
-#define PCI_CFG_DEV_INT_PIN	0x3d
-#define PCI_CFG_MIN_GRANT	0x3e
-#define PCI_CFG_MAX_LATENCY	0x3f
-#define PCI_CFG_SPECIAL_USE	0x41
-#define PCI_CFG_MODE		0x43
-
-#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
-#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
-#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
-#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */
-#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */
-#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */
-#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */
-#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */
-#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */
-#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable */
-
-
-/*CSR Register bit definitions*/
-#define PCI_CSR_HOST  BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS   BIT(2)
-#define PCI_CSR_PDS   BIT(3)
-#define PCI_CSR_ABE   BIT(4)
-#define PCI_CSR_DBT   BIT(5)
-#define PCI_CSR_ASE   BIT(8)
-#define PCI_CSR_IC    BIT(15)
-
-/*Configuration command bit definitions*/
-#define PCI_CFG_CMD_IOAE BIT(0)
-#define PCI_CFG_CMD_MAE	 BIT(1)
-#define PCI_CFG_CMD_BME	 BIT(2)
-#define PCI_CFG_CMD_MWIE BIT(4)
-#define PCI_CFG_CMD_SER	 BIT(8)
-#define PCI_CFG_CMD_FBBE BIT(9)
-#define PCI_CFG_CMD_MDPE BIT(24)
-#define PCI_CFG_CMD_STA	 BIT(27)
-#define PCI_CFG_CMD_RTA	 BIT(28)
-#define PCI_CFG_CMD_RMA	 BIT(29)
-#define PCI_CFG_CMD_SSE	 BIT(30)
-#define PCI_CFG_CMD_DPE	 BIT(31)
-
-/*DMACTRL DMA Control and status Register*/
-#define PCI_DMACTRL_APDCEN  BIT(0)
-#define PCI_DMACTRL_APDC0   BIT(4)
-#define PCI_DMACTRL_APDE0   BIT(5)
-#define PCI_DMACTRL_APDC1   BIT(6)
-#define PCI_DMACTRL_APDE1   BIT(7)
-#define PCI_DMACTRL_PADCEN  BIT(8)
-#define PCI_DMACTRL_PADC0   BIT(12)
-#define PCI_DMACTRL_PADE0   BIT(13)
-#define PCI_DMACTRL_PADC1   BIT(14)
-#define PCI_DMACTRL_PADE1   BIT(15)
-
-#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 60e8726..63e4ad5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -32,9 +32,6 @@ struct arch_global_data {
 	unsigned long tbl;
 	unsigned long lastinc;
 	unsigned long long timer_reset_value;
-#ifdef CONFIG_IXP425
-	unsigned long timestamp;
-#endif
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	unsigned long tlb_addr;
 	unsigned long tlb_size;
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index dfea54a..db9b402 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -29,9 +29,6 @@
 #include <asm/arch/gpio.h>
 #endif
 #endif
-#ifdef	CONFIG_IXP425			/* only valid for IXP425 */
-#include <asm/arch/ixp425.h>
-#endif
 #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
 #include <asm/io.h>
 #endif