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authorAnson Huang <Anson.Huang@nxp.com>2016-04-14 22:49:35 +0800
committerAnson Huang <Anson.Huang@nxp.com>2016-04-15 00:33:26 +0800
commitc5f3ebc2b4a3d01f2a923776450661787dd0aee3 (patch)
tree9c208f5ef5ac127b315ad5424dfe05265b436723
parent772af34b1216acc8e6a1a3faf43fef7c90b26a2f (diff)
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MLK-12658 imx: adjust POR_B setting on i.MX6ULL
Adjust POR_B settings on i.MX6ULL according to design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index a1d7721..ee832a3 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -490,6 +490,20 @@ int arch_cpu_init(void)
}
}
+ if (is_cpu_type(MXC_CPU_MX6ULL)) {
+ /*
+ * GPBIT[1:0] is suggested to set to 2'b11:
+ * 2'b00 : always PUP100K
+ * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
+ * 2'b10 : always disable PUP100K
+ * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
+ * register offset is different from i.MX6UL, since
+ * i.MX6UL is fixed by ECO.
+ */
+ writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
+ 0x3, MX6UL_SNVS_LP_BASE_ADDR);
+ }
+
/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
set_preclk_from_osc();