MLK-12929 imx6ull: support splash screen for epdc

add splash screen feature for epdc.
it's tested on imx6ull arm2 board.

Signed-off-by: Robby Cai <robby.cai@nxp.com>

7 files changed, 322 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index c289a14..0cb576f 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1372,6 +1372,35 @@ void enable_ipu_clock(void)
 	}
 }
 
+#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_MX6ULL)
+void enable_epdc_clock(void)
+{
+	u32 reg = 0;
+
+	/* disable the clock gate first */
+	clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
+
+	/* PLL3_PFD2 */
+	reg = readl(&imx_ccm->chsccdr);
+	reg &= ~MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK;
+	reg |= 5 << MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET;
+	writel(reg, &imx_ccm->chsccdr);
+
+	reg = readl(&imx_ccm->chsccdr);
+	reg &= ~MXC_CCM_CHSCCDR_EPDC_PODF_MASK;
+	reg |= 7 << MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET;
+	writel(reg, &imx_ccm->chsccdr);
+
+	reg = readl(&imx_ccm->chsccdr);
+	reg &= ~MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK;
+	reg |= 0 <<MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET;
+	writel(reg, &imx_ccm->chsccdr);
+
+	/* enable the clock gate */
+	setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
+}
+#endif
+
 /***************************************************/
 
 U_BOOT_CMD(
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 9101b83..d789159 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -72,6 +72,7 @@ int enable_lcdif_clock(u32 base_addr);
 int enable_lvds_bridge(u32 lcd_base_addr);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
+void enable_epdc_clock(void);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
 void mxs_set_vadcclk(void);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
index 2138b00..85f3dce 100644
--- a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
@@ -430,6 +430,7 @@ enum {
 	MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08                    = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA0__KPP_ROW04                     = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR                  = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08                   = IOMUX_PAD(0x0370, 0x00E4, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01                 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX                  = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
@@ -440,6 +441,7 @@ enum {
 	MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09                    = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA1__KPP_COL04                     = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC                   = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
+	MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09                   = IOMUX_PAD(0x0374, 0x00E8, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN                      = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_EN__UART7_DCE_TX                     = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
@@ -450,6 +452,7 @@ enum {
 	MX6_PAD_ENET2_RX_EN__GPIO2_IO10                       = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_EN__KPP_ROW05                        = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M                = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__EPDC_SDDO10                      = IOMUX_PAD(0x0378, 0x00EC, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00                 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX                  = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
@@ -459,6 +462,7 @@ enum {
 	MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02                    = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11                    = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__KPP_COL05                     = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11                   = IOMUX_PAD(0x037C, 0x00F0, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01                 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX                  = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
@@ -469,6 +473,7 @@ enum {
 	MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12                    = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA1__KPP_ROW06                     = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR                  = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12                   = IOMUX_PAD(0x0380, 0x00F4, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN                      = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX                     = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
@@ -479,6 +484,7 @@ enum {
 	MX6_PAD_ENET2_TX_EN__GPIO2_IO13                       = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_EN__KPP_COL06                        = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_EN__USB_OTG2_OC                      = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
+	MX6_PAD_ENET2_TX_EN__EPDC_SDDO13                      = IOMUX_PAD(0x0384, 0x00F8, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK                    = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS                   = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
@@ -489,6 +495,7 @@ enum {
 	MX6_PAD_ENET2_TX_CLK__GPIO2_IO14                      = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_CLK__KPP_ROW07                       = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID                  = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
+	MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14                     = IOMUX_PAD(0x0388, 0x00FC, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER                      = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS                    = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
@@ -499,6 +506,7 @@ enum {
 	MX6_PAD_ENET2_RX_ER__GPIO2_IO15                       = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_ER__KPP_COL07                        = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY                   = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__EPDC_SDDO15                      = IOMUX_PAD(0x038C, 0x0100, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_CLK__LCDIF_CLK                            = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_CLK__LCDIF_WR_RWN                         = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
@@ -508,6 +516,7 @@ enum {
 	MX6_PAD_LCD_CLK__EIM_CS2_B                            = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_CLK__GPIO3_IO00                           = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                 = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__EPDC_SDCLK                           = IOMUX_PAD(0x0390, 0x0104, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE                      = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_ENABLE__LCDIF_RD_E                        = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
@@ -517,6 +526,7 @@ enum {
 	MX6_PAD_LCD_ENABLE__EIM_CS3_B                         = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_ENABLE__GPIO3_IO01                        = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_ENABLE__ECSPI2_RDY                        = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__EPDC_SDLE                         = IOMUX_PAD(0x0394, 0x0108, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC                        = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
 	MX6_PAD_LCD_HSYNC__LCDIF_RS                           = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
@@ -526,6 +536,7 @@ enum {
 	MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB               = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_HSYNC__GPIO3_IO02                         = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_HSYNC__ECSPI2_SS1                         = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__EPDC_SDOE                          = IOMUX_PAD(0x0398, 0x010C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC                        = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_VSYNC__LCDIF_BUSY                         = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
@@ -535,6 +546,7 @@ enum {
 	MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B                       = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_VSYNC__GPIO3_IO03                         = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_VSYNC__ECSPI2_SS2                         = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__EPDC_SDCE0                         = IOMUX_PAD(0x039C, 0x0110, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_RESET__LCDIF_RESET                        = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_RESET__LCDIF_CS                           = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
@@ -543,6 +555,7 @@ enum {
 	MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_RESET__GPIO3_IO04                         = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_RESET__ECSPI2_SS3                         = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__EPDC_GDOE                          = IOMUX_PAD(0x03A0, 0x0114, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA00__LCDIF_DATA00                      = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__PWM1_OUT                          = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
@@ -551,6 +564,7 @@ enum {
 	MX6_PAD_LCD_DATA00__GPIO3_IO05                        = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__SRC_BT_CFG00                      = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__SAI1_MCLK                         = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
+	MX6_PAD_LCD_DATA00__EPDC_SDDO00                       = IOMUX_PAD(0x03A4, 0x0118, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA01__LCDIF_DATA01                      = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__PWM2_OUT                          = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
@@ -559,6 +573,7 @@ enum {
 	MX6_PAD_LCD_DATA01__GPIO3_IO06                        = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__SRC_BT_CFG01                      = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__SAI1_TX_SYNC                      = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
+	MX6_PAD_LCD_DATA01__EPDC_SDDO01                       = IOMUX_PAD(0x03A8, 0x011C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA02__LCDIF_DATA02                      = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__PWM3_OUT                          = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
@@ -567,6 +582,7 @@ enum {
 	MX6_PAD_LCD_DATA02__GPIO3_IO07                        = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__SRC_BT_CFG02                      = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__SAI1_TX_BCLK                      = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
+	MX6_PAD_LCD_DATA02__EPDC_SDDO02                       = IOMUX_PAD(0x03AC, 0x0120, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA03__LCDIF_DATA03                      = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__PWM4_OUT                          = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
@@ -575,6 +591,7 @@ enum {
 	MX6_PAD_LCD_DATA03__GPIO3_IO08                        = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__SRC_BT_CFG03                      = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__SAI1_RX_DATA                      = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
+	MX6_PAD_LCD_DATA03__EPDC_SDDO03                       = IOMUX_PAD(0x03B0, 0x0124, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA04__LCDIF_DATA04                      = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__UART8_DCE_CTS                     = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
@@ -584,6 +601,7 @@ enum {
 	MX6_PAD_LCD_DATA04__GPIO3_IO09                        = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__SRC_BT_CFG04                      = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__SAI1_TX_DATA                      = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__EPDC_SDDO04                       = IOMUX_PAD(0x03B4, 0x0128, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA05__LCDIF_DATA05                      = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__UART8_DCE_RTS                     = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
@@ -593,6 +611,7 @@ enum {
 	MX6_PAD_LCD_DATA05__GPIO3_IO10                        = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__SRC_BT_CFG05                      = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__ECSPI1_SS1                        = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__EPDC_SDDO05                       = IOMUX_PAD(0x03B8, 0x012C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA06__LCDIF_DATA06                      = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__UART7_DCE_CTS                     = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
@@ -602,6 +621,7 @@ enum {
 	MX6_PAD_LCD_DATA06__GPIO3_IO11                        = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__SRC_BT_CFG06                      = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__ECSPI1_SS2                        = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__EPDC_SDDO06                       = IOMUX_PAD(0x03BC, 0x0130, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA07__LCDIF_DATA07                      = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__UART7_DCE_RTS                     = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
@@ -611,6 +631,7 @@ enum {
 	MX6_PAD_LCD_DATA07__GPIO3_IO12                        = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__SRC_BT_CFG07                      = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__ECSPI1_SS3                        = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__EPDC_SDDO07                       = IOMUX_PAD(0x03C0, 0x0134, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA08__LCDIF_DATA08                      = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA08__SPDIF_IN                          = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
@@ -667,6 +688,7 @@ enum {
 	MX6_PAD_LCD_DATA14__GPIO3_IO19                        = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA14__SRC_BT_CFG14                      = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA14__USDHC2_DATA4                      = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
+	MX6_PAD_LCD_DATA14__EPDC_SDSHR                        = IOMUX_PAD(0x03DC, 0x0150, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA15__LCDIF_DATA15                      = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__SAI3_TX_DATA                      = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
@@ -675,6 +697,7 @@ enum {
 	MX6_PAD_LCD_DATA15__GPIO3_IO20                        = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__SRC_BT_CFG15                      = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__USDHC2_DATA5                      = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
+	MX6_PAD_LCD_DATA15__EPDC_GDRL                         = IOMUX_PAD(0x03E0, 0x0154, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA16__LCDIF_DATA16                      = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__UART7_DCE_TX                      = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
@@ -684,6 +707,7 @@ enum {
 	MX6_PAD_LCD_DATA16__GPIO3_IO21                        = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__SRC_BT_CFG24                      = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__USDHC2_DATA6                      = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
+	MX6_PAD_LCD_DATA16__EPDC_GDCLK                        = IOMUX_PAD(0x03E4, 0x0158, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA17__LCDIF_DATA17                      = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__UART7_DCE_RX                      = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
@@ -693,6 +717,7 @@ enum {
 	MX6_PAD_LCD_DATA17__GPIO3_IO22                        = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__SRC_BT_CFG25                      = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__USDHC2_DATA7                      = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
+	MX6_PAD_LCD_DATA17__EPDC_GDSP                         = IOMUX_PAD(0x03E8, 0x015C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA18__LCDIF_DATA18                      = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA18__PWM5_OUT                          = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
@@ -731,6 +756,7 @@ enum {
 	MX6_PAD_LCD_DATA21__GPIO3_IO26                        = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA21__SRC_BT_CFG29                      = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA21__USDHC2_DATA1                      = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
+	MX6_PAD_LCD_DATA21__EPDC_SDCE1                        = IOMUX_PAD(0x03F8, 0x016C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA22__LCDIF_DATA22                      = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA22__MQS_RIGHT                         = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
diff --git a/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c b/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
index 5b8369e..58c354d 100644
--- a/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
+++ b/board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
@@ -29,6 +29,10 @@
 #include "../common/pfuze.h"
 #include <usb.h>
 #include <usb/ehci-fsl.h>
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
 #include <asm/imx-common/video.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -80,6 +84,8 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define EPDC_PAD_CTRL	0x010b1
+
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC and EEPROM */
@@ -546,6 +552,216 @@ struct display_info_t const displays[] = {{
 size_t display_count = ARRAY_SIZE(displays);
 #endif
 
+#ifdef CONFIG_MXC_EPDC
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__EPDC_SDDO10	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__EPDC_SDDO13	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__EPDC_SDDO15	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_CLK__EPDC_SDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__EPDC_SDDO00	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__EPDC_SDDO01	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__EPDC_SDDO02	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__EPDC_SDDO03	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__EPDC_SDDO04	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__EPDC_SDDO05	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__EPDC_SDDO06	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__EPDC_SDDO07	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__EPDC_SDSHR	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__EPDC_GDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_RESET__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08,
+	MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09,
+	MX6_PAD_ENET2_RX_EN__GPIO2_IO10,
+	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11,
+	MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12,
+	MX6_PAD_ENET2_TX_EN__GPIO2_IO13,
+	MX6_PAD_ENET2_TX_CLK__GPIO2_IO14,
+	MX6_PAD_ENET2_RX_ER__GPIO2_IO15,
+	MX6_PAD_LCD_CLK__GPIO3_IO00,
+	MX6_PAD_LCD_ENABLE__GPIO3_IO01,
+	MX6_PAD_LCD_HSYNC__GPIO3_IO02,
+	MX6_PAD_LCD_VSYNC__GPIO3_IO03,
+	MX6_PAD_LCD_DATA00__GPIO3_IO05,
+	MX6_PAD_LCD_DATA01__GPIO3_IO06,
+	MX6_PAD_LCD_DATA02__GPIO3_IO07,
+	MX6_PAD_LCD_DATA03__GPIO3_IO08,
+	MX6_PAD_LCD_DATA04__GPIO3_IO09,
+	MX6_PAD_LCD_DATA05__GPIO3_IO10,
+	MX6_PAD_LCD_DATA06__GPIO3_IO11,
+	MX6_PAD_LCD_DATA07__GPIO3_IO12,
+	MX6_PAD_LCD_DATA14__GPIO3_IO19,
+	MX6_PAD_LCD_DATA15__GPIO3_IO20,
+	MX6_PAD_LCD_DATA16__GPIO3_IO21,
+	MX6_PAD_LCD_DATA17__GPIO3_IO22,
+	MX6_PAD_LCD_RESET__GPIO3_IO04,
+};
+
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 1024,
+	.vl_row = 758,
+	.vl_pixclock = 40000000,
+	.vl_left_margin = 12,
+	.vl_right_margin = 76,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 5,
+	.vl_hsync = 12,
+	.vl_vsync = 2,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 524,
+	.gdsp_offs = 327,
+	.gdoe_offs = 0,
+	.gdclk_offs = 19,
+	.num_ce = 1,
+};
+
+static void setup_epdc_power(void)
+{
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA11__GPIO3_IO16 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	gpio_direction_input(IMX_GPIO_NR(3, 16));
+
+	/* EPDC_VCOM0 - GPIO3[24] for VCOM control */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA19__GPIO3_IO24 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set as output */
+	gpio_direction_output(IMX_GPIO_NR(3, 24), 1);
+
+	/* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA09__GPIO3_IO14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
+
+	/* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA12__GPIO3_IO17 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
+				ARRAY_SIZE(epdc_enable_pads));
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
+				ARRAY_SIZE(epdc_disable_pads));
+}
+
+static void setup_epdc(void)
+{
+	/*** epdc Maxim PMIC settings ***/
+
+	/* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA11__GPIO3_IO16 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_VCOM0 - GPIO3[24] for VCOM control */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA19__GPIO3_IO24 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA09__GPIO3_IO14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA12__GPIO3_IO17 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set pixel clock rates for EPDC in clock.c */
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO3_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(3, 17), 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	gpio_set_value(IMX_GPIO_NR(3, 14), 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 16)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	gpio_set_value(IMX_GPIO_NR(3, 24), 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	gpio_set_value(IMX_GPIO_NR(3, 14), 0);
+
+	/* Disable VCOM */
+	gpio_set_value(IMX_GPIO_NR(3, 24), 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(3, 17), 0);
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int board_eth_init(bd_t *bis)
 {
@@ -753,6 +969,11 @@ int board_init(void)
 	board_qspi_init();
 #endif
 
+#ifdef	CONFIG_MXC_EPDC
+	enable_epdc_clock();
+	setup_epdc();
+#endif
+
 	return 0;
 }
 
diff --git a/configs/mx6ull_14x14_ddr3_arm2_epdc_defconfig b/configs/mx6ull_14x14_ddr3_arm2_epdc_defconfig
new file mode 100644
index 0000000..e50583d
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_arm2_epdc_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,MXC_EPDC"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
+CONFIG_CMD_GPIO=y
diff --git a/include/configs/mx6ull_ddr3_arm2.h b/include/configs/mx6ull_ddr3_arm2.h
index 28562db..9325d33 100644
--- a/include/configs/mx6ull_ddr3_arm2.h
+++ b/include/configs/mx6ull_ddr3_arm2.h
@@ -87,4 +87,43 @@
 #define CONFIG_FEC_DMA_MINALIGN		64
 #endif
 
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+/* #define CONFIG_SPLASH_SCREEN*/
+/* #define CONFIG_MXC_EPDC*/
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
+/*
+ * Framebuffer and LCD
+ */
+#define	CONFIG_CFB_CONSOLE
+#define CONFIG_CMD_BMP
+#define CONFIG_LCD
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#undef LCD_TEST_PATTERN
+/* #define CONFIG_SPLASH_IS_IN_MMC			1 */
+#define LCD_BPP					LCD_MONOCHROME
+/* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
+
+#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif
+
 #endif
diff --git a/include/mxc_epdc_fb.h b/include/mxc_epdc_fb.h
index 33761a7..7594958 100644
--- a/include/mxc_epdc_fb.h
+++ b/include/mxc_epdc_fb.h
@@ -193,7 +193,7 @@
 #define EPDC_PIGEON_16_0		0xC00
 #define EPDC_PIGEON_16_1		0xC10
 #define EPDC_PIGEON_16_2		0xC20
-#ifdef CONFIG_MX7
+#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL)
 #define EPDC_WB_ADDR_TCE		0x010
 #else
 #define EPDC_WB_ADDR_TCE		0xC10