summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorBai Ping <ping.bai@nxp.com>2016-08-25 18:26:38 +0800
committerBai Ping <ping.bai@nxp.com>2016-08-25 21:30:35 +0800
commit911fcf93bad8c0a595c350b92f107b626029559b (patch)
tree7259ba62692f2b429338ac9884858c9d4c490e6b
parent44a84b44a84cd1bdcc54d722987e5f109510891b (diff)
downloadu-boot-imx-911fcf93bad8c0a595c350b92f107b626029559b.zip
u-boot-imx-911fcf93bad8c0a595c350b92f107b626029559b.tar.gz
u-boot-imx-911fcf93bad8c0a595c350b92f107b626029559b.tar.bz2
MLK-13124 ARM: imx: update the REFTOP_VBGADJ setting
Per to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000' - set REFTOP_VBGADJ[2:0] to 3b'110 '110' - set REFTOP_VBGADJ[2:0] to 3b'000 '001' - set REFTOP_VBGADJ[2:0] to 3b'001 '010' - set REFTOP_VBGADJ[2:0] to 3b'010 '011' - set REFTOP_VBGADJ[2:0] to 3b'011 '100' - set REFTOP_VBGADJ[2:0] to 3b'100 '101' - set REFTOP_VBGADJ[2:0] to 3b'101 '111' - set REFTOP_VBGADJ[2:0] to 3b'111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c36
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h2
2 files changed, 32 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 1f3e145..9ecee77 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -310,9 +310,17 @@ static void clear_mmdc_ch_mask(void)
writel(reg, &mxc_ccm->ccdr);
}
+#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
+
static void init_bandgap(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
/*
* Ensure the bandgap has stabilized.
*/
@@ -325,14 +333,32 @@ static void init_bandgap(void)
*/
writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
/*
- * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
- * VBGADJ bits to 2b'110 to adjust it.
+ * On i.MX6ULL,we need to set VBGADJ bits according to the
+ * REFTOP_TRIM[3:0] in fuse table
+ * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
+ * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
+ * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
+ * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
+ * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
+ * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
+ * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
+ * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
*/
- if (is_cpu_type(MXC_CPU_MX6ULL))
- writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
+ if (is_cpu_type(MXC_CPU_MX6ULL)) {
+ val = readl(&fuse->mem0);
+ val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
+ val &= 0x7;
+
+ if (val == 0) {
+ val = 6;
+ } else if (val == 6) {
+ val = 0;
+ }
+ writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+ &anatop->ana_misc0_set);
+ }
}
-
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index bc4f39e..c85e918 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1272,7 +1272,7 @@ struct mxc_ccm_reg {
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
-#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
#define BP_PMU_MISC2_AUDIO_DIV_MSB 23