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authorHaibo Chen <haibo.chen@nxp.com>2016-05-24 16:34:31 +0800
committerHaibo Chen <haibo.chen@nxp.com>2016-05-24 18:21:09 +0800
commit8cdf030f2c12d26ea555708175540916a3ac9090 (patch)
tree59b0de737d0dac23d937d83842a945abed717c22
parentdf339c7bdb189aeedfcac2783b5021c623916c6f (diff)
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MLK-12848: mx6ull_14x14_ddr3_arm2: add new TSC config
Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2 board, disable PMIC and ldo bypass check. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
-rw-r--r--configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig5
-rw-r--r--include/configs/mx6ull_ddr3_arm2.h16
2 files changed, 21 insertions, 0 deletions
diff --git a/configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig b/configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig
new file mode 100644
index 0000000..7092752
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_arm2_tsc_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_arm2/imximage.cfg,MX6ULL_DDR3_ARM2_TSC_REWORK"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6ULL_DDR3_ARM2=y
+CONFIG_CMD_GPIO=y
diff --git a/include/configs/mx6ull_ddr3_arm2.h b/include/configs/mx6ull_ddr3_arm2.h
index 9e20d33..28562db 100644
--- a/include/configs/mx6ull_ddr3_arm2.h
+++ b/include/configs/mx6ull_ddr3_arm2.h
@@ -36,6 +36,22 @@
#define PHYS_SDRAM_SIZE SZ_1G
+/*
+ * TSC pins conflict with I2C1 bus, so after TSC
+ * hardware rework, need to disable i2c1 bus, also
+ * need to disable PMIC and ldo bypass check.
+ */
+#ifdef CONFIG_MX6ULL_DDR3_ARM2_TSC_REWORK
+#undef CONFIG_LDO_BYPASS_CHECK
+#undef CONFIG_SYS_I2C_MXC
+#undef CONFIG_SYS_I2C
+#undef CONFIG_CMD_I2C
+#undef CONFIG_POWER_PFUZE100_I2C_ADDR
+#undef CONFIG_POWER_PFUZE100
+#undef CONFIG_POWER_I2C
+#undef CONFIG_POWER
+#endif
+
#ifdef CONFIG_SYS_USE_SPINOR
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH