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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2014-10-28 11:22:19 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2015-01-26 08:55:57 +0100 |
| commit | f60c6fbbc658201f968a22addff7dd1acbe5eaca (patch) | |
| tree | 36232fa5b868ef1572a9da4baebe235c84b5ac84 | |
| parent | 3ad87ca18203f8b0de0e30b7c12d2ffadf2d8553 (diff) | |
| download | u-boot-imx-f60c6fbbc658201f968a22addff7dd1acbe5eaca.zip u-boot-imx-f60c6fbbc658201f968a22addff7dd1acbe5eaca.tar.gz u-boot-imx-f60c6fbbc658201f968a22addff7dd1acbe5eaca.tar.bz2 | |
ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 934ccc3..2521589 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void) zynq_slcr_unlock(); /* Disable AXI interface by asserting FPGA resets */ - writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); + writel(0xF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ writel(0xA, &slcr_base->lvl_shftr_en); |