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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-03-30 17:01:06 -0500 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-04-21 12:23:16 +0200 |
| commit | 9fd565dbe7eadc9736c496bc67f2a0414b50069f (patch) | |
| tree | 190f0d4108856c51fa764c3e2d9ddbae03593635 | |
| parent | 0812a1d3e5d056b012d6a9b4b2e83469440f7018 (diff) | |
| download | u-boot-imx-9fd565dbe7eadc9736c496bc67f2a0414b50069f.zip u-boot-imx-9fd565dbe7eadc9736c496bc67f2a0414b50069f.tar.gz u-boot-imx-9fd565dbe7eadc9736c496bc67f2a0414b50069f.tar.bz2 | |
arm: socfpga: spl: Add call to timer_init
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| -rw-r--r-- | arch/arm/cpu/armv7/socfpga/spl.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index a4dbe4f..95992f0 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -148,6 +148,8 @@ void spl_board_init(void) socfpga_uart0_enable(); socfpga_osc1timer_enable(); + timer_init(); + debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); |