powerpc: ppc4xx: remove lwmon5 support

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Remove CONFIG_LWMON5 references.
(Also, remove undefined CONFIG_WD_MAX_RATE while I am here.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>

15 files changed, 2 insertions, 2128 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index c6bbe12..883463a 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -8,10 +8,6 @@ choice
 	prompt "Target select"
 	optional
 
-config TARGET_LWMON5
-	bool "Support lwmon5"
-	select SUPPORT_SPL
-
 config TARGET_PCS440EP
 	bool "Support pcs440ep"
 
@@ -181,7 +177,6 @@ source "board/gdsys/405ex/Kconfig"
 source "board/gdsys/dlvision/Kconfig"
 source "board/gdsys/gdppc440etx/Kconfig"
 source "board/gdsys/intip/Kconfig"
-source "board/lwmon5/Kconfig"
 source "board/mosaixtech/icon/Kconfig"
 source "board/mpl/mip405/Kconfig"
 source "board/mpl/pip405/Kconfig"
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 4090975..2527ef8 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -106,12 +106,6 @@ struct arch_global_data {
 #ifdef CONFIG_SYS_FPGA_COUNT
 	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
 #endif
-#if defined(CONFIG_WD_MAX_RATE)
-	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
-#endif
-#if defined(CONFIG_LWMON5)
-	unsigned long kbd_status;
-#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/board/lwmon5/Kconfig b/board/lwmon5/Kconfig
deleted file mode 100644
index 90566d8..0000000
--- a/board/lwmon5/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_LWMON5
-
-config SYS_BOARD
-	default "lwmon5"
-
-config SYS_CONFIG_NAME
-	default "lwmon5"
-
-endif
diff --git a/board/lwmon5/MAINTAINERS b/board/lwmon5/MAINTAINERS
deleted file mode 100644
index 7402ab6..0000000
--- a/board/lwmon5/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-LWMON5 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/lwmon5/
-F:	include/configs/lwmon5.h
-F:	configs/lcd4_lwmon5_defconfig
-F:	configs/lwmon5_defconfig
diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile
deleted file mode 100644
index 02478ca..0000000
--- a/board/lwmon5/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= lwmon5.o kbd.o sdram.o
-extra-y	+= init.o
diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk
deleted file mode 100644
index d0348e8..0000000
--- a/board/lwmon5/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# lwmon5 (440EPx)
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
deleted file mode 100644
index e5207c2..0000000
--- a/board/lwmon5/init.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
-	/* TLB-entry for PCI Memory */
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
-
-	/* TLB-entry for the FPGA Chip select 2 */
-	tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for the FPGA Chip select 3 */
-	tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for the LIME Controller */
-	tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for Internal Registers & OCM */
-	tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I)
-
-	/*TLB-entry PCI registers*/
-	tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG)
-
-	/* TLB-entry for peripherals */
-	tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
-	tlbtab_end
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
deleted file mode 100644
index 97962da..0000000
--- a/board/lwmon5/kbd.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2001, 2002
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <i2c.h>
-#include <command.h>
-#include <post.h>
-#include <serial.h>
-#include <malloc.h>
-
-#include <linux/types.h>
-#include <linux/string.h>	/* for strdup */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void kbd_init (void);
-static int compare_magic (uchar *kbd_data, uchar *str);
-
-/*--------------------- Local macros and constants --------------------*/
-#define	_NOT_USED_	0xFFFFFFFF
-
-/*------------------------- dspic io expander -----------------------*/
-#define DSPIC_PON_STATUS_REG	0x80A
-#define DSPIC_PON_INV_STATUS_REG 0x80C
-#define DSPIC_PON_KEY_REG	0x810
-/*------------------------- Keyboard controller -----------------------*/
-/* command codes */
-#define	KEYBD_CMD_READ_KEYS	0x01
-#define KEYBD_CMD_READ_VERSION	0x02
-#define KEYBD_CMD_READ_STATUS	0x03
-#define KEYBD_CMD_RESET_ERRORS	0x10
-
-/* status codes */
-#define KEYBD_STATUS_MASK	0x3F
-#define	KEYBD_STATUS_H_RESET	0x20
-#define KEYBD_STATUS_BROWNOUT	0x10
-#define KEYBD_STATUS_WD_RESET	0x08
-#define KEYBD_STATUS_OVERLOAD	0x04
-#define KEYBD_STATUS_ILLEGAL_WR	0x02
-#define KEYBD_STATUS_ILLEGAL_RD	0x01
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_VERSIONLEN	2	/* version information */
-
-/*
- * This is different from the "old" lwmon dsPIC kbd controller
- * implementation. Now the controller still answers with 9 bytes,
- * but the last 3 bytes are always "0x06 0x07 0x08". So we just
- * set the length to compare to 6 instead of 9.
- */
-#define	KEYBD_DATALEN		6	/* normal key scan data */
-
-/* maximum number of "magic" key codes that can be assigned */
-
-static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
-static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
-
-static uchar *key_match (uchar *);
-
-#define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output */
-
-/***********************************************************************
-F* Function:     int board_postclk_init (void) P*A*Z*
- *
-P* Parameters:   none
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned.
- *
-Z* Intention:    This function is the board_postclk_init() method implementation
-Z*               for the lwmon board.
- *
- ***********************************************************************/
-int board_postclk_init (void)
-{
-	kbd_init();
-
-	return (0);
-}
-
-static void kbd_init (void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	uchar tmp_data[KEYBD_DATALEN];
-	uchar val, errcd;
-	int i;
-
-	i2c_set_bus_num(0);
-
-	gd->arch.kbd_status = 0;
-
-	/* Forced by PIC. Delays <= 175us loose */
-	udelay(1000);
-
-	/* Read initial keyboard error code */
-	val = KEYBD_CMD_READ_STATUS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, &errcd, 1);
-	/* clear unused bits */
-	errcd &= KEYBD_STATUS_MASK;
-	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
-	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
-	if (errcd) {
-		gd->arch.kbd_status |= errcd << 8;
-	}
-	/* Reset error code and verify */
-	val = KEYBD_CMD_RESET_ERRORS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	udelay(1000);	/* delay NEEDED by keyboard PIC !!! */
-
-	val = KEYBD_CMD_READ_STATUS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, &val, 1);
-
-	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
-	if (val) {			/* permanent error, report it */
-		gd->arch.kbd_status |= val;
-		return;
-	}
-
-	/*
-	 * Read current keyboard state.
-	 *
-	 * After the error reset it may take some time before the
-	 * keyboard PIC picks up a valid keyboard scan - the total
-	 * scan time is approx. 1.6 ms (information by Martin Rajek,
-	 * 28 Sep 2002). We read a couple of times for the keyboard
-	 * to stabilize, using a big enough delay.
-	 * 10 times should be enough. If the data is still changing,
-	 * we use what we get :-(
-	 */
-
-	memset (tmp_data, 0xFF, KEYBD_DATALEN);	/* impossible value */
-	for (i=0; i<10; ++i) {
-		val = KEYBD_CMD_READ_KEYS;
-		i2c_write (kbd_addr, 0, 0, &val, 1);
-		i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-		if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
-			/* consistent state, done */
-			break;
-		}
-		/* remeber last state, delay, and retry */
-		memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
-		udelay (5000);
-	}
-}
-
-
-/* Read a register from the dsPIC. */
-int _dspic_read(ushort reg, ushort *data)
-{
-	uchar buf[sizeof(*data)];
-	int rval;
-
-	if (i2c_read(dspic_addr, reg, 2, buf, 2))
-		return -1;
-
-	rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
-	*data = (buf[0] << 8) | buf[1];
-
-	return rval;
-}
-
-
-/***********************************************************************
-F* Function:     int misc_init_r (void) P*A*Z*
- *
-P* Parameters:   none
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned, even in the case of a keyboard
-P*                    error.
- *
-Z* Intention:    This function is the misc_init_r() method implementation
-Z*               for the lwmon board.
-Z*               The keyboard controller is initialized and the result
-Z*               of a read copied to the environment variable "keybd".
-Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z*               this key, and if found display to the LCD will be enabled.
-Z*               The keys in "keybd" are checked against the magic
-Z*               keycommands defined in the environment.
-Z*               See also key_match().
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int misc_init_r_kbd (void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar kbd_init_status = gd->arch.kbd_status >> 8;
-	uchar kbd_status = gd->arch.kbd_status;
-	uchar val;
-	ushort data, inv_data;
-	char *str;
-	int i;
-
-	if (kbd_init_status) {
-		printf ("KEYBD: Error %02X\n", kbd_init_status);
-	}
-	if (kbd_status) {		/* permanent error, report it */
-		printf ("*** Keyboard error code %02X ***\n", kbd_status);
-		sprintf (keybd_env, "%02X", kbd_status);
-		setenv ("keybd", keybd_env);
-		return 0;
-	}
-
-	/*
-	 * Now we know that we have a working  keyboard,  so  disable
-	 * all output to the LCD except when a key press is detected.
-	 */
-
-	if ((console_assign (stdout, "serial") < 0) ||
-		(console_assign (stderr, "serial") < 0)) {
-		printf ("Can't assign serial port as output device\n");
-	}
-
-	/* Read Version */
-	val = KEYBD_CMD_READ_VERSION;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
-	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
-	/* Read current keyboard state */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	/* read out start key from bse01 received via can */
-	_dspic_read(DSPIC_PON_STATUS_REG, &data);
-	/* check highbyte from status register */
-	if (data > 0xFF) {
-		_dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
-
-		/* check inverse data */
-		if ((data+inv_data) == 0xFFFF) {
-			/* don't overwrite local key */
-			if (kbd_data[1] == 0) {
-				/* read key value */
-				_dspic_read(DSPIC_PON_KEY_REG, &data);
-				str = (char *)&data;
-				/* swap bytes */
-				kbd_data[1] = str[1];
-				kbd_data[2] = str[0];
-				printf("CAN received startkey: 0x%X\n", data);
-			}
-		}
-	}
-
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-	}
-
-	setenv ("keybd", keybd_env);
-
-	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
-#ifdef KEYBD_SET_DEBUGMODE
-	if (kbd_data[0] == KEYBD_SET_DEBUGMODE) {	/* set debug mode */
-		if ((console_assign (stdout, "lcd") < 0) ||
-			(console_assign (stderr, "lcd") < 0)) {
-			printf ("Can't assign LCD display as output device\n");
-		}
-	}
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
-	setenv ("preboot", str);	/* set or delete definition */
-#endif /* CONFIG_PREBOOT */
-	if (str != NULL) {
-		free (str);
-	}
-	return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
-	uchar compare[KEYBD_DATALEN-1];
-	char *nxt;
-	int i;
-
-	/* Don't include modifier byte */
-	memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
-	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
-		uchar c;
-		int k;
-
-		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
-		if (str == (uchar *)nxt) {	/* invalid character */
-			break;
-		}
-
-		/*
-		 * Check if this key matches the input.
-		 * Set matches to zero, so they match only once
-		 * and we can find duplicates or extra keys
-		 */
-		for (k = 0; k < sizeof(compare); ++k) {
-			if (compare[k] == '\0')	/* only non-zero entries */
-				continue;
-			if (c == compare[k]) {	/* found matching key */
-				compare[k] = '\0';
-				break;
-			}
-		}
-		if (k == sizeof(compare)) {
-			return -1;		/* unmatched key */
-		}
-	}
-
-	/*
-	 * A full match leaves no keys in the `compare' array,
-	 */
-	for (i = 0; i < sizeof(compare); ++i) {
-		if (compare[i])
-		{
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-/***********************************************************************
-F* Function:     static uchar *key_match (uchar *kbd_data) P*A*Z*
- *
-P* Parameters:   uchar *kbd_data
-P*                - The keys to match against our magic definitions
-P*
-P* Returnvalue:  uchar *
-P*                - != NULL: Pointer to the corresponding command(s)
-P*                     NULL: No magic is about to happen
- *
-Z* Intention:    Check if pressed key(s) match magic sequence,
-Z*               and return the command string associated with that key(s).
-Z*
-Z*               If no key press was decoded, NULL is returned.
-Z*
-Z*               Note: the first character of the argument will be
-Z*                     overwritten with the "magic charcter code" of the
-Z*                     decoded key(s), or '\0'.
-Z*
-Z*               Note: the string points to static environment data
-Z*                     and must be saved before you call any function that
-Z*                     modifies the environment.
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-static uchar *key_match (uchar *kbd_data)
-{
-	char magic[sizeof (kbd_magic_prefix) + 1];
-	uchar *suffix;
-	char *kbd_magic_keys;
-
-	/*
-	 * The following string defines the characters that can pe appended
-	 * to "key_magic" to form the names of environment variables that
-	 * hold "magic" key codes, i. e. such key codes that can cause
-	 * pre-boot actions. If the string is empty (""), then only
-	 * "key_magic" is checked (old behaviour); the string "125" causes
-	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
-	 */
-	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
-		kbd_magic_keys = "";
-
-	/* loop over all magic keys;
-	 * use '\0' suffix in case of empty string
-	 */
-	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
-		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-		debug ("### Check magic \"%s\"\n", magic);
-		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
-			char cmd_name[sizeof (kbd_command_prefix) + 1];
-			char *cmd;
-
-			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
-			cmd = getenv (cmd_name);
-			debug ("### Set PREBOOT to $(%s): \"%s\"\n",
-					cmd_name, cmd ? cmd : "<<NULL>>");
-			*kbd_data = *suffix;
-			return ((uchar *)cmd);
-		}
-	}
-	debug ("### Delete PREBOOT\n");
-	*kbd_data = '\0';
-	return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-/***********************************************************************
-F* Function:     int do_kbd (cmd_tbl_t *cmdtp, int flag,
-F*                           int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters:   cmd_tbl_t *cmdtp
-P*                - Pointer to our command table entry
-P*               int flag
-P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
-P*                  a repetition
-P*               int argc
-P*                - Argument count
-P*               char * const argv[]
-P*                - Array of the actual arguments
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned.
- *
-Z* Intention:    Implement the "kbd" command.
-Z*               The keyboard status is read.  The result is printed on
-Z*               the console and written into the "keybd" environment
-Z*               variable.
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar val;
-	int i;
-
-#if 0 /* Done in kbd_init */
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
-	/* Read keys */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	puts ("Keys:");
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-		printf (" %02x", kbd_data[i]);
-	}
-	putc ('\n');
-	setenv ("keybd", keybd_env);
-	return 0;
-}
-
-U_BOOT_CMD(
-	kbd,	1,	1,	do_kbd,
-	"read keyboard status",
-	""
-);
-
-/*----------------------------- Utilities -----------------------------*/
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	uchar val;
-
-	/* Read keys */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
-}
-#endif
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
deleted file mode 100644
index e9aa0b7..0000000
--- a/board/lwmon5/lwmon5.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <post.h>
-#include <flash.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
-
-ulong flash_get_size(ulong base, int banknum);
-int misc_init_r_kbd(void);
-
-int board_early_init_f(void)
-{
-	u32 sdr0_pfc1, sdr0_pfc2;
-	u32 reg;
-
-	/* PLB Write pipelining disabled. Denali Core workaround */
-	mtdcr(PLB4A0_ACR, 0xDE000000);
-	mtdcr(PLB4A1_ACR, 0xDE000000);
-
-	/*--------------------------------------------------------------------
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
-	mtdcr(UIC0SR, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
-	mtdcr(UIC0ER, 0x00000000);  /* disable all */
-	mtdcr(UIC0CR, 0x00000000);  /* we have not critical interrupts at the moment */
-	mtdcr(UIC0PR, 0xFFBFF1EF);  /* Adjustment of the polarity */
-	mtdcr(UIC0TR, 0x00000900);  /* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC0SR, 0xffffffff);  /* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
-	mtdcr(UIC1ER, 0x00000000);  /* disable all */
-	mtdcr(UIC1CR, 0x00000000);  /* all non-critical */
-	mtdcr(UIC1PR, 0xFFFFC6A5);  /* Adjustment of the polarity */
-	mtdcr(UIC1TR, 0x60000040);  /* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
-	mtdcr(UIC2ER, 0x00000000);  /* disable all */
-	mtdcr(UIC2CR, 0x00000000);  /* all non-critical */
-	mtdcr(UIC2PR, 0x27C00000);  /* Adjustment of the polarity */
-	mtdcr(UIC2TR, 0x3C000000);  /* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
-
-	/* Trace Pins are disabled. SDR0_PFC0 Register */
-	mtsdr(SDR0_PFC0, 0x0);
-
-	/* select Ethernet pins */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	/* SMII via ZMII */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
-		SDR0_PFC1_SELECT_CONFIG_6;
-	mfsdr(SDR0_PFC2, sdr0_pfc2);
-	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
-		SDR0_PFC2_SELECT_CONFIG_6;
-
-	/* enable SPI (SCP) */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
-
-	mtsdr(SDR0_PFC2, sdr0_pfc2);
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-
-	mtsdr(SDR0_PFC4, 0x80000000);
-
-	/* PCI arbiter disabled */
-	/* PCI Host Configuration disbaled */
-	mfsdr(SDR0_PCI0, reg);
-	reg = 0;
-	mtsdr(SDR0_PCI0, 0x00000000 | reg);
-
-	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-	/* enable the LSB transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-	/* enable the CAN transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
-
-	reg = 0; /* reuse as counter */
-	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
-		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
-			& ~CONFIG_SYS_DSPIC_TEST_MASK);
-	while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
-		udelay(1000);
-	}
-	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
-		/* set "boot error" flag */
-		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
-			in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
-			CONFIG_SYS_DSPIC_TEST_MASK);
-	}
-#endif
-
-	/*
-	 * Reset PHY's:
-	 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
-	 * upon reset, and with the first reset upon powerup, the addresses are
-	 * not latched reliable, since the IRQ line is multiplexed with an
-	 * MDIO address. A 2nd reset at this time will make sure, that the
-	 * correct address is latched.
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-	udelay(1000);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
-	udelay(1000);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-
-	return 0;
-}
-
-/*
- * Override weak default with board specific version
- */
-phys_addr_t cfi_flash_bank_addr(int bank)
-{
-	return lwmon5_cfi_flash_bank_addr[bank];
-}
-
-/*
- * Override the weak default mapping function with a board specific one
- */
-u32 flash_get_bank_size(int cs, int idx)
-{
-	return flash_info[idx].size;
-}
-
-int board_early_init_r(void)
-{
-	u32 val0, val1;
-
-	/*
-	 * lwmon5 is manufactured in 2 different board versions:
-	 * The lwmon5a board has 64MiB NOR flash instead of the
-	 * 128MiB of the original lwmon5. Unfortunately the CFI driver
-	 * will report 2 banks of 64MiB even for the smaller flash
-	 * chip, since the bank is mirrored. To fix this, we bring
-	 * one bank into CFI query mode and read its response. This
-	 * enables us to detect the real number of flash devices/
-	 * banks which will be used later on by the common CFI driver.
-	 */
-
-	/* Put bank 0 into CFI command mode and read */
-	out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
-	val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
-	val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
-
-	/* Reset flash again out of query mode */
-	out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
-
-	/* When not identical, we have 2 different flash devices/banks */
-	if (val0 != val1)
-		return 0;
-
-	/*
-	 * Now we're sure that we're running on a LWMON5a board with
-	 * only 64MiB NOR flash in one bank:
-	 *
-	 * Set flash base address and bank count for CFI driver probing.
-	 */
-	cfi_flash_num_flash_banks = 1;
-	lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 pbcr;
-	int size_val = 0;
-	u32 reg;
-#ifndef CONFIG_LCD4_LWMON5
-	unsigned long usb2d0cr = 0;
-	unsigned long usb2phy0cr, usb2h0cr = 0;
-	unsigned long sdr0_pfc1, sdr0_srst;
-#endif
-
-	/*
-	 * FLASH stuff...
-	 */
-
-	/* Re-do sizing to get full correct info */
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	mfebc(PB0CR, pbcr);
-	size_val = ffs(gd->bd->bi_flashsize) - 21;
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtebc(PB0CR, pbcr);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size(gd->bd->bi_flashstart, 0);
-
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
-		      &flash_info[cfi_flash_num_flash_banks - 1]);
-
-	/* Env protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-		      CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[cfi_flash_num_flash_banks - 1]);
-
-#ifndef CONFIG_LCD4_LWMON5
-	/*
-	 * USB suff...
-	 */
-
-	/* Reset USB */
-	/* Reset of USB2PHY0 must be active at least 10 us  */
-	mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
-	udelay(2000);
-
-	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
-	      SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
-	      SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
-	udelay(2000);
-
-	/* Errata CHIP_6 */
-
-	/* 1. Set internal PHY configuration */
-	/* SDR Setting */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	mfsdr(SDR0_USB0, usb2d0cr);
-	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
-
-	/*
-	 * An 8-bit/60MHz interface is the only possible alternative
-	 * when connecting the Device to the PHY
-	 */
-	usb2h0cr   = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
-	usb2h0cr   = usb2h0cr |  SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
-
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-	mtsdr(SDR0_USB0, usb2d0cr);
-	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	/* 2. De-assert internal PHY reset */
-	mfsdr(SDR0_SRST1, sdr0_srst);
-	sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
-	mtsdr(SDR0_SRST1, sdr0_srst);
-
-	/* 3. Wait for more than 1 ms */
-	udelay(2000);
-
-	/* 4. De-assert USB 2.0 Host main reset */
-	mfsdr(SDR0_SRST0, sdr0_srst);
-	sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
-	mtsdr(SDR0_SRST0, sdr0_srst);
-	udelay(1000);
-
-	/* 5. De-assert reset of OPB2 cores */
-	mfsdr(SDR0_SRST1, sdr0_srst);
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
-	mtsdr(SDR0_SRST1, sdr0_srst);
-	udelay(1000);
-
-	/* 6. Set EHCI Configure FLAG */
-
-	/* 7. Reassert internal PHY reset: */
-	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
-	udelay(1000);
-#endif
-
-	/*
-	 * Clear resets
-	 */
-	mtsdr(SDR0_SRST1, 0x00000000);
-	mtsdr(SDR0_SRST0, 0x00000000);
-
-#ifndef CONFIG_LCD4_LWMON5
-	printf("USB:   Host(int phy) Device(ext phy)\n");
-#endif
-
-	/*
-	 * Clear PLB4A0_ACR[WRP]
-	 * This fix will make the MAL burst disabling patch for the Linux
-	 * EMAC driver obsolete.
-	 */
-	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
-	mtdcr(PLB4A0_ACR, reg);
-
-#ifndef CONFIG_LCD4_LWMON5
-	/*
-	 * Init matrix keyboard
-	 */
-	misc_init_r_kbd();
-#endif
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: %s", __stringify(CONFIG_HOSTNAME));
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-void hw_watchdog_reset(void)
-{
-	int val;
-#if defined(CONFIG_WD_MAX_RATE)
-	unsigned long long ct = get_ticks();
-
-	/*
-	 * Don't allow watch-dog triggering more frequently than
-	 * the predefined value CONFIG_WD_MAX_RATE [ticks].
-	 */
-	if (ct >= gd->arch.wdt_last) {
-		if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
-			return;
-	} else {
-		/* Time base counter had been reset */
-		if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
-		    CONFIG_WD_MAX_RATE)
-			return;
-	}
-	gd->arch.wdt_last = get_ticks();
-#endif
-
-	/*
-	 * Toggle watchdog output
-	 */
-	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
-	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
-}
-
-int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	if ((strcmp(argv[1], "on") == 0))
-		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
-	else if ((strcmp(argv[1], "off") == 0))
-		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
-	else
-		return cmd_usage(cmdtp);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	eepromwp,	2,	0,	do_eeprom_wp,
-	"eeprom write protect off/on",
-	"<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
-);
-
-#if defined(CONFIG_VIDEO)
-#include <video_fb.h>
-#include <mb862xx.h>
-
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs [] = {
-	{ 0x0100, 0x00000f00 },
-	{ 0x0020, 0x801401df },
-	{ 0x0024, 0x00000000 },
-	{ 0x0028, 0x00000000 },
-	{ 0x002c, 0x00000000 },
-	{ 0x0110, 0x00000000 },
-	{ 0x0114, 0x00000000 },
-	{ 0x0118, 0x01df0280 },
-	{ 0x0004, 0x031f0000 },
-	{ 0x0008, 0x027f027f },
-	{ 0x000c, 0x015f028f },
-	{ 0x0010, 0x020c0000 },
-	{ 0x0014, 0x01df01ea },
-	{ 0x0018, 0x00000000 },
-	{ 0x001c, 0x01e00280 },
-	{ 0x0100, 0x80010f00 },
-	{ 0x0, 0x0 }
-};
-
-const gdc_regs *board_get_regs(void)
-{
-	return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init(void)
-{
-	/*
-	 * Reset Lime controller
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
-	udelay(500);
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
-	mb862xx.winSizeX = 640;
-	mb862xx.winSizeY = 480;
-	mb862xx.gdfBytesPP = 2;
-	mb862xx.gdfIndex = GDF_15BIT_555RGB;
-
-	return CONFIG_SYS_LIME_BASE_0;
-}
-
-#define DEFAULT_BRIGHTNESS	0x64
-
-static void board_backlight_brightness(int brightness)
-{
-	if (brightness > 0) {
-		/* pwm duty, lamp on */
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
-	} else {
-		/* lamp off */
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
-	}
-}
-
-void board_backlight_switch(int flag)
-{
-	char * param;
-	int rc;
-
-	if (flag) {
-		param = getenv("brightness");
-		rc = param ? simple_strtol(param, NULL, 10) : -1;
-		if (rc < 0)
-			rc = DEFAULT_BRIGHTNESS;
-	} else {
-		rc = 0;
-	}
-	board_backlight_brightness(rc);
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
-	if (line_number == 1)
-		strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
-	else
-		info [0] = '\0';
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_VIDEO */
-
-void board_reset(void)
-{
-	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * lwmon5 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
-	char s[8];
-
-	env_init();
-	getenv_f("boot_os", s, sizeof(s));
-	if ((s != NULL) && (strcmp(s, "yes") == 0))
-		return 0;
-
-	return 1;
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
-	const gdc_regs *regs = board_get_regs();
-
-	/*
-	 * Setup PFC registers, mainly for ethernet support
-	 * later on in Linux
-	 */
-	board_early_init_f();
-
-	/* enable the LSB transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-
-	/*
-	 * Clear resets
-	 */
-	mtsdr(SDR0_SRST1, 0x00000000);
-	mtsdr(SDR0_SRST0, 0x00000000);
-
-	/*
-	 * Reset Lime controller
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
-	udelay(500);
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
-	out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
-	udelay(300);
-	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
-
-	while (regs->index) {
-		out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
-			 regs->index, regs->value);
-		regs++;
-	}
-
-	board_backlight_brightness(DEFAULT_BRIGHTNESS);
-}
-#endif
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
deleted file mode 100644
index 5dfbb0b..0000000
--- a/board/lwmon5/sdram.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-#include <watchdog.h>
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-extern void dcbz_area(u32 start_address, u32 num_bytes);
-
-static u32 is_ecc_enabled(void)
-{
-	u32 val;
-
-	mfsdram(DDR0_22, val);
-	val &= DDR0_22_CTRL_RAW_MASK;
-	if (val)
-		return 1;
-	else
-		return 0;
-}
-
-void board_add_ram_info(int use_default)
-{
-	PPC4xx_SYS_INFO board_cfg;
-	u32 val;
-
-	if (is_ecc_enabled())
-		puts(" (ECC");
-	else
-		puts(" (ECC not");
-
-	get_sys_info(&board_cfg);
-	printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
-
-	mfsdram(DDR0_03, val);
-	val = DDR0_03_CASLAT_DECODE(val);
-	printf(", CL%d)", val);
-}
-
-#ifdef CONFIG_DDR_ECC
-static void wait_ddr_idle(void)
-{
-	/*
-	 * Controller idle status cannot be determined for Denali
-	 * DDR2 code. Just return here.
-	 */
-}
-
-static void program_ecc(u32 start_address,
-			u32 num_bytes,
-			u32 tlb_word2_i_value)
-{
-	u32 val;
-	u32 current_addr = start_address;
-	u32 size;
-	int bytes_remaining;
-
-	sync();
-	wait_ddr_idle();
-
-	/*
-	 * Because of 440EPx errata CHIP 11, we don't touch the last 256
-	 * bytes of SDRAM.
-	 */
-	bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
-
-	/*
-	 * We have to write the ECC bytes by zeroing and flushing in smaller
-	 * steps, since the whole 256MByte takes too long for the external
-	 * watchdog.
-	 */
-	while (bytes_remaining > 0) {
-		size = min((64 << 20), bytes_remaining);
-
-		/* Write zero's to SDRAM */
-		dcbz_area(current_addr, size);
-
-		/* Write modified dcache lines back to memory */
-		clean_dcache_range(current_addr, current_addr + size);
-
-		current_addr += 64 << 20;
-		bytes_remaining -= 64 << 20;
-		WATCHDOG_RESET();
-	}
-
-	sync();
-	wait_ddr_idle();
-
-	/* Clear error status */
-	mfsdram(DDR0_00, val);
-	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
-	/* Set 'int_mask' parameter to functionnal value */
-	mfsdram(DDR0_01, val);
-	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
-
-	sync();
-	wait_ddr_idle();
-}
-#endif
-
-/*************************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5)
-	/* CL=4 */
-	mtsdram(DDR0_02, 0x00000000);
-
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
-
-	mtsdram(DDR0_04, 0x0B030300);
-	mtsdram(DDR0_05, 0x02020308);
-	mtsdram(DDR0_06, 0x0003C812);
-	mtsdram(DDR0_07, 0x00090100);
-	mtsdram(DDR0_08, 0x03c80001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000100);
-	mtsdram(DDR0_11, 0x000CC800);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x1e000000);
-	mtsdram(DDR0_18, 0x1e1e1e1e);
-	mtsdram(DDR0_19, 0x1e1e1e1e);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
-	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
-#else
-	mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
-	mtsdram(DDR0_23, 0x01000000);
-	mtsdram(DDR0_24, 0x01010001);
-
-	mtsdram(DDR0_26, 0x2D93028A);
-	mtsdram(DDR0_27, 0x0784682B);
-
-	mtsdram(DDR0_28, 0x00000080);
-	mtsdram(DDR0_31, 0x00000000);
-	mtsdram(DDR0_42, 0x01000008);
-
-	mtsdram(DDR0_43, 0x050A0200);
-	mtsdram(DDR0_44, 0x00000005);
-	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-
-	denali_wait_for_dlllock();
-
-#if defined(CONFIG_DDR_DATA_EYE)
-	/* -----------------------------------------------------------+
-	 * Perform data eye search if requested.
-	 * ----------------------------------------------------------*/
-	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
-		    TLB_WORD2_I_ENABLE);
-	denali_core_search_data_eye();
-	remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif
-
-	/*
-	 * Program tlb entries for this size (dynamic)
-	 */
-	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
-		    MY_TLB_WORD2_I_ENABLE);
-
-#if defined(CONFIG_DDR_ECC)
-#if defined(CONFIG_4xx_DCACHE)
-	/*
-	 * If ECC is enabled, initialize the parity bits.
-	 */
-	program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#else /* CONFIG_4xx_DCACHE */
-	/*
-	 * Setup 2nd TLB with same physical address but different virtual address
-	 * with cache enabled. This is done for fast ECC generation.
-	 */
-	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
-	/*
-	 * If ECC is enabled, initialize the parity bits.
-	 */
-	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
-	/*
-	 * Now after initialization (auto-calibration and ECC generation)
-	 * remove the TLB entries with caches enabled and program again with
-	 * desired cache functionality
-	 */
-	remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif /* CONFIG_4xx_DCACHE */
-#endif /* CONFIG_DDR_ECC */
-
-	/*
-	 * Clear possible errors resulting from data-eye-search.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-#endif /* CONFIG_SPL_BUILD */
-
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
-}
diff --git a/configs/lcd4_lwmon5_defconfig b/configs/lcd4_lwmon5_defconfig
deleted file mode 100644
index b911dbd..0000000
--- a/configs/lcd4_lwmon5_defconfig
+++ /dev/null
@@ -1,6 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_LWMON5=y
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5"
-# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
deleted file mode 100644
index 0a6da68..0000000
--- a/configs/lwmon5_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_LWMON5=y
-# CONFIG_CMD_SETEXPR is not set
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 87e2b35..2697451 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+lwmon5           powerpc     ppc4xx         -           -           Stefan Roese <sr@denx.de>
 csb272/csb472    powerpc     ppc4xx         -           -           Tolunay Orkun <torkun@nextio.com>
 alpr             powerpc     ppc4xx         -           -           Stefan Roese <sr@denx.de>
 cam_enc_4xx      arm         arm926ejs      8d775763    2015-08-20  Heiko Schocher <hs@denx.de>
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index 1c74e97..868c512 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -419,8 +419,7 @@ void *video_hw_init (void)
 	board_disp_init ();
 #endif
 
-#if (defined(CONFIG_LWMON5) || \
-     defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
+#if defined(CONFIG_SOCRATES) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
 	/* Lamp on */
 	board_backlight_switch (1);
 #endif
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
deleted file mode 100644
index 513167e..0000000
--- a/include/configs/lwmon5.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * lwmon5.h - configuration for lwmon5 board
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Liebherr extra version info
- */
-#define CONFIG_IDENT_STRING	" - v2.0"
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_LWMON5		1		/* Board is lwmon5	*/
-#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
-#define CONFIG_440		1		/* ... PPC440 family	*/
-
-#ifdef CONFIG_LCD4_LWMON5
-#define	CONFIG_SYS_TEXT_BASE	0x01000000 /* SPL U-Boot TEXT_BASE */
-#define CONFIG_HOSTNAME		lcd4_lwmon5
-#else
-#define CONFIG_SYS_TEXT_BASE	0xFFF80000
-#define CONFIG_HOSTNAME		lwmon5
-#endif
-
-#define CONFIG_SYS_CLK_FREQ	33300000	/* external freq to pll	*/
-
-#define CONFIG_4xx_DCACHE		/* enable cache in SDRAM	*/
-
-#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_early_init_f	*/
-#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r	*/
-#define CONFIG_BOARD_POSTCLK_INIT	/* Call board_postclk_init	*/
-#define CONFIG_MISC_INIT_R		/* Call misc_init_r		*/
-#define CONFIG_BOARD_RESET		/* Call board_reset		*/
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
-#define CONFIG_SYS_MONITOR_LEN		0x80000
-#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
-
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
-#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH	*/
-#define CONFIG_SYS_LIME_BASE_0		0xc0000000
-#define CONFIG_SYS_LIME_BASE_1		0xc1000000
-#define CONFIG_SYS_LIME_BASE_2		0xc2000000
-#define CONFIG_SYS_LIME_BASE_3		0xc3000000
-#define CONFIG_SYS_FPGA_BASE_0		0xc4000000
-#define CONFIG_SYS_FPGA_BASE_1		0xc4200000
-#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
-#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
-#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
-#define CONFIG_SYS_PCI_MEMBASE1		(CONFIG_SYS_PCI_MEMBASE  + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE2		(CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
-#define CONFIG_SYS_PCI_MEMBASE3		(CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
-
-#ifndef CONFIG_LCD4_LWMON5
-#define CONFIG_SYS_USB2D0_BASE		0xe0000100
-#define CONFIG_SYS_USB_DEVICE		0xe0000000
-#define CONFIG_SYS_USB_HOST		0xe0000400
-#endif
-
-/*
- * Initial RAM & stack pointer
- *
- * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
- * the POST_WORD from OCM to a 440EPx register that preserves it's
- * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
- * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
- */
-#ifndef CONFIG_LCD4_LWMON5
-#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#endif
-/* unused GPT0 COMP reg	*/
-#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
-#define CONFIG_SYS_OCM_SIZE		(16 << 10)
-/* 440EPx errata CHIP 11: don't use last 4kbytes */
-#define CONFIG_SYS_MEM_TOP_HIDE		(4 << 10)
-
-/* Additional registers for watchdog timer post test */
-#define CONFIG_SYS_WATCHDOG_TIME_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
-#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
-#define CONFIG_SYS_DSPIC_TEST_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_OCM_STATUS_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
-#define CONFIG_SYS_WATCHDOG_MAGIC	0x12480000
-#define CONFIG_SYS_WATCHDOG_MAGIC_MASK	0xFFFF0000
-#define CONFIG_SYS_DSPIC_TEST_MASK	0x00000001
-#define CONFIG_SYS_OCM_STATUS_OK	0x00009A00
-#define CONFIG_SYS_OCM_STATUS_FAIL	0x0000A300
-#define CONFIG_SYS_OCM_STATUS_MASK	0x0000FF00
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external clock provided	*/
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE						\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environment vars	*/
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-
-#define CONFIG_SYS_FLASH0		0xFC000000
-#define CONFIG_SYS_FLASH1		0xF8000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 	/* use buffered writes (20x faster)	*/
-#define CONFIG_SYS_FLASH_PROTECTION		/* use hardware flash protection	*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST		/* don't warn upon unknown flash	*/
-
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_SYS_MBYTES_SDRAM		256
-#define CONFIG_SYS_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
-#define CONFIG_DDR_DATA_EYE			/* use DDR2 optimization	*/
-#ifndef CONFIG_LCD4_LWMON5
-#define CONFIG_DDR_ECC				/* enable ECC			*/
-#endif
-
-#ifndef CONFIG_LCD4_LWMON5
-/* POST support */
-#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
-				 CONFIG_SYS_POST_CPU		| \
-				 CONFIG_SYS_POST_ECC		| \
-				 CONFIG_SYS_POST_ETHER		| \
-				 CONFIG_SYS_POST_FPU		| \
-				 CONFIG_SYS_POST_I2C		| \
-				 CONFIG_SYS_POST_MEMORY		| \
-				 CONFIG_SYS_POST_OCM		| \
-				 CONFIG_SYS_POST_RTC		| \
-				 CONFIG_SYS_POST_SPR		| \
-				 CONFIG_SYS_POST_UART		| \
-				 CONFIG_SYS_POST_SYSMON		| \
-				 CONFIG_SYS_POST_WATCHDOG	| \
-				 CONFIG_SYS_POST_DSP		| \
-				 CONFIG_SYS_POST_BSPEC1		| \
-				 CONFIG_SYS_POST_BSPEC2		| \
-				 CONFIG_SYS_POST_BSPEC3		| \
-				 CONFIG_SYS_POST_BSPEC4		| \
-				 CONFIG_SYS_POST_BSPEC5)
-
-/* Define here the base-addresses of the UARTs to test in POST */
-#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
-			CONFIG_SYS_NS16550_COM2 }
-
-#define CONFIG_POST_UART  {				\
-	"UART test",					\
-	"uart",						\
-	"This test verifies the UART operation.",	\
-	POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,	\
-	&uart_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_UART				\
-	}
-
-#define CONFIG_POST_WATCHDOG  {				\
-	"Watchdog timer test",				\
-	"watchdog",					\
-	"This test checks the watchdog timer.",		\
-	POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
-	&lwmon5_watchdog_post_test,			\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_WATCHDOG			\
-	}
-
-#define CONFIG_POST_BSPEC1    {				\
-	"dsPIC init test",				\
-	"dspic_init",					\
-	"This test returns result of dsPIC READY test run earlier.",	\
-	POST_RAM | POST_ALWAYS,				\
-	&dspic_init_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC1				\
-	}
-
-#define CONFIG_POST_BSPEC2    {				\
-	"dsPIC test",					\
-	"dspic",					\
-	"This test gets result of dsPIC POST and dsPIC version.",	\
-	POST_RAM | POST_ALWAYS,				\
-	&dspic_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC2				\
-	}
-
-#define CONFIG_POST_BSPEC3    {				\
-	"FPGA test",					\
-	"fpga",						\
-	"This test checks FPGA registers and memory.",	\
-	POST_RAM | POST_ALWAYS | POST_MANUAL,		\
-	&fpga_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC3				\
-	}
-
-#define CONFIG_POST_BSPEC4    {				\
-	"GDC test",					\
-	"gdc",						\
-	"This test checks GDC registers and memory.",	\
-	POST_RAM | POST_ALWAYS | POST_MANUAL,\
-	&gdc_post_test,					\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC4				\
-	}
-
-#define CONFIG_POST_BSPEC5    {				\
-	"SYSMON1 test",					\
-	"sysmon1",					\
-	"This test checks GPIO_62_EPX pin indicating power failure.",	\
-	POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST,	\
-	&sysmon1_post_test,				\
-	NULL,						\
-	NULL,						\
-	CONFIG_SYS_POST_BSPEC5				\
-	}
-
-#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
-#define CONFIG_LOGBUFFER
-/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
-#define CONFIG_ALT_LH_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
-#define CONFIG_ALT_LB_ADDR	(CONFIG_SYS_OCM_BASE)
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* RTC				*/
-#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR	0x52	/* EEPROM          (CPU Modul)	*/
-#define CONFIG_SYS_I2C_EEPROM_MB_ADDR	0x53	/* EEPROM AT24C128 (MainBoard)	*/
-#define CONFIG_SYS_I2C_DSPIC_ADDR	0x54	/* dsPIC   			*/
-#define CONFIG_SYS_I2C_DSPIC_2_ADDR	0x55	/* dsPIC			*/
-#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR	0x56	/* dsPIC			*/
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* dsPIC			*/
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel AT24C128 has	*/
-					/* 64 byte page write mode using*/
-					/* last 6 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
-
-#define CONFIG_RTC_PCF8563			/* enable Philips PCF8563 RTC	*/
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51	/* Philips PCF8563 RTC address	*/
-#define CONFIG_SYS_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard		*/
-#define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* PIC I/O addr               */
-
-#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_RTC_ADDR,	\
-					 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
-					 CONFIG_SYS_I2C_EEPROM_MB_ADDR,	\
-					 CONFIG_SYS_I2C_DSPIC_ADDR,	\
-					 CONFIG_SYS_I2C_DSPIC_2_ADDR,	\
-					 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
-					 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
-
-/*
- * Pass open firmware flat tree
- */
-#define CONFIG_OF_LIBFDT
-#define CONFIG_OF_BOARD_SETUP
-/* Update size in "reg" property of NOR FLASH device tree nodes */
-#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-
-#define CONFIG_FIT			/* enable FIT image support	*/
-
-#define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
-
-#define	CONFIG_PREBOOT		"setenv bootdelay 15"
-
-#undef	CONFIG_BOOTARGS
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"hostname=lwmon5\0"						\
-	"netdev=eth0\0"							\
-	"unlock=yes\0"							\
-	"logversion=2\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
-	"addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
-	"flash_nfs=run nfsargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty addmisc;"			\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};"				\
-		"run nfsargs addip addtty addmisc;bootm\0"		\
-	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
-	"bootfile=/tftpboot/lwmon5/uImage\0"				\
-	"kernel_addr=FC000000\0"					\
-	"ramdisk_addr=FC180000\0"					\
-	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
-	"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"	\
-		"cp.b 200000 FFF80000 80000\0"			        \
-	"upd=run load update\0"						\
-	"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"	\
-		"autoscr 200000\0"					\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define	CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		3	/* PHY address, See schematics	*/
-
-#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
-#define CONFIG_PHY_RESET_DELAY	300
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#define CONFIG_PHY1_ADDR	1
-
-/* Video console */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_MB862xx
-#define CONFIG_VIDEO_MB862xx_ACCEL
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define VIDEO_FB_16BPP_PIXEL_SWAP
-#define VIDEO_FB_16BPP_WORD_SWAP
-
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#define CONFIG_SPLASH_SCREEN
-
-#ifndef CONFIG_LCD4_LWMON5
-/*
- * USB/EHCI
- */
-#define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
-#define CONFIG_USB_EHCI_PPC4XX		/* on PPC4xx platform		*/
-#define CONFIG_SYS_PPC4XX_USB_ADDR	0xe0000300
-#define CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define CONFIG_EHCI_DESC_BIG_ENDIAN
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
-#define CONFIG_USB_STORAGE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-
-#ifdef CONFIG_VIDEO
-#define CONFIG_CMD_BMP
-#endif
-
-#ifndef CONFIG_LCD4_LWMON5
-#ifdef CONFIG_440EPX
-#define CONFIG_CMD_USB
-#endif
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_LOOPW            1       /* enable loopw command         */
-#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
-
-#ifndef CONFIG_LCD4_LWMON5
-#ifndef DEBUG
-#define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
-#endif
-#define CONFIG_WD_PERIOD	40000	/* in usec */
-#define CONFIG_WD_MAX_RATE	66600	/* in ticks */
-#endif
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the 40x Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(16 << 20) /* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTM_LEN		(16 << 20) /* Increase max gunzip size */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
-
-/* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x03000280
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xfc000)
-
-/* Memory Bank 1 (Lime) initialization						*/
-#define CONFIG_SYS_EBC_PB1AP		0x01004380
-#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_LIME_BASE_0 | 0xbc000)
-
-/* Memory Bank 2 (FPGA) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP		0x01004400
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
-
-/* Memory Bank 3 (FPGA2) initialization						*/
-#define CONFIG_SYS_EBC_PB3AP		0x01004400
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
-
-#define CONFIG_SYS_EBC_CFG		0xb8400000
-
-/*
- * Graphics (Fujitsu Lime)
- */
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK	0xC1FC0038
-#if 1 /* 133MHz is not tested enough, use 100MHz for now */
-/* Lime Clock frequency is to set 100MHz */
-#define CONFIG_SYS_LIME_CLOCK_100MHZ	0x00000
-#else
-/* Lime Clock frequency for 133MHz */
-#define CONFIG_SYS_LIME_CLOCK_133MHZ	0x10000
-#endif
-
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR		0xC1FCFFFC
-/*
- * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
- * and pixel flare on display when 133MHz was configured. According to
- * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
- * Grade
- */
-#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_MB862xx_MMR	0x414FB7F3
-#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_133MHZ
-#else
-#define CONFIG_SYS_MB862xx_MMR	0x414FB7F2
-#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_100MHZ
-#endif
-
-/*
- * GPIO Setup
- */
-#define CONFIG_SYS_GPIO_PHY1_RST	12
-#define CONFIG_SYS_GPIO_FLASH_WP	14
-#define CONFIG_SYS_GPIO_PHY0_RST	22
-#define CONFIG_SYS_GPIO_PERM_VOLT_FEED	49
-#define CONFIG_SYS_GPIO_DSPIC_READY	51
-#define CONFIG_SYS_GPIO_CAN_ENABLE	53
-#define CONFIG_SYS_GPIO_LSB_ENABLE	54
-#define CONFIG_SYS_GPIO_EEPROM_EXT_WP	55
-#define CONFIG_SYS_GPIO_HIGHSIDE	56
-#define CONFIG_SYS_GPIO_EEPROM_INT_WP	57
-#define CONFIG_SYS_GPIO_BOARD_RESET	58
-#define CONFIG_SYS_GPIO_LIME_S		59
-#define CONFIG_SYS_GPIO_LIME_RST	60
-#define CONFIG_SYS_GPIO_SYSMON_STATUS	62
-#define CONFIG_SYS_GPIO_WATCHDOG	63
-
-/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
-#ifdef CONFIG_LCD4_LWMON5
-#define GPIO49_VAL	0
-#else
-#define GPIO49_VAL	1
-#endif
-
-/*
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
-{											\
-/* GPIO Core 0 */									\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)			*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)			*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
-},											\
-{											\
-/* GPIO Core 1 */									\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
-}											\
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * SPL related defines
- */
-#ifdef CONFIG_LCD4_LWMON5
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NOR_SUPPORT
-#define CONFIG_SPL_TEXT_BASE		0xffff0000 /* last 64 KiB for SPL */
-#define CONFIG_SYS_SPL_MAX_LEN		(64 << 10)
-#define CONFIG_UBOOT_PAD_TO		458752	/* decimal for 'dd' */
-#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* image.c */
-#define CONFIG_SPL_LIBGENERIC_SUPPORT	/* string.c */
-#define CONFIG_SPL_SERIAL_SUPPORT
-
-/* Place BSS for SPL near end of SDRAM */
-#define CONFIG_SPL_BSS_START_ADDR	((256 - 1) << 20)
-#define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)
-
-#define CONFIG_SPL_OS_BOOT
-/* Place patched DT blob (fdt) at this address */
-#define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000
-
-#define CONFIG_SPL_TARGET		"u-boot-img-spl-at-end.bin"
-
-/* Settings for real U-Boot to be loaded from NOR flash */
-#define CONFIG_SYS_UBOOT_BASE		(-CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_UBOOT_START		0x01002100
-
-#define CONFIG_SYS_OS_BASE		0xf8000000
-#define CONFIG_SYS_FDT_BASE		0xf87c0000
-#endif
-
-#endif	/* __CONFIG_H */