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| author | Heiko Schocher <hs@denx.de> | 2011-11-01 20:00:27 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-11-03 22:56:24 +0100 |
| commit | 882ecfa390516791d5e04db2d7c5ed602441755a (patch) | |
| tree | 16efaeac273a1fc99f4511a8f0aa57f4cc1bf688 | |
| parent | 1fa892c67baffd4b51170cfe9ca6d57ddf0eba60 (diff) | |
| download | u-boot-imx-882ecfa390516791d5e04db2d7c5ed602441755a.zip u-boot-imx-882ecfa390516791d5e04db2d7c5ed602441755a.tar.gz u-boot-imx-882ecfa390516791d5e04db2d7c5ed602441755a.tar.bz2 | |
net, davinci_emac: make clock divider in MDIO control register configurable
Define CONFIG_SYS_EMAC_TI_CLKDIV for setting the clkdiv value
in the MDIO control register.
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Sandeep Paulraj <s-paulraj@ti.com>
cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| -rw-r--r-- | drivers/net/davinci_emac.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index a900480..fa31159 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -53,6 +53,11 @@ unsigned int emac_dbg = 0; #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ #endif +#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) +#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ + EMAC_MDIO_CLOCK_FREQ) - 1) +#endif + static void davinci_eth_mdio_enable(void); static int gen_init_phy(int phy_addr); @@ -131,7 +136,7 @@ static void davinci_eth_mdio_enable(void) { u_int32_t clkdiv; - clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | @@ -473,7 +478,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) #endif /* Init MDIO & get link state */ - clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, &adap_mdio->CONTROL); |