arm: rmobile: Add BLANCHE board support

BLANCHE is development board based on R-Car V2H SoC (R8A7792)

This commit supports the following periherals:
- SCIF, Ethernet, QSPI, MMC

Signed-off-by: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

19 files changed, 5006 insertions, 47 deletions

diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32
index b485953..89588aa 100644
--- a/arch/arm/mach-rmobile/Kconfig.32
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -7,6 +7,11 @@ choice
 config TARGET_ARMADILLO_800EVA
 	bool "armadillo 800 eva board"
 
+config TARGET_BLANCHE
+	bool "Blanche board"
+	select DM
+	select DM_SERIAL
+
 config TARGET_GOSE
 	bool "Gose board"
 	select DM
@@ -52,12 +57,12 @@ config SYS_SOC
 
 config RMOBILE_EXTRAM_BOOT
 	bool "Enable boot from RAM"
-	depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
+	depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
 	default n
 
 choice
 	prompt "Qos setting primary"
-	depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
+	depends on TARGET_ALT || TARGET_BLANCHE || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
 	default QOS_PRI_NORMAL
 
 config QOS_PRI_NORMAL
@@ -78,6 +83,7 @@ config QOS_PRI_GFX
 endchoice
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
+source "board/renesas/blanche/Kconfig"
 source "board/renesas/gose/Kconfig"
 source "board/renesas/koelsch/Kconfig"
 source "board/renesas/lager/Kconfig"
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index a598cf9..d5bb843 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
 obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index d47c47c..129ab0c 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -53,6 +53,7 @@ static const struct {
 	{ 0x40, "R8A7740" },
 	{ 0x45, "R8A7790" },
 	{ 0x47, "R8A7791" },
+	{ 0x4A, "R8A7792" },
 	{ 0x4B, "R8A7793" },
 	{ 0x4C, "R8A7794" },
 	{ 0x0, "CPU" },
diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h
index d8703f5..4861bfe0 100644
--- a/arch/arm/mach-rmobile/include/mach/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void);
 #elif defined(CONFIG_R8A7791)
 #include "r8a7791-gpio.h"
 void r8a7791_pinmux_init(void);
+#elif defined(CONFIG_R8A7792)
+#include "r8a7792-gpio.h"
+void r8a7792_pinmux_init(void);
 #elif defined(CONFIG_R8A7793)
 #include "r8a7793-gpio.h"
 void r8a7793_pinmux_init(void);
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h
new file mode 100644
index 0000000..86931c3
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h
@@ -0,0 +1,220 @@
+#ifndef __ASM_R8A7792_GPIO_H__
+#define __ASM_R8A7792_GPIO_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16,
+
+	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+	GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+	GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+	GPIO_GP_6_16,
+
+	GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
+	GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
+	GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
+	GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
+	GPIO_GP_7_16,
+
+	GPIO_GP_8_0, GPIO_GP_8_1, GPIO_GP_8_2, GPIO_GP_8_3,
+	GPIO_GP_8_4, GPIO_GP_8_5, GPIO_GP_8_6, GPIO_GP_8_7,
+	GPIO_GP_8_8, GPIO_GP_8_9, GPIO_GP_8_10, GPIO_GP_8_11,
+	GPIO_GP_8_12, GPIO_GP_8_13, GPIO_GP_8_14, GPIO_GP_8_15,
+	GPIO_GP_8_16,
+
+	GPIO_GP_9_0, GPIO_GP_9_1, GPIO_GP_9_2, GPIO_GP_9_3,
+	GPIO_GP_9_4, GPIO_GP_9_5, GPIO_GP_9_6, GPIO_GP_9_7,
+	GPIO_GP_9_8, GPIO_GP_9_9, GPIO_GP_9_10, GPIO_GP_9_11,
+	GPIO_GP_9_12, GPIO_GP_9_13, GPIO_GP_9_14, GPIO_GP_9_15,
+	GPIO_GP_9_16,
+
+	GPIO_GP_10_0, GPIO_GP_10_1, GPIO_GP_10_2, GPIO_GP_10_3,
+	GPIO_GP_10_4, GPIO_GP_10_5, GPIO_GP_10_6, GPIO_GP_10_7,
+	GPIO_GP_10_8, GPIO_GP_10_9, GPIO_GP_10_10, GPIO_GP_10_11,
+	GPIO_GP_10_12, GPIO_GP_10_13, GPIO_GP_10_14, GPIO_GP_10_15,
+	GPIO_GP_10_16, GPIO_GP_10_17, GPIO_GP_10_18, GPIO_GP_10_19,
+	GPIO_GP_10_20, GPIO_GP_10_21, GPIO_GP_10_22, GPIO_GP_10_23,
+	GPIO_GP_10_24, GPIO_GP_10_25, GPIO_GP_10_26, GPIO_GP_10_27,
+	GPIO_GP_10_28, GPIO_GP_10_29, GPIO_GP_10_30, GPIO_GP_10_31,
+
+	GPIO_GP_11_0, GPIO_GP_11_1, GPIO_GP_11_2, GPIO_GP_11_3,
+	GPIO_GP_11_4, GPIO_GP_11_5, GPIO_GP_11_6, GPIO_GP_11_7,
+	GPIO_GP_11_8, GPIO_GP_11_9, GPIO_GP_11_10, GPIO_GP_11_11,
+	GPIO_GP_11_12, GPIO_GP_11_13, GPIO_GP_11_14, GPIO_GP_11_15,
+	GPIO_GP_11_16, GPIO_GP_11_17, GPIO_GP_11_18, GPIO_GP_11_19,
+	GPIO_GP_11_20, GPIO_GP_11_21, GPIO_GP_11_22, GPIO_GP_11_23,
+	GPIO_GP_11_24, GPIO_GP_11_25, GPIO_GP_11_26, GPIO_GP_11_27,
+	GPIO_GP_11_28, GPIO_GP_11_29,
+
+	GPIO_FN_DU1_DB2_C0_DATA12, GPIO_FN_DU1_DB3_C1_DATA13,
+	GPIO_FN_DU1_DB4_C2_DATA14, GPIO_FN_DU1_DB5_C3_DATA15,
+	GPIO_FN_DU1_DB6_C4, GPIO_FN_DU1_DB7_C5, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
+	GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_DU1_DISP, GPIO_FN_DU1_CDE,
+
+	GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
+	GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, GPIO_FN_D11,
+	GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, GPIO_FN_A0, GPIO_FN_A1,
+	GPIO_FN_A2, GPIO_FN_A3, GPIO_FN_A4, GPIO_FN_A5, GPIO_FN_A6, GPIO_FN_A7,
+	GPIO_FN_A8, GPIO_FN_A9, GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
+	GPIO_FN_A14, GPIO_FN_A15,
+
+	GPIO_FN_A16, GPIO_FN_A17, GPIO_FN_A18, GPIO_FN_A19,
+	GPIO_FN_CS1_A26, GPIO_FN_EX_CS0, GPIO_FN_EX_CS1, GPIO_FN_EX_CS2,
+	GPIO_FN_EX_CS3, GPIO_FN_EX_CS4, GPIO_FN_EX_CS5, GPIO_FN_BS,
+	GPIO_FN_RD, GPIO_FN_RD_WR, GPIO_FN_WE0, GPIO_FN_WE1, GPIO_FN_EX_WAIT0,
+	GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3, GPIO_FN_CS0,
+
+	GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_VSYNC,
+	GPIO_FN_VI0_D0_B0_C0, GPIO_FN_VI0_D1_B1_C1, GPIO_FN_VI0_D2_B2_C2, GPIO_FN_VI0_D3_B3_C3,
+	GPIO_FN_VI0_D4_B4_C4, GPIO_FN_VI0_D5_B5_C5, GPIO_FN_VI0_D6_B6_C6, GPIO_FN_VI0_D7_B7_C7,
+	GPIO_FN_VI0_D8_G0_Y0, GPIO_FN_VI0_D9_G1_Y1, GPIO_FN_VI0_D10_G2_Y2, GPIO_FN_VI0_D11_G3_Y3,
+	GPIO_FN_VI0_FIELD,
+
+	GPIO_FN_VI1_CLK, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_HSYNC,
+	GPIO_FN_VI1_VSYNC, GPIO_FN_VI1_D0_B0_C0, GPIO_FN_VI1_D1_B1_C1,
+	GPIO_FN_VI1_D2_B2_C2, GPIO_FN_VI1_D3_B3_C3, GPIO_FN_VI1_D4_B4_C4,
+	GPIO_FN_VI1_D5_B5_C5, GPIO_FN_VI1_D6_B6_C6, GPIO_FN_VI1_D7_B7_C7,
+	GPIO_FN_VI1_D8_G0_Y0, GPIO_FN_VI1_D9_G1_Y1, GPIO_FN_VI1_D10_G2_Y2,
+	GPIO_FN_VI1_D11_G3_Y3, GPIO_FN_VI1_FIELD,
+
+	GPIO_FN_VI3_D10_Y2, GPIO_FN_VI3_FIELD,
+
+	GPIO_FN_VI4_CLK,
+
+	GPIO_FN_VI5_CLK, GPIO_FN_VI5_D9_Y1, GPIO_FN_VI5_D10_Y2, GPIO_FN_VI5_D11_Y3, GPIO_FN_VI5_FIELD,
+
+	GPIO_FN_HRTS0, GPIO_FN_HCTS1, GPIO_FN_SCK0, GPIO_FN_CTS0, GPIO_FN_RTS0, GPIO_FN_TX0,
+	GPIO_FN_RX0, GPIO_FN_SCK1, GPIO_FN_CTS1, GPIO_FN_RTS1, GPIO_FN_TX1, GPIO_FN_RX1,
+	GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_TX, GPIO_FN_CAN0_RX,
+	GPIO_FN_CAN_CLK, GPIO_FN_CAN1_TX, GPIO_FN_CAN1_RX,
+
+	GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, GPIO_FN_SD0_DAT0,
+	GPIO_FN_SD0_DAT1, GPIO_FN_SD0_DAT2, GPIO_FN_SD0_DAT3,
+	GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, GPIO_FN_ADICLK,
+	GPIO_FN_ADICS_SAMP, GPIO_FN_ADIDATA, GPIO_FN_ADICHS0,
+	GPIO_FN_ADICHS1, GPIO_FN_ADICHS2, GPIO_FN_AVS1, GPIO_FN_AVS2,
+
+	GPIO_FN_DU0_DR0_DATA0, GPIO_FN_DU0_DR1_DATA1, GPIO_FN_DU0_DR2_Y4_DATA2,
+	GPIO_FN_DU0_DR3_Y5_DATA3, GPIO_FN_DU0_DR4_Y6_DATA4, GPIO_FN_DU0_DR5_Y7_DATA5,
+	GPIO_FN_DU0_DR6_Y8_DATA6, GPIO_FN_DU0_DR7_Y9_DATA7, GPIO_FN_DU0_DG0_DATA8,
+	GPIO_FN_DU0_DG1_DATA9, GPIO_FN_DU0_DG2_C6_DATA10, GPIO_FN_DU0_DG3_C7_DATA11,
+	GPIO_FN_DU0_DG4_Y0_DATA12, GPIO_FN_DU0_DG5_Y1_DATA13, GPIO_FN_DU0_DG6_Y2_DATA14,
+	GPIO_FN_DU0_DG7_Y3_DATA15, GPIO_FN_DU0_DB0, GPIO_FN_DU0_DB1,
+	GPIO_FN_DU0_DB2_C0, GPIO_FN_DU0_DB3_C1, GPIO_FN_DU0_DB4_C2,
+	GPIO_FN_DU0_DB5_C3, GPIO_FN_DU0_DB6_C4, GPIO_FN_DU0_DB7_C5,
+
+	GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_DU0_EXVSYNC_DU0_VSYNC,
+	GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_DU0_DISP, GPIO_FN_DU0_CDE,
+	GPIO_FN_DU1_DR2_Y4_DATA0, GPIO_FN_DU1_DR3_Y5_DATA1, GPIO_FN_DU1_DR4_Y6_DATA2,
+	GPIO_FN_DU1_DR5_Y7_DATA3, GPIO_FN_DU1_DR6_DATA4, GPIO_FN_DU1_DR7_DATA5,
+	GPIO_FN_DU1_DG2_C6_DATA6, GPIO_FN_DU1_DG3_C7_DATA7, GPIO_FN_DU1_DG4_Y0_DATA8,
+	GPIO_FN_DU1_DG5_Y1_DATA9, GPIO_FN_DU1_DG6_Y2_DATA10, GPIO_FN_DU1_DG7_Y3_DATA11,
+	GPIO_FN_A20, GPIO_FN_MOSI_IO0, GPIO_FN_A21, GPIO_FN_MISO_IO1, GPIO_FN_A22, GPIO_FN_IO2,
+	GPIO_FN_A23, GPIO_FN_IO3, GPIO_FN_A24, GPIO_FN_SPCLK, GPIO_FN_A25, GPIO_FN_SSL,
+
+	GPIO_FN_VI2_CLK, GPIO_FN_AVB_RX_CLK, GPIO_FN_VI2_CLKENB, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_VI2_HSYNC, GPIO_FN_AVB_RXD0, GPIO_FN_VI2_VSYNC, GPIO_FN_AVB_RXD1,
+	GPIO_FN_VI2_D0_C0, GPIO_FN_AVB_RXD2, GPIO_FN_VI2_D1_C1, GPIO_FN_AVB_RXD3,
+	GPIO_FN_VI2_D2_C2, GPIO_FN_AVB_RXD4, GPIO_FN_VI2_D3_C3, GPIO_FN_AVB_RXD5,
+	GPIO_FN_VI2_D4_C4, GPIO_FN_AVB_RXD6, GPIO_FN_VI2_D5_C5, GPIO_FN_AVB_RXD7,
+	GPIO_FN_VI2_D6_C6, GPIO_FN_AVB_RX_ER, GPIO_FN_VI2_D7_C7, GPIO_FN_AVB_COL,
+	GPIO_FN_VI2_D8_Y0, GPIO_FN_AVB_TXD3, GPIO_FN_VI2_D9_Y1, GPIO_FN_AVB_TX_EN,
+	GPIO_FN_VI2_D10_Y2, GPIO_FN_AVB_TXD0, GPIO_FN_VI2_D11_Y3, GPIO_FN_AVB_TXD1,
+	GPIO_FN_VI2_FIELD, GPIO_FN_AVB_TXD2,
+
+	GPIO_FN_VI3_CLK, GPIO_FN_AVB_TX_CLK, GPIO_FN_VI3_CLKENB, GPIO_FN_AVB_TXD4,
+	GPIO_FN_VI3_HSYNC, GPIO_FN_AVB_TXD5, GPIO_FN_VI3_VSYNC, GPIO_FN_AVB_TXD6,
+	GPIO_FN_VI3_D0_C0, GPIO_FN_AVB_TXD7, GPIO_FN_VI3_D1_C1, GPIO_FN_AVB_TX_ER,
+	GPIO_FN_VI3_D2_C2, GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI3_D3_C3, GPIO_FN_AVB_MDC,
+	GPIO_FN_VI3_D4_C4, GPIO_FN_AVB_MDIO, GPIO_FN_VI3_D5_C5, GPIO_FN_AVB_LINK,
+	GPIO_FN_VI3_D6_C6, GPIO_FN_AVB_MAGIC, GPIO_FN_VI3_D7_C7, GPIO_FN_AVB_PHY_INT,
+	GPIO_FN_VI3_D8_Y0, GPIO_FN_AVB_CRS, GPIO_FN_VI3_D9_Y1, GPIO_FN_AVB_GTXREFCLK,
+	GPIO_FN_VI3_D11_Y3,
+
+	GPIO_FN_VI4_CLKENB, GPIO_FN_VI0_D12_G4_Y4, GPIO_FN_VI4_HSYNC, GPIO_FN_VI0_D13_G5_Y5,
+	GPIO_FN_VI4_VSYNC, GPIO_FN_VI0_D14_G6_Y6, GPIO_FN_VI4_D0_C0, GPIO_FN_VI0_D15_G7_Y7,
+	GPIO_FN_VI4_D1_C1, GPIO_FN_VI0_D16_R0, GPIO_FN_VI1_D12_G4_Y4_0,
+	GPIO_FN_VI4_D2_C2, GPIO_FN_VI0_D17_R1, GPIO_FN_VI1_D13_G5_Y5_0,
+	GPIO_FN_VI4_D3_C3, GPIO_FN_VI0_D18_R2, GPIO_FN_VI1_D14_G6_Y6_0,
+	GPIO_FN_VI4_D4_C4, GPIO_FN_VI0_D19_R3, GPIO_FN_VI1_D15_G7_Y7_0,
+	GPIO_FN_VI4_D5_C5, GPIO_FN_VI0_D20_R4, GPIO_FN_VI2_D12_Y4,
+	GPIO_FN_VI4_D6_C6, GPIO_FN_VI0_D21_R5, GPIO_FN_VI2_D13_Y5,
+	GPIO_FN_VI4_D7_C7, GPIO_FN_VI0_D22_R6, GPIO_FN_VI2_D14_Y6,
+	GPIO_FN_VI4_D8_Y0, GPIO_FN_VI0_D23_R7, GPIO_FN_VI2_D15_Y7,
+	GPIO_FN_VI4_D9_Y1, GPIO_FN_VI3_D12_Y4, GPIO_FN_VI4_D10_Y2, GPIO_FN_VI3_D13_Y5,
+	GPIO_FN_VI4_D11_Y3, GPIO_FN_VI3_D14_Y6, GPIO_FN_VI4_FIELD, GPIO_FN_VI3_D15_Y7,
+
+	GPIO_FN_VI5_CLKENB, GPIO_FN_VI1_D12_G4_Y4_1, GPIO_FN_VI5_HSYNC, GPIO_FN_VI1_D13_G5_Y5_1,
+	GPIO_FN_VI5_VSYNC, GPIO_FN_VI1_D14_G6_Y6_1, GPIO_FN_VI5_D0_C0, GPIO_FN_VI1_D15_G7_Y7_1,
+	GPIO_FN_VI5_D1_C1, GPIO_FN_VI1_D16_R0, GPIO_FN_VI5_D2_C2, GPIO_FN_VI1_D17_R1,
+	GPIO_FN_VI5_D3_C3, GPIO_FN_VI1_D18_R2, GPIO_FN_VI5_D4_C4, GPIO_FN_VI1_D19_R3,
+	GPIO_FN_VI5_D5_C5, GPIO_FN_VI1_D20_R4, GPIO_FN_VI5_D6_C6, GPIO_FN_VI1_D21_R5,
+	GPIO_FN_VI5_D7_C7, GPIO_FN_VI1_D22_R6, GPIO_FN_VI5_D8_Y0, GPIO_FN_VI1_D23_R7,
+
+	GPIO_FN_MSIOF0_SCK, GPIO_FN_HSCK0, GPIO_FN_MSIOF0_SYNC, GPIO_FN_HCTS0,
+	GPIO_FN_MSIOF0_TXD, GPIO_FN_HTX0, GPIO_FN_MSIOF0_RXD, GPIO_FN_HRX0,
+	GPIO_FN_MSIOF1_SCK, GPIO_FN_HSCK1, GPIO_FN_MSIOF1_SYNC, GPIO_FN_HRTS1,
+	GPIO_FN_MSIOF1_TXD, GPIO_FN_HTX1, GPIO_FN_MSIOF1_RXD, GPIO_FN_HRX1,
+	GPIO_FN_DRACK0, GPIO_FN_SCK2, GPIO_FN_DACK0, GPIO_FN_TX2,
+	GPIO_FN_DREQ0, GPIO_FN_RX2, GPIO_FN_DACK1, GPIO_FN_SCK3,
+	GPIO_FN_TX3, GPIO_FN_DREQ1, GPIO_FN_RX3,
+
+	GPIO_FN_PWM0, GPIO_FN_TCLK1, GPIO_FN_FSO_CFE_0,
+	GPIO_FN_PWM1, GPIO_FN_TCLK2, GPIO_FN_FSO_CFE_1,
+	GPIO_FN_PWM2, GPIO_FN_TCLK3, GPIO_FN_FSO_TOE,
+	GPIO_FN_PWM3, GPIO_FN_PWM4, GPIO_FN_SSI_SCK3, GPIO_FN_TPU0TO0,
+	GPIO_FN_SSI_WS3, GPIO_FN_TPU0TO1, GPIO_FN_SSI_SDATA3, GPIO_FN_TPU0TO2,
+	GPIO_FN_SSI_SCK4, GPIO_FN_TPU0TO3, GPIO_FN_SSI_WS4,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_AUDIO_CLKOUT,
+	GPIO_FN_AUDIO_CLKA, GPIO_FN_AUDIO_CLKB,
+};
+
+#endif /* __ASM_R8A7792_GPIO_H__ */
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h
new file mode 100644
index 0000000..be57d3c
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7792.h
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_R8A7792_H
+#define __ASM_ARCH_R8A7792_H
+
+#include "rcar-base.h"
+
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
+#define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS	0x00400801
+#define MSTP1_BITS	0x9B6F987F
+#define MSTP2_BITS	0x108CE100
+#define MSTP3_BITS	0x20004010
+#define MSTP4_BITS	0x80000184
+#define MSTP5_BITS	0x44C00004
+#define MSTP7_BITS	0x01BF0000
+#define MSTP8_BITS	0x1FE01FB0
+#define MSTP9_BITS	0xFE2BFFB2
+#define MSTP10_BITS	0x00001820
+#define MSTP11_BITS	0x00000008
+
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
+
+#endif /* __ASM_ARCH_R8A7792_H */
diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h
index 53ead26..709bc75 100644
--- a/arch/arm/mach-rmobile/include/mach/rcar-base.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h
@@ -10,7 +10,7 @@
 #define __ASM_ARCH_RCAR_BASE_H
 
 /*
- * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses
  */
 #define RWDT_BASE		0xE6020000
 #define SWDT_BASE		0xE6030000
@@ -142,6 +142,12 @@
 
 #define SYS_AXI_SYX64TO128_BASE	0xFF800300
 #define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_AX2M_BASE	0xFF800380
+#define SYS_AXI_CC50_BASE	0xFF8003C0
+#define SYS_AXI_CCI_BASE	0xFF800440
+#define SYS_AXI_CS_BASE		0xFF800480
+#define SYS_AXI_DDM_BASE	0xFF8004C0
+#define SYS_AXI_ETH_BASE	0xFF800500
 #define SYS_AXI_G2D_BASE	0xFF800540
 #define SYS_AXI_IMP0_BASE	0xFF800580
 #define SYS_AXI_IMP1_BASE	0xFF8005C0
@@ -154,30 +160,49 @@
 #define SYS_AXI_MMUR_BASE	0xFF800780
 #define SYS_AXI_MMUS0_BASE	0xFF8007C0
 #define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MPXM_BASE	0xFF800840
 #define SYS_AXI_MTSB0_BASE	0xFF800880
 #define SYS_AXI_MTSB1_BASE	0xFF8008C0
 #define SYS_AXI_PCI_BASE	0xFF800900
 #define SYS_AXI_RTX_BASE	0xFF800940
-#define SYS_AXI_SDS0_BASE	0xFF800A80
-#define SYS_AXI_SDS1_BASE	0xFF800AC0
-#define SYS_AXI_USB20_BASE	0xFF800C00
-#define SYS_AXI_USB21_BASE	0xFF800C40
-#define SYS_AXI_USB22_BASE	0xFF800C80
-#define SYS_AXI_USB30_BASE	0xFF800CC0
-#define SYS_AXI_AX2M_BASE	0xFF800380
-#define SYS_AXI_CC50_BASE	0xFF8003C0
-#define SYS_AXI_CCI_BASE	0xFF800440
-#define SYS_AXI_CS_BASE		0xFF800480
-#define SYS_AXI_DDM_BASE	0xFF8004C0
-#define SYS_AXI_ETH_BASE	0xFF800500
-#define SYS_AXI_MPXM_BASE	0xFF800840
 #define SYS_AXI_SAT0_BASE	0xFF800980
 #define SYS_AXI_SAT1_BASE	0xFF8009C0
 #define SYS_AXI_SDM0_BASE	0xFF800A00
 #define SYS_AXI_SDM1_BASE	0xFF800A40
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
 #define SYS_AXI_TRAB_BASE	0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
 #define SYS_AXI_UDM0_BASE	0xFF800B80
 #define SYS_AXI_UDM1_BASE	0xFF800BC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+#define SYS_AXI_ADM_BASE	0xFF800D00
+#define SYS_AXI_ADS_BASE	0xFF800D40
+#define SYS_AXI_SYX_BASE	0xFF800FB8
+
+#define SYS_AXI_AXI64TO128W_BASE	0xFF801300
+#define SYS_AXI_AVBW_BASE	0xFF801340
+#define SYS_AXI_CC50W_BASE	0xFF8013C0
+#define SYS_AXI_CCIW_BASE	0xFF801440
+#define SYS_AXI_CSW_BASE	0xFF801480
+#define SYS_AXI_G2DW_BASE	0xFF801540
+#define SYS_AXI_IMUX0W_BASE	0xFF801600
+#define SYS_AXI_IMUX1W_BASE	0xFF801640
+#define SYS_AXI_IMUX2W_BASE	0xFF801680
+#define SYS_AXI_LBSW_BASE	0xFF8016C0
+#define SYS_AXI_RTXW_BASE	0xFF801940
+#define SYS_AXI_SDM0W_BASE	0xFF801A00
+#define SYS_AXI_SDM1W_BASE	0xFF801A40
+#define SYS_AXI_SDS0W_BASE	0xFF801A80
+#define SYS_AXI_SDS1W_BASE	0xFF801AC0
+#define SYS_AXI_TRABW_BASE	0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
+#define SYS_AXI_UDM0W_BASE	0xFF801B80
+#define SYS_AXI_UDM1W_BASE	0xFF801BC0
+#define SYS_AXI_ADMW_BASE	0xFF801D00
+#define SYS_AXI_ADSW_BASE	0xFF801D40
+#define SYS_AXI_SYXW_BASE	0xFF801FB8
 
 #define RT_AXI_SHX_BASE		0xFF810100
 #define RT_AXI_DBG_BASE		0xFF810140 /* R8A7791 only */
@@ -186,6 +211,11 @@
 #define RT_AXI_RTX64TO128_BASE	0xFF810200
 #define RT_AXI_STPRO_BASE	0xFF810240
 #define RT_AXI_SY2RT_BASE	0xFF810280 /* R8A7791 only */
+#define RT_AXI_RT_BASE		0xFF810FC0
+#define RT_AXI_SHXW_BASE	0xFF811100
+#define RT_AXI_DBGW_BASE	0xFF811140
+#define RT_AXI_RTX64TO128W_BASE	0xFF811200
+#define RT_AXI_RTW_BASE		0xFF811FC0
 
 #define MP_AXI_ADSP_BASE	0xFF820100
 #define MP_AXI_ASDS0_BASE	0xFF8201C0
@@ -197,8 +227,16 @@
 
 #define SYS_AXI256_AXI128TO256_BASE	0xFF860100
 #define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_AXM_BASE	0xFF860140
 #define SYS_AXI256_MPX_BASE	0xFF860180
 #define SYS_AXI256_MXI_BASE	0xFF8601C0
+#define SYS_AXI256_IMP0_BASE	0xFF860580
+#define SYS_AXI256_SY2_BASE	0xFF860FC0
+#define SYS_AXI256_AXI128TO256W_BASE	0xFF861100
+#define SYS_AXI256_AXMW_BASE	0xFF861140
+#define SYS_AXI256_MXIW_BASE	0xFF8611C0
+#define SYS_AXI256_IMP0W_BASE	0xFF861580
+#define SYS_AXI256_SY2W_BASE	0xFF861FC0
 
 #define CCI_AXI_MMUS0_BASE	0xFF880100
 #define CCI_AXI_SYX2_BASE	0xFF880140
@@ -227,9 +265,6 @@
 #define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
 #define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
 #define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
-#define MEDIA_AXI_VIN0W_BASE	0xFE966900
-#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
 #define MEDIA_AXI_FDP0R_BASE	0xFE964D40
 #define MEDIA_AXI_FDP0W_BASE	0xFE966D40
 #define MEDIA_AXI_IMSR_BASE	0xFE964D80
@@ -242,12 +277,6 @@
 #define MEDIA_AXI_IMRW_BASE	0xFE967180
 #define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
 #define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
-#define MEDIA_AXI_DU0R_BASE	0xFE965580
-#define MEDIA_AXI_DU0W_BASE	0xFE967580
 #define MEDIA_AXI_DU1R_BASE	0xFE9655C0
 #define MEDIA_AXI_DU1W_BASE	0xFE9675C0
 #define MEDIA_AXI_VCP0CR_BASE	0xFE965900
@@ -261,8 +290,66 @@
 #define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
 #define MEDIA_AXI_VPC1R_BASE	0xFE965D80
 
+#if defined (CONFIG_R8A7792)
+#define MEDIA_AXI_VCTU0R_BASE	0xFE964500 /* R8A7792 */
+#define MEDIA_AXI_VCTU0W_BASE	0xFE966500
+#define MEDIA_AXI_VDCTU0R_BASE	0xFE964540
+#define MEDIA_AXI_VDCTU0W_BASE	0xFE966540
+#define MEDIA_AXI_VDCTU1R_BASE	0xFE964580
+#define MEDIA_AXI_VDCTU1W_BASE	0xFE966580
+#define MEDIA_AXI_VIN0W_BASE	0xFE967580
+#define MEDIA_AXI_VIN1W_BASE	0xFE966D80
+#define MEDIA_AXI_RDRW_BASE	0xFE9675C0
+#define MEDIA_AXI_IMS01R_BASE	0xFE965500
+#define MEDIA_AXI_IMS01W_BASE	0xFE967500
+#define MEDIA_AXI_IMS23R_BASE	0xFE965540 /* FIXME */
+#define MEDIA_AXI_IMS23W_BASE	0xFE967540
+#define MEDIA_AXI_IMS45R_BASE	0xFE964D00
+#define MEDIA_AXI_IMS45W_BASE	0xFE966D00
+#define MEDIA_AXI_ROTCE4R_BASE	0xFE965100
+#define MEDIA_AXI_ROTCE4W_BASE	0xFE967100
+#define MEDIA_AXI_ROTVLC4R_BASE	0xFE965140
+#define MEDIA_AXI_ROTVLC4W_BASE	0xFE965140
+#define MEDIA_AXI_VSPD0R_BASE	0xFE964900
+#define MEDIA_AXI_VSPD0W_BASE	0xFE966900
+#define MEDIA_AXI_VSPD1R_BASE	0xFE964940
+#define MEDIA_AXI_VSPD1W_BASE	0xFE966940
+#define MEDIA_AXI_DU0R_BASE	0xFE964980
+#define MEDIA_AXI_DU0W_BASE	0xFE966980
+#define MEDIA_AXI_VSP0R_BASE	0xFE9649C0
+#define MEDIA_AXI_VSP0W_BASE	0xFE9669C0
+#define MEDIA_AXI_ROTCE0R_BASE	0xFE965900
+#define MEDIA_AXI_ROTCE0W_BASE	0xFE967900
+#define MEDIA_AXI_ROTVLC0R_BASE	0xFE965940
+#define MEDIA_AXI_ROTVLC0W_BASE	0xFE967940
+#define MEDIA_AXI_ROTCE1R_BASE	0xFE965980
+#define MEDIA_AXI_ROTCE1W_BASE	0xFE967980
+#define MEDIA_AXI_ROTVLC1R_BASE	0xFE9659C0
+#define MEDIA_AXI_ROTVLC1W_BASE	0xFE9679C0
+#define MEDIA_AXI_ROTCE2R_BASE	0xFE965D00
+#define MEDIA_AXI_ROTCE2W_BASE	0xFE967D00
+#define MEDIA_AXI_ROTVLC2R_BASE	0xFE965D40
+#define MEDIA_AXI_ROTVLC2W_BASE	0xFE967D40
+#define MEDIA_AXI_ROTCE3R_BASE	0xFE965D80
+#define MEDIA_AXI_ROTCE3W_BASE	0xFE967D80
+#define MEDIA_AXI_ROTVLC3R_BASE	0xFE965DC0
+#define MEDIA_AXI_ROTVLC3W_BASE	0xFE967DC0
+#else	/* R8A7792 */
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#endif	/* R8A7792 */
+
+
 #define SYS_AXI_AVBDMSCR	0xFF802000
 #define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_AX2MDMSCR	0xFF802004
 #define SYS_AXI_CC50DMSCR	0xFF802008
 #define SYS_AXI_CC51DMSCR	0xFF80200C
 #define SYS_AXI_CCIDMSCR	0xFF802010
@@ -301,6 +388,7 @@
 #define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
 #define SYS_AXI_AVBSLVDMSCR	0xFF802108
 #define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_AX2SLVDMSCR	0xFF80210C
 #define SYS_AXI_ETHSLVDMSCR	0xFF802110
 #define SYS_AXI_GICSLVDMSCR	0xFF802114
 #define SYS_AXI_IMPSLVDMSCR	0xFF802118
@@ -318,6 +406,11 @@
 #define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
 #define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
 #define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAPC1SLVDMSCR	0xFF802154
+#define SYS_AXI_SAPC2SLVDMSCR	0xFF802158
+#define SYS_AXI_SAPC3SLVDMSCR	0xFF80215C
+#define SYS_AXI_SAPC65SLVDMSCR	0xFF802160
+#define SYS_AXI_SAPC8SLVDMSCR	0xFF802164
 #define SYS_AXI_SAT0SLVDMSCR	0xFF802168
 #define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
 #define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
@@ -325,8 +418,10 @@
 #define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
 #define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
 #define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_SGXSLV1SLVDMSCR	0xFF802184
 #define SYS_AXI_STBSLVDMSCR	0xFF802188
 #define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR	0xFF802190
 #define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
 #define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
 #define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
@@ -334,6 +429,32 @@
 #define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
 #define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
 #define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+#define SYS_AXI_UTLBDSSLVDMSCR	0xFF8021B0
+#define SYS_AXI_UTLBS0SLVDMSCR	0xFF8021B4
+#define SYS_AXI_UTLBS1SLVDMSCR	0xFF8021B8
+#define	SYS_AXI_ROT0DMSCR	0xFF802320
+#define	SYS_AXI_ROT1DMSCR	0xFF802324
+#define	SYS_AXI_ROT2DMSCR	0xFF802328
+#define	SYS_AXI_ROT3DMSCR	0xFF80232C
+#define	SYS_AXI_ROT4DMSCR	0xFF802330
+#define	SYS_AXI_IMUX3SLVDMSCR	0xFF802334
+#define	SYS_AXI_STBR0SLVDMSCR	0xFF803200
+#define	SYS_AXI_STBR0PSLVDMSCR	0xFF803204
+#define	SYS_AXI_STBR0XSLVDMSCR	0xFF803208
+#define	SYS_AXI_STBR1SLVDMSCR	0xFF803210
+#define	SYS_AXI_STBR1PSLVDMSCR	0xFF803214
+#define	SYS_AXI_STBR1XSLVDMSCR	0xFF803218
+#define	SYS_AXI_STBR2SLVDMSCR	0xFF803220
+#define	SYS_AXI_STBR2PSLVDMSCR	0xFF803224
+#define	SYS_AXI_STBR2XSLVDMSCR	0xFF803228
+#define	SYS_AXI_STBR3SLVDMSCR	0xFF803230
+#define	SYS_AXI_STBR3PSLVDMSCR	0xFF803234
+#define	SYS_AXI_STBR3XSLVDMSCR	0xFF803238
+#define	SYS_AXI_STBR4SLVDMSCR	0xFF803240
+#define	SYS_AXI_STBR4PSLVDMSCR	0xFF803244
+#define	SYS_AXI_STBR4XSLVDMSCR	0xFF803248
+#define	SYS_AXI_ADM_DMSCR	0xFF803260
+#define	SYS_AXI_ADS_DMSCR	0xFF803264
 
 #define RT_AXI_CBMDMSCR		0xFF812000
 #define RT_AXI_DBDMSCR		0xFF812004
@@ -380,9 +501,86 @@
 #define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
 #define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
 
+#define	DM_AXI_DMAXICONF	0xFF850000
+#define	DM_AXI_DMAPBCONF	0xFF850004
+#define	DM_AXI_DMADMCONF	0xFF850020
+#define	DM_AXI_DMSDM0CONF	0xFF850024
+#define	DM_AXI_DMSDM1CONF	0xFF850028
+#define	DM_AXI_DMQSPAPSLVCONF	0xFF850030
+#define	DM_AXI_RAPD4SLVCONF	0xFF850034
+#define	DM_AXI_SAPD4SLVCONF	0xFF85003C
+#define	DM_AXI_SAPD5SLVCONF	0xFF850040
+#define	DM_AXI_SAPD6SLVCONF	0xFF850044
+#define	DM_AXI_SAPD65DSLVCONF	0xFF850048
+#define	DM_AXI_SDAP0SLVCONF	0xFF85004C
+#define	DM_AXI_MAPD2SLVCONF	0xFF850050
+#define	DM_AXI_MAPD3SLVCONF	0xFF850054
+#define	DM_AXI_DMXXDEFAULTSLAVESLVCONF	0xFF850058
+#define	DM_AXI_DMADMRQOSCONF	0xFF850100
+#define	DM_AXI_DMADMRQOSCTSET0	0xFF850104
+#define	DM_AXI_DMADMRQOSREQCTR	0xFF850114
+#define	DM_AXI_DMADMRQOSQON	0xFF850124
+#define	DM_AXI_DMADMRQOSIN	0xFF850128
+#define	DM_AXI_DMADMRQOSSTAT	0xFF85012C
+#define	DM_AXI_DMSDM0RQOSCONF	0xFF850140
+#define	DM_AXI_DMSDM0RQOSCTSET0	0xFF850144
+#define	DM_AXI_DMSDM0RQOSREQCTR	0xFF850154
+#define	DM_AXI_DMSDM0RQOSQON	0xFF850164
+#define	DM_AXI_DMSDM0RQOSIN	0xFF850168
+#define	DM_AXI_DMSDM0RQOSSTAT	0xFF85016C
+#define	DM_AXI_DMSDM1RQOSCONF	0xFF850180
+#define	DM_AXI_DMSDM1RQOSCTSET0	0xFF850184
+#define	DM_AXI_DMSDM1RQOSREQCTR	0xFF850194
+#define	DM_AXI_DMSDM1RQOSQON	0xFF8501A4
+#define	DM_AXI_DMSDM1RQOSIN	0xFF8501A8
+#define	DM_AXI_DMSDM1RQOSSTAT	0xFF8501AC
+#define	DM_AXI_DMRQOSCTSET1	0xFF850FC0
+#define	DM_AXI_DMRQOSCTSET2	0xFF850FC4
+#define	DM_AXI_DMRQOSCTSET3	0xFF850FC8
+#define	DM_AXI_DMRQOSTHRES0	0xFF850FCC
+#define	DM_AXI_DMRQOSTHRES1	0xFF850FD0
+#define	DM_AXI_DMRQOSTHRES2	0xFF850FD4
+#define	DM_AXI_DMADMWQOSCONF	0xFF851100
+#define	DM_AXI_DMADMWQOSCTSET0	0xFF851104
+#define	DM_AXI_DMADMWQOSREQCTR	0xFF851114
+#define	DM_AXI_DMADMWQOSQON	0xFF851124
+#define	DM_AXI_DMADMWQOSIN	0xFF851128
+#define	DM_AXI_DMADMWQOSSTAT	0xFF85112C
+#define	DM_AXI_DMSDM0WQOSCONF	0xFF851140
+#define	DM_AXI_DMSDM0WQOSCTSET0	0xFF851144
+#define	DM_AXI_DMSDM0WQOSREQCTR	0xFF851154
+#define	DM_AXI_DMSDM0WQOSQON	0xFF851164
+#define	DM_AXI_DMSDM0WQOSIN	0xFF851168
+#define	DM_AXI_DMSDM0WQOSSTAT	0xFF85116C
+#define	DM_AXI_DMSDM1WQOSCONF	0xFF851180
+#define	DM_AXI_DMSDM1WQOSCTSET0	0xFF851184
+#define	DM_AXI_DMSDM1WQOSREQCTR	0xFF851194
+#define	DM_AXI_DMSDM1WQOSQON	0xFF8511A4
+#define	DM_AXI_DMSDM1WQOSIN	0xFF8511A8
+#define	DM_AXI_DMSDM1WQOSSTAT	0xFF8511AC
+#define	DM_AXI_DMWQOSCTSET1	0xFF851FC0
+#define	DM_AXI_DMWQOSCTSET2	0xFF851FC4
+#define	DM_AXI_DMWQOSCTSET3	0xFF851FC8
+#define	DM_AXI_DMWQOSTHRES0	0xFF851FCC
+#define	DM_AXI_DMWQOSTHRES1	0xFF851FD0
+#define	DM_AXI_DMWQOSTHRES2	0xFF851FD4
+
 #define DM_AXI_RDMDMSCR		0xFF852000
 #define DM_AXI_SDM0DMSCR	0xFF852004
 #define DM_AXI_SDM1DMSCR	0xFF852008
+#if defined(CONFIG_R8A7792)
+#define	DM_AXI_DMQSPAPSLVDMSCR	0xFF852104
+#define	DM_AXI_RAPD4SLVDMSCR	0xFF852108
+#define	DM_AXI_SAPD4SLVDMSCR	0xFF852110
+#define	DM_AXI_SAPD5SLVDMSCR	0xFF852114
+#define	DM_AXI_SAPD6SLVDMSCR	0xFF852118
+#define	DM_AXI_SAPD65DSLVDMSCR	0xFF85211C
+#define	DM_AXI_SDAP0SLVDMSCR	0xFF852120
+#define	DM_AXI_MAPD2SLVDMSCR	0xFF852124
+#define	DM_AXI_MAPD3SLVDMSCR	0xFF852128
+#define	DM_AXI_DMXXDEFAULTSLAVESLVDMSCR	0xFF85212C
+#define	DM_AXI_DMXREGDMSENN	0xFF852200
+#else
 #define DM_AXI_MMAP0SLVDMSCR	0xFF852100
 #define DM_AXI_MMAP1SLVDMSCR	0xFF852104
 #define DM_AXI_QSPAPSLVDMSCR	0xFF852108
@@ -396,6 +594,7 @@
 #define DM_AXI_SDAP1SLVDMSCR	0xFF852128
 #define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
 #define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+#endif
 
 #define SYS_AXI256_SYXDMSCR	0xFF862000
 #define SYS_AXI256_MPXDMSCR	0xFF862004
@@ -407,6 +606,16 @@
 #define SYS_AXI256_S3CSLVDMSCR	0xFF862110
 
 #define MXT_SYXDMSCR		0xFF872000
+#if defined(CONFIG_R8A7792)
+#define	MXT_IMRSLVDMSCR		0xFF872110
+#define	MXT_VINSLVDMSCR		0xFF872114
+#define	MXT_VSP1SLVDMSCR	0xFF87211C
+#define	MXT_VSPD0SLVDMSCR	0xFF872120
+#define	MXT_VSPD1SLVDMSCR	0xFF872124
+#define	MXT_MAP1SLVDMSCR	0xFF872128
+#define	MXT_MAP2SLVDMSCR	0xFF87212C
+#define	MXT_MAP2BSLVDMSCR	0xFF872134
+#else	/* R8A7792 */
 #define MXT_CMM0SLVDMSCR	0xFF872100
 #define MXT_CMM1SLVDMSCR	0xFF872104
 #define MXT_CMM2SLVDMSCR	0xFF872108
@@ -421,6 +630,58 @@
 #define MXT_VSPD1SLVDMSCR	0xFF87212C
 #define MXT_MAP1SLVDMSCR	0xFF872130
 #define MXT_MAP2SLVDMSCR	0xFF872134
+#endif	/* R8A7792 */
+
+/* DMS Register (MXI) */
+#if defined(CONFIG_R8A7792)
+#define	MXI_JPURDMSCR		0xFE964200
+#define	MXI_JPUWDMSCR		0xFE966200
+#define	MXI_VCTU0RDMSCR		0xFE964600
+#define	MXI_VCTU0WDMSCR		0xFE966600
+#define	MXI_VDCTU0RDMSCR	0xFE964604
+#define	MXI_VDCTU0WDMSCR	0xFE966604
+#define	MXI_VDCTU1RDMSCR	0xFE964608
+#define	MXI_VDCTU1WDMSCR	0xFE966608
+#define	MXI_VIN0WDMSCR		0xFE967608
+#define	MXI_VIN1WDMSCR		0xFE966E08
+#define	MXI_RDRWDMSCR		0xFE96760C
+#define	MXI_IMS01RDMSCR		0xFE965600
+#define	MXI_IMS01WDMSCR		0xFE967600
+#define	MXI_IMS23RDMSCR		0xFE965604
+#define	MXI_IMS23WDMSCR		0xFE967604
+#define	MXI_IMS45RDMSCR		0xFE964E00
+#define	MXI_IMS45WDMSCR		0xFE966E00
+#define	MXI_IMRRDMSCR		0xFE964E04
+#define	MXI_IMRWDMSCR		0xFE966E04
+#define	MXI_ROTCE4RDMSCR	0xFE965200
+#define	MXI_ROTCE4WDMSCR	0xFE967200
+#define	MXI_ROTVLC4RDMSCR	0xFE965204
+#define	MXI_ROTVLC4WDMSCR	0xFE967204
+#define	MXI_VSPD0RDMSCR		0xFE964A00
+#define	MXI_VSPD0WDMSCR		0xFE966A00
+#define	MXI_VSPD1RDMSCR		0xFE964A04
+#define	MXI_VSPD1WDMSCR		0xFE966A04
+#define	MXI_DU0RDMSCR		0xFE964A08
+#define	MXI_DU0WDMSCR		0xFE966A08
+#define	MXI_VSP0RDMSCR		0xFE964A0C
+#define	MXI_VSP0WDMSCR		0xFE966A0C
+#define	MXI_ROTCE0RDMSCR	0xFE965A00
+#define	MXI_ROTCE0WDMSCR	0xFE967A00
+#define	MXI_ROTVLC0RDMSCR	0xFE965A04
+#define	MXI_ROTVLC0WDMSCR	0xFE967A04
+#define	MXI_ROTCE1RDMSCR	0xFE965A08
+#define	MXI_ROTCE1WDMSCR	0xFE967A08
+#define	MXI_ROTVLC1RDMSCR	0xFE965A0C
+#define	MXI_ROTVLC1WDMSCR	0xFE967A0C
+#define	MXI_ROTCE2RDMSCR	0xFE965E00
+#define	MXI_ROTCE2WDMSCR	0xFE967E00
+#define	MXI_ROTVLC2RDMSCR	0xFE965E04
+#define	MXI_ROTVLC2WDMSCR	0xFE967E04
+#define	MXI_ROTCE3RDMSCR	0xFE965E08
+#define	MXI_ROTCE3WDMSCR	0xFE967E08
+#define	MXI_ROTVLC3RDMSCR	0xFE965E0C
+#define	MXI_ROTVLC3WDMSCR	0xFE967E0C
+#endif	/* R8A7792 */
 
 #define CCI_AXI_MMUS0DMSCR	0xFF882000
 #define CCI_AXI_SYX2DMSCR	0xFF882004
@@ -597,6 +858,81 @@ struct rcar_dbsc3 {
 	u32 dbwt0cnf2;
 	u32 dbwt0cnf3;
 	u32 dbwt0cnf4;
+	u32 dummy17[27];	/* 0x394 .. 0x3FC */
+	u32 dbeccmode;
+	u32 dummy18[3];		/* 0x404 .. 0x40C */
+	u32 dbeccarea0;
+	u32 dbeccarea1;
+	u32 dbeccarea2;
+	u32 dbeccarea3;
+	u32 dummy19[4];		/* 0x420 .. 0x42C */
+	u32 dbeccintenable;
+	u32 dbeccintdetect;
+	u32 dummy20[22];	/* 0x438 .. 0x48C */
+	u32 dbeccmodulcnt;
+	u32 dummy21[27];	/* 0x494 .. 0x4FC */
+	u32 dbschecnt0;
+	u32 dummy22[63];	/* 0x504 .. 0x5FC */
+	u32 dbreradr0;
+	u32 dbreblane0;
+	u32 dbrerid0;
+	u32 dbrerinfo0;
+	u32 dbureradr0;
+	u32 dbureblane0;
+	u32 dburerid0;
+	u32 dburerinfo0;
+	u32 dbreradr1;
+	u32 dbreblane1;
+	u32 dbrerid1;
+	u32 dbrerinfo1;
+	u32 dbureradr1;
+	u32 dbureblane1;
+	u32 dburerid1;
+	u32 dburerinfo1;
+	u32 dbreradr2;
+	u32 dbreblane2;
+	u32 dbrerid2;
+	u32 dbrerinfo2;
+	u32 dbureradr2;
+	u32 dbureblane2;
+	u32 dburerid2;
+	u32 dburerinfo2;
+	u32 dbreradr3;
+	u32 dbreblane3;
+	u32 dbrerid3;
+	u32 dbrerinfo3;
+	u32 dbureradr3;
+	u32 dbureblane3;
+	u32 dburerid3;
+	u32 dburerinfo3;
+	u32 dummy23[160];	/* 0x680 .. 0x8FC */
+	u32 dbpccr;
+	u32 dbpeier;
+	u32 dbpeisr;
+	u32 dummy24;
+	u32 dbwdpesr0;
+	u32 dbwspesr0;
+	u32 dbpwear0;
+	u32 dbpweid0;
+	u32 dbpweinfo0;
+	u32 dummy25[3];		/* 0x924 .. 0x92C */
+	u32 dbwdpesr1;
+	u32 dbwspesr1;
+	u32 dbpwear1;
+	u32 dbpweid1;
+	u32 dbpweinfo1;
+	u32 dummy26[3];		/* 0x944 .. 0x94C */
+	u32 dbwdpesr2;
+	u32 dbwspesr2;
+	u32 dbpwear2;
+	u32 dbpweid2;
+	u32 dbpweinfo2;
+	u32 dummy27[3];		/* 0x964 .. 0x96C */
+	u32 dbwdpesr3;
+	u32 dbwspesr3;
+	u32 dbpwear3;
+	u32 dbpweid3;
+	u32 dbpweinfo3;
 };
 
 /* GPIO */
@@ -678,6 +1014,10 @@ struct rcar_mxi {
 	u32 dummy2;	/* 0x3C */
 	u32 mxrtcr;
 	u32 mxwtcr;
+	u32 mxaxirtcr;	/* R8a7792 only */
+	u32 mxaxiwtcr;
+	u32 mxs3crtcr;
+	u32 mxs3cwtcr;
 };
 
 struct rcar_mxi_qos {
@@ -699,6 +1039,7 @@ struct rcar_axi_qos {
 	u32 qosthres1;
 	u32 qosthres2;
 	u32 qosqon;
+	u32 qosin;
 };
 
 #endif
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 1c3fe0b..22d97b1 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -10,6 +10,8 @@
 #include <asm/arch/r8a7790.h>
 #elif defined(CONFIG_R8A7791)
 #include <asm/arch/r8a7791.h>
+#elif defined(CONFIG_R8A7792)
+#include <asm/arch/r8a7792.h>
 #elif defined(CONFIG_R8A7793)
 #include <asm/arch/r8a7793.h>
 #elif defined(CONFIG_R8A7794)
diff --git a/arch/arm/mach-rmobile/pfc-r8a7790.h b/arch/arm/mach-rmobile/pfc-r8a7790.h
index a13317b..52f6d9e 100644
--- a/arch/arm/mach-rmobile/pfc-r8a7790.h
+++ b/arch/arm/mach-rmobile/pfc-r8a7790.h
@@ -55,6 +55,54 @@
 	CPU_32_PORT(fn, pfx##_5_, sfx),				\
 	CPU_32_PORT(fn, pfx##_6_, sfx),				\
 	CPU_32_PORT1(fn, pfx##_7_, sfx)
+
+#elif defined(CONFIG_R8A7792)
+/*
+ * GP_0_0_DATA -> GP_11_29_DATA
+ * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
+ *  GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
+ */
+#define CPU_32_PORT0_28(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
+	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx),	\
+	PORT_1(fn, pfx##28, sfx)
+
+#define CPU_32_PORT0_22(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx)
+
+#define CPU_32_PORT0_27(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
+	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
+
+#define CPU_32_PORT0_16(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), 					\
+	PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx),	\
+	PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx),	\
+	PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx),	\
+	PORT_1(fn, pfx##16, sfx)
+
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT0_28(fn, pfx##_0_, sfx),			\
+	CPU_32_PORT0_22(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT(fn, pfx##_2_, sfx),				\
+	CPU_32_PORT0_27(fn, pfx##_3_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_4_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_5_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_6_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_7_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_8_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_9_, sfx),			\
+	CPU_32_PORT(fn, pfx##_10_, sfx),			\
+	CPU_32_PORT2(fn, pfx##_11_, sfx)
+
 #else
 #error "NO support"
 #endif
diff --git a/arch/arm/mach-rmobile/pfc-r8a7792.c b/arch/arm/mach-rmobile/pfc-r8a7792.c
new file mode 100644
index 0000000..be29ee5
--- /dev/null
+++ b/arch/arm/mach-rmobile/pfc-r8a7792.c
@@ -0,0 +1,2302 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7792.c
+ *     This file is r8a7792 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3,
+	FN_IP0_4, FN_IP0_5, FN_IP0_6, FN_IP0_7,
+	FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15,
+	FN_IP0_16, FN_IP0_17, FN_IP0_18, FN_IP0_19,
+	FN_IP0_20, FN_IP0_21, FN_IP0_22, FN_IP0_23,
+	FN_IP1_0, FN_IP1_1, FN_IP1_2, FN_IP1_3,
+	FN_IP1_4,
+
+	/* GPSR1 */
+	FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8,
+	FN_IP1_9, FN_IP1_10, FN_IP1_11, FN_IP1_12,
+	FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
+	FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14, FN_DU1_DB5_C3_DATA15,
+	FN_DU1_DB6_C4, FN_DU1_DB7_C5, FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
+	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
+
+	/* GPSR2 */
+	FN_D0, FN_D1, FN_D2, FN_D3,
+	FN_D4, FN_D5, FN_D6, FN_D7,
+	FN_D8, FN_D9, FN_D10, FN_D11,
+	FN_D12, FN_D13, FN_D14, FN_D15,
+	FN_A0, FN_A1, FN_A2, FN_A3,
+	FN_A4, FN_A5, FN_A6, FN_A7,
+	FN_A8, FN_A9, FN_A10, FN_A11,
+	FN_A12, FN_A13, FN_A14, FN_A15,
+
+	/* GPSR3 */
+	FN_A16, FN_A17, FN_A18, FN_A19,
+	FN_IP1_17, FN_IP1_18, FN_CS1_A26, FN_EX_CS0,
+	FN_EX_CS1, FN_EX_CS2, FN_EX_CS3, FN_EX_CS4,
+	FN_EX_CS5, FN_BS, FN_RD, FN_RD_WR,
+	FN_WE0, FN_WE1, FN_EX_WAIT0, FN_IRQ0,
+	FN_IRQ1, FN_IRQ2, FN_IRQ3, FN_IP1_19,
+	FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0,
+
+	/* GPSR4 */
+	FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC, FN_VI0_VSYNC,
+	FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
+	FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
+	FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
+	FN_VI0_FIELD,
+
+	/* GPSR5 */
+	FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC, FN_VI1_VSYNC,
+	FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
+	FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
+	FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
+	FN_VI1_FIELD,
+
+	/* GPSR6 */
+	FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3,
+	FN_IP2_4, FN_IP2_5, FN_IP2_6, FN_IP2_7,
+	FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11,
+	FN_IP2_12, FN_IP2_13, FN_IP2_14, FN_IP2_15,
+	FN_IP2_16,
+
+	/* GPSR7 */
+	FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3,
+	FN_IP3_4, FN_IP3_5, FN_IP3_6, FN_IP3_7,
+	FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11,
+	FN_IP3_12, FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14,
+	FN_VI3_FIELD,
+
+	/* GPSR8 */
+	FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2,
+	FN_IP4_4, FN_IP4_6_5, FN_IP4_8_7, FN_IP4_10_9,
+	FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15, FN_IP4_18_17,
+	FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
+
+	/* GPSR9 */
+	FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2,
+	FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
+	FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10,
+	FN_IP5_11, FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3,
+	FN_VI5_FIELD,
+
+	/* GPSR10 */
+	FN_IP6_0, FN_IP6_1, FN_HRTS0, FN_IP6_2,
+	FN_IP6_3, FN_IP6_4, FN_IP6_5, FN_HCTS1,
+	FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0,
+	FN_RTS0, FN_TX0, FN_RX0, FN_SCK1,
+	FN_CTS1, FN_RTS1, FN_TX1, FN_RX1,
+	FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
+	FN_IP6_16, FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX,
+	FN_CAN0_RX, FN_CAN_CLK, FN_CAN1_TX, FN_CAN1_RX,
+
+	/* GPSR11 */
+	FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6,
+	FN_IP7_7, FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DAT0,
+	FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3, FN_SD0_CD,
+	FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
+	FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18,
+	FN_IP7_19, FN_IP7_20, FN_ADICLK, FN_ADICS_SAMP,
+	FN_ADIDATA, FN_ADICHS0, FN_ADICHS1, FN_ADICHS2,
+	FN_AVS1, FN_AVS2,
+
+	/* IPSR0 */
+	FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2, FN_DU0_DR3_Y5_DATA3,
+	FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5, FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7,
+	FN_DU0_DG0_DATA8, FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
+	FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14, FN_DU0_DG7_Y3_DATA15,
+	FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0, FN_DU0_DB3_C1,
+	FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4, FN_DU0_DB7_C5,
+
+	/* IPSR1 */
+	FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC, FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP,
+	FN_DU0_CDE, FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
+	FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5, FN_DU1_DG2_C6_DATA6,
+	FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8, FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10,
+	FN_DU1_DG7_Y3_DATA11, FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1,
+	FN_A22, FN_IO2, FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
+
+	/* IPSR2 */
+	FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
+	FN_VI2_HSYNC, FN_AVB_RXD0, FN_VI2_VSYNC, FN_AVB_RXD1,
+	FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
+	FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
+	FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
+	FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
+	FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
+	FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
+	FN_VI2_FIELD, FN_AVB_TXD2,
+
+	/* IPSR3 */
+	FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
+	FN_VI3_HSYNC, FN_AVB_TXD5, FN_VI3_VSYNC, FN_AVB_TXD6,
+	FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
+	FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
+	FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
+	FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
+	FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
+	FN_VI3_D11_Y3,
+
+	/* IPSR4 */
+	FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC, FN_VI0_D13_G5_Y5,
+	FN_VI4_VSYNC, FN_VI0_D14_G6_Y6, FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
+	FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4_0, FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5_0,
+	FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6_0, FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7_0,
+	FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
+	FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
+	FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
+	FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
+
+	/* IPSR5 */
+	FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_1, FN_VI5_HSYNC, FN_VI1_D13_G5_Y5_1,
+	FN_VI5_VSYNC, FN_VI1_D14_G6_Y6_1, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_1,
+	FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
+	FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
+	FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
+	FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
+
+	/* IPSR6 */
+	FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0,
+	FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
+	FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1,
+	FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
+	FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2,
+	FN_DREQ0, FN_RX2, FN_DACK1, FN_SCK3,
+	FN_TX3, FN_DREQ1, FN_RX3,
+
+	/* IPSR7 */
+	FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
+	FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
+	FN_SSI_SCK3, FN_TPU0TO0, FN_SSI_WS3, FN_TPU0TO1,
+	FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
+	FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
+
+	FN_SEL_VI1_0, FN_SEL_VI1_1,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+	DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
+	DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
+	DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
+	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, DU1_DISP_MARK, DU1_CDE_MARK,
+
+	D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
+	D6_MARK, D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK,
+	D12_MARK, D13_MARK, D14_MARK, D15_MARK, A0_MARK, A1_MARK,
+	A2_MARK, A3_MARK, A4_MARK, A5_MARK, A6_MARK, A7_MARK,
+	A8_MARK, A9_MARK, A10_MARK, A11_MARK, A12_MARK, A13_MARK,
+	A14_MARK, A15_MARK,
+
+	A16_MARK, A17_MARK, A18_MARK, A19_MARK,
+	CS1_A26_MARK, EX_CS0_MARK, EX_CS1_MARK, EX_CS2_MARK,
+	EX_CS3_MARK, EX_CS4_MARK, EX_CS5_MARK, BS_MARK,
+	RD_MARK, RD_WR_MARK, WE0_MARK, WE1_MARK, EX_WAIT0_MARK,
+	IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_MARK,
+
+	VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_MARK, VI0_VSYNC_MARK,
+	VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
+	VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
+	VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
+	VI0_FIELD_MARK,
+
+	VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_MARK,
+	VI1_VSYNC_MARK, VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
+	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK,
+	VI1_D5_B5_C5_MARK, VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
+	VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK,
+	VI1_D11_G3_Y3_MARK, VI1_FIELD_MARK,
+
+	VI3_D10_Y2_MARK, VI3_FIELD_MARK,
+
+	VI4_CLK_MARK,
+
+	VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, VI5_FIELD_MARK,
+
+	HRTS0_MARK, HCTS1_MARK, SCK0_MARK, CTS0_MARK, RTS0_MARK, TX0_MARK,
+	RX0_MARK, SCK1_MARK, CTS1_MARK, RTS1_MARK, TX1_MARK, RX1_MARK,
+	SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
+	CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
+
+	SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK,
+	SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+	SD0_CD_MARK, SD0_WP_MARK, ADICLK_MARK,
+	ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
+	ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
+
+	DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
+	DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
+	DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
+	DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
+	DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
+	DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
+	DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK,
+	DU0_DB5_C3_MARK, DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
+
+	DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
+	DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
+	DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
+	DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
+	DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
+	A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
+	A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
+
+	VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
+	VI2_HSYNC_MARK, AVB_RXD0_MARK, VI2_VSYNC_MARK, AVB_RXD1_MARK,
+	VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_RXD3_MARK,
+	VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
+	VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
+	VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
+	VI2_D8_Y0_MARK, AVB_TXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
+	VI2_D10_Y2_MARK, AVB_TXD0_MARK, VI2_D11_Y3_MARK, AVB_TXD1_MARK,
+	VI2_FIELD_MARK, AVB_TXD2_MARK,
+
+	VI3_CLK_MARK, AVB_TX_CLK_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
+	VI3_HSYNC_MARK, AVB_TXD5_MARK, VI3_VSYNC_MARK, AVB_TXD6_MARK,
+	VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
+	VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
+	VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
+	VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
+	VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
+	VI3_D11_Y3_MARK,
+
+	VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_MARK, VI0_D13_G5_Y5_MARK,
+	VI4_VSYNC_MARK, VI0_D14_G6_Y6_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK,
+	VI4_D1_C1_MARK, VI0_D16_R0_MARK, VI1_D12_G4_Y4_0_MARK,
+	VI4_D2_C2_MARK, VI0_D17_R1_MARK, VI1_D13_G5_Y5_0_MARK,
+	VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_0_MARK,
+	VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_0_MARK,
+	VI4_D5_C5_MARK, VI0_D20_R4_MARK, VI2_D12_Y4_MARK,
+	VI4_D6_C6_MARK, VI0_D21_R5_MARK, VI2_D13_Y5_MARK,
+	VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
+	VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK,
+	VI4_D9_Y1_MARK, VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK,
+	VI4_D11_Y3_MARK, VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
+
+	VI5_CLKENB_MARK, VI1_D12_G4_Y4_1_MARK, VI5_HSYNC_MARK, VI1_D13_G5_Y5_1_MARK,
+	VI5_VSYNC_MARK, VI1_D14_G6_Y6_1_MARK, VI5_D0_C0_MARK, VI1_D15_G7_Y7_1_MARK,
+	VI5_D1_C1_MARK, VI1_D16_R0_MARK, VI5_D2_C2_MARK, VI1_D17_R1_MARK,
+	VI5_D3_C3_MARK, VI1_D18_R2_MARK, VI5_D4_C4_MARK, VI1_D19_R3_MARK,
+	VI5_D5_C5_MARK, VI1_D20_R4_MARK, VI5_D6_C6_MARK, VI1_D21_R5_MARK,
+	VI5_D7_C7_MARK, VI1_D22_R6_MARK, VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
+
+	MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_MARK,
+	MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
+	MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_MARK,
+	MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
+	DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK,
+	DREQ0_MARK, RX2_MARK, DACK1_MARK, SCK3_MARK,
+	TX3_MARK, DREQ1_MARK, RX3_MARK,
+
+	PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK,
+	PWM1_MARK, TCLK2_MARK, FSO_CFE_1_MARK,
+	PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK,
+	PWM3_MARK, PWM4_MARK, SSI_SCK3_MARK, TPU0TO0_MARK,
+	SSI_WS3_MARK, TPU0TO1_MARK, SSI_SDATA3_MARK, TPU0TO2_MARK,
+	SSI_SCK4_MARK, TPU0TO3_MARK, SSI_WS4_MARK,
+	SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK,
+	AUDIO_CLKA_MARK, AUDIO_CLKB_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_DATA(DU1_DB2_C0_DATA12_MARK, FN_DU1_DB2_C0_DATA12),
+	PINMUX_DATA(DU1_DB3_C1_DATA13_MARK, FN_DU1_DB3_C1_DATA13),
+	PINMUX_DATA(DU1_DB4_C2_DATA14_MARK, FN_DU1_DB4_C2_DATA14),
+	PINMUX_DATA(DU1_DB5_C3_DATA15_MARK, FN_DU1_DB5_C3_DATA15),
+	PINMUX_DATA(DU1_DB6_C4_MARK, FN_DU1_DB6_C4),
+	PINMUX_DATA(DU1_DB7_C5_MARK, FN_DU1_DB7_C5),
+	PINMUX_DATA(DU1_EXHSYNC_DU1_HSYNC_MARK, FN_DU1_EXHSYNC_DU1_HSYNC),
+	PINMUX_DATA(DU1_EXVSYNC_DU1_VSYNC_MARK, FN_DU1_EXVSYNC_DU1_VSYNC),
+	PINMUX_DATA(DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE),
+	PINMUX_DATA(DU1_DISP_MARK, FN_DU1_DISP),
+	PINMUX_DATA(DU1_CDE_MARK, FN_DU1_CDE),
+
+	PINMUX_DATA(D0_MARK, FN_D0),
+	PINMUX_DATA(D1_MARK, FN_D1),
+	PINMUX_DATA(D2_MARK, FN_D2),
+	PINMUX_DATA(D3_MARK, FN_D3),
+	PINMUX_DATA(D4_MARK, FN_D4),
+	PINMUX_DATA(D5_MARK, FN_D5),
+	PINMUX_DATA(D6_MARK, FN_D6),
+	PINMUX_DATA(D7_MARK, FN_D7),
+	PINMUX_DATA(D8_MARK, FN_D8),
+	PINMUX_DATA(D9_MARK, FN_D9),
+	PINMUX_DATA(D10_MARK, FN_D10),
+	PINMUX_DATA(D11_MARK, FN_D11),
+	PINMUX_DATA(D12_MARK, FN_D12),
+	PINMUX_DATA(D13_MARK, FN_D13),
+	PINMUX_DATA(D14_MARK, FN_D14),
+	PINMUX_DATA(D15_MARK, FN_D15),
+	PINMUX_DATA(A0_MARK, FN_A0),
+	PINMUX_DATA(A1_MARK, FN_A1),
+	PINMUX_DATA(A2_MARK, FN_A2),
+	PINMUX_DATA(A3_MARK, FN_A3),
+	PINMUX_DATA(A4_MARK, FN_A4),
+	PINMUX_DATA(A5_MARK, FN_A5),
+	PINMUX_DATA(A6_MARK, FN_A6),
+	PINMUX_DATA(A7_MARK, FN_A7),
+	PINMUX_DATA(A8_MARK, FN_A8),
+	PINMUX_DATA(A9_MARK, FN_A9),
+	PINMUX_DATA(A10_MARK, FN_A10),
+	PINMUX_DATA(A11_MARK, FN_A11),
+	PINMUX_DATA(A12_MARK, FN_A12),
+	PINMUX_DATA(A13_MARK, FN_A13),
+	PINMUX_DATA(A14_MARK, FN_A14),
+	PINMUX_DATA(A15_MARK, FN_A15),
+
+	PINMUX_DATA(A16_MARK, FN_A16),
+	PINMUX_DATA(A17_MARK, FN_A17),
+	PINMUX_DATA(A18_MARK, FN_A18),
+	PINMUX_DATA(A19_MARK, FN_A19),
+	PINMUX_DATA(CS1_A26_MARK, FN_CS1_A26),
+	PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
+	PINMUX_DATA(EX_CS1_MARK, FN_EX_CS1),
+	PINMUX_DATA(EX_CS2_MARK, FN_EX_CS2),
+	PINMUX_DATA(EX_CS3_MARK, FN_EX_CS3),
+	PINMUX_DATA(EX_CS4_MARK, FN_EX_CS4),
+	PINMUX_DATA(EX_CS5_MARK, FN_EX_CS5),
+	PINMUX_DATA(BS_MARK, FN_BS),
+	PINMUX_DATA(RD_MARK, FN_RD),
+	PINMUX_DATA(RD_WR_MARK, FN_RD_WR),
+	PINMUX_DATA(WE0_MARK, FN_WE0),
+	PINMUX_DATA(WE1_MARK, FN_WE1),
+	PINMUX_DATA(EX_WAIT0_MARK, FN_EX_WAIT0),
+	PINMUX_DATA(IRQ0_MARK, FN_IRQ0),
+	PINMUX_DATA(IRQ1_MARK, FN_IRQ1),
+	PINMUX_DATA(IRQ2_MARK, FN_IRQ2),
+	PINMUX_DATA(IRQ3_MARK, FN_IRQ3),
+	PINMUX_DATA(CS0_MARK, FN_CS0),
+
+	PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
+	PINMUX_DATA(VI0_CLKENB_MARK, FN_VI0_CLKENB),
+	PINMUX_DATA(VI0_HSYNC_MARK, FN_VI0_HSYNC),
+	PINMUX_DATA(VI0_VSYNC_MARK, FN_VI0_VSYNC),
+	PINMUX_DATA(VI0_D0_B0_C0_MARK, FN_VI0_D0_B0_C0),
+	PINMUX_DATA(VI0_D1_B1_C1_MARK, FN_VI0_D1_B1_C1),
+	PINMUX_DATA(VI0_D2_B2_C2_MARK, FN_VI0_D2_B2_C2),
+	PINMUX_DATA(VI0_D3_B3_C3_MARK, FN_VI0_D3_B3_C3),
+	PINMUX_DATA(VI0_D4_B4_C4_MARK, FN_VI0_D4_B4_C4),
+	PINMUX_DATA(VI0_D5_B5_C5_MARK, FN_VI0_D5_B5_C5),
+	PINMUX_DATA(VI0_D6_B6_C6_MARK, FN_VI0_D6_B6_C6),
+	PINMUX_DATA(VI0_D7_B7_C7_MARK, FN_VI0_D7_B7_C7),
+	PINMUX_DATA(VI0_D8_G0_Y0_MARK, FN_VI0_D8_G0_Y0),
+	PINMUX_DATA(VI0_D9_G1_Y1_MARK, FN_VI0_D9_G1_Y1),
+	PINMUX_DATA(VI0_D10_G2_Y2_MARK, FN_VI0_D10_G2_Y2),
+	PINMUX_DATA(VI0_D11_G3_Y3_MARK, FN_VI0_D11_G3_Y3),
+	PINMUX_DATA(VI0_FIELD_MARK, FN_VI0_FIELD),
+
+	PINMUX_DATA(VI1_CLK_MARK, FN_VI1_CLK),
+	PINMUX_DATA(VI1_CLKENB_MARK, FN_VI1_CLKENB),
+	PINMUX_DATA(VI1_HSYNC_MARK, FN_VI1_HSYNC),
+	PINMUX_DATA(VI1_VSYNC_MARK, FN_VI1_VSYNC),
+	PINMUX_DATA(VI1_D0_B0_C0_MARK, FN_VI1_D0_B0_C0),
+	PINMUX_DATA(VI1_D1_B1_C1_MARK, FN_VI1_D1_B1_C1),
+	PINMUX_DATA(VI1_D2_B2_C2_MARK, FN_VI1_D2_B2_C2),
+	PINMUX_DATA(VI1_D3_B3_C3_MARK, FN_VI1_D3_B3_C3),
+	PINMUX_DATA(VI1_D4_B4_C4_MARK, FN_VI1_D4_B4_C4),
+	PINMUX_DATA(VI1_D5_B5_C5_MARK, FN_VI1_D5_B5_C5),
+	PINMUX_DATA(VI1_D6_B6_C6_MARK, FN_VI1_D6_B6_C6),
+	PINMUX_DATA(VI1_D7_B7_C7_MARK, FN_VI1_D7_B7_C7),
+	PINMUX_DATA(VI1_D8_G0_Y0_MARK, FN_VI1_D8_G0_Y0),
+	PINMUX_DATA(VI1_D9_G1_Y1_MARK, FN_VI1_D9_G1_Y1),
+	PINMUX_DATA(VI1_D10_G2_Y2_MARK, FN_VI1_D10_G2_Y2),
+	PINMUX_DATA(VI1_D11_G3_Y3_MARK, FN_VI1_D11_G3_Y3),
+	PINMUX_DATA(VI1_FIELD_MARK, FN_VI1_FIELD),
+
+	PINMUX_DATA(VI3_D10_Y2_MARK, FN_VI3_D10_Y2),
+	PINMUX_DATA(VI3_FIELD_MARK, FN_VI3_FIELD),
+
+	PINMUX_DATA(VI4_CLK_MARK, FN_VI4_CLK),
+
+	PINMUX_DATA(VI5_CLK_MARK, FN_VI5_CLK),
+	PINMUX_DATA(VI5_D9_Y1_MARK, FN_VI5_D9_Y1),
+	PINMUX_DATA(VI5_D10_Y2_MARK, FN_VI5_D10_Y2),
+	PINMUX_DATA(VI5_D11_Y3_MARK, FN_VI5_D11_Y3),
+	PINMUX_DATA(VI5_FIELD_MARK, FN_VI5_FIELD),
+
+	PINMUX_DATA(HRTS0_MARK, FN_HRTS0),
+	PINMUX_DATA(HCTS1_MARK, FN_HCTS1),
+	PINMUX_DATA(SCK0_MARK, FN_SCK0),
+	PINMUX_DATA(CTS0_MARK, FN_CTS0),
+	PINMUX_DATA(RTS0_MARK, FN_RTS0),
+	PINMUX_DATA(TX0_MARK, FN_TX0),
+	PINMUX_DATA(RX0_MARK, FN_RX0),
+	PINMUX_DATA(SCK1_MARK, FN_SCK1),
+	PINMUX_DATA(CTS1_MARK, FN_CTS1),
+	PINMUX_DATA(RTS1_MARK, FN_RTS1),
+	PINMUX_DATA(TX1_MARK, FN_TX1),
+	PINMUX_DATA(RX1_MARK, FN_RX1),
+	PINMUX_DATA(SCIF_CLK_MARK, FN_SCIF_CLK),
+	PINMUX_DATA(CAN0_TX_MARK, FN_CAN0_TX),
+	PINMUX_DATA(CAN0_RX_MARK, FN_CAN0_RX),
+	PINMUX_DATA(CAN_CLK_MARK, FN_CAN_CLK),
+	PINMUX_DATA(CAN1_TX_MARK, FN_CAN1_TX),
+	PINMUX_DATA(CAN1_RX_MARK, FN_CAN1_RX),
+
+	PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
+	PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
+	PINMUX_DATA(SD0_DAT0_MARK, FN_SD0_DAT0),
+	PINMUX_DATA(SD0_DAT1_MARK, FN_SD0_DAT1),
+	PINMUX_DATA(SD0_DAT2_MARK, FN_SD0_DAT2),
+	PINMUX_DATA(SD0_DAT3_MARK, FN_SD0_DAT3),
+	PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
+	PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
+	PINMUX_DATA(ADICLK_MARK, FN_ADICLK),
+	PINMUX_DATA(ADICS_SAMP_MARK, FN_ADICS_SAMP),
+	PINMUX_DATA(ADIDATA_MARK, FN_ADIDATA),
+	PINMUX_DATA(ADICHS0_MARK, FN_ADICHS0),
+	PINMUX_DATA(ADICHS1_MARK, FN_ADICHS1),
+	PINMUX_DATA(ADICHS2_MARK, FN_ADICHS2),
+	PINMUX_DATA(AVS1_MARK, FN_AVS1),
+	PINMUX_DATA(AVS2_MARK, FN_AVS2),
+
+	PINMUX_IPSR_DATA(IP0_0, DU0_DR0_DATA0),
+	PINMUX_IPSR_DATA(IP0_1, DU0_DR1_DATA1),
+	PINMUX_IPSR_DATA(IP0_2, DU0_DR2_Y4_DATA2),
+	PINMUX_IPSR_DATA(IP0_3, DU0_DR3_Y5_DATA3),
+	PINMUX_IPSR_DATA(IP0_4, DU0_DR4_Y6_DATA4),
+	PINMUX_IPSR_DATA(IP0_5, DU0_DR5_Y7_DATA5),
+	PINMUX_IPSR_DATA(IP0_6, DU0_DR6_Y8_DATA6),
+	PINMUX_IPSR_DATA(IP0_7, DU0_DR7_Y9_DATA7),
+	PINMUX_IPSR_DATA(IP0_8, DU0_DG0_DATA8),
+	PINMUX_IPSR_DATA(IP0_9, DU0_DG1_DATA9),
+	PINMUX_IPSR_DATA(IP0_10, DU0_DG2_C6_DATA10),
+	PINMUX_IPSR_DATA(IP0_11, DU0_DG3_C7_DATA11),
+	PINMUX_IPSR_DATA(IP0_12, DU0_DG4_Y0_DATA12),
+	PINMUX_IPSR_DATA(IP0_13, DU0_DG5_Y1_DATA13),
+	PINMUX_IPSR_DATA(IP0_14, DU0_DG6_Y2_DATA14),
+	PINMUX_IPSR_DATA(IP0_15, DU0_DG7_Y3_DATA15),
+	PINMUX_IPSR_DATA(IP0_16, DU0_DB0),
+	PINMUX_IPSR_DATA(IP0_17, DU0_DB1),
+	PINMUX_IPSR_DATA(IP0_18, DU0_DB2_C0),
+	PINMUX_IPSR_DATA(IP0_19, DU0_DB3_C1),
+	PINMUX_IPSR_DATA(IP0_20, DU0_DB4_C2),
+	PINMUX_IPSR_DATA(IP0_21, DU0_DB5_C3),
+	PINMUX_IPSR_DATA(IP0_22, DU0_DB6_C4),
+	PINMUX_IPSR_DATA(IP0_23, DU0_DB7_C5),
+
+	PINMUX_IPSR_DATA(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
+	PINMUX_IPSR_DATA(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
+	PINMUX_IPSR_DATA(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP1_3, DU0_DISP),
+	PINMUX_IPSR_DATA(IP1_4, DU0_CDE),
+	PINMUX_IPSR_DATA(IP1_5, DU1_DR2_Y4_DATA0),
+	PINMUX_IPSR_DATA(IP1_6, DU1_DR3_Y5_DATA1),
+	PINMUX_IPSR_DATA(IP1_7, DU1_DR4_Y6_DATA2),
+	PINMUX_IPSR_DATA(IP1_8, DU1_DR5_Y7_DATA3),
+	PINMUX_IPSR_DATA(IP1_9, DU1_DR6_DATA4),
+	PINMUX_IPSR_DATA(IP1_10, DU1_DR7_DATA5),
+	PINMUX_IPSR_DATA(IP1_11, DU1_DG2_C6_DATA6),
+	PINMUX_IPSR_DATA(IP1_12, DU1_DG3_C7_DATA7),
+	PINMUX_IPSR_DATA(IP1_13, DU1_DG4_Y0_DATA8),
+	PINMUX_IPSR_DATA(IP1_14, DU1_DG5_Y1_DATA9),
+	PINMUX_IPSR_DATA(IP1_15, DU1_DG6_Y2_DATA10),
+	PINMUX_IPSR_DATA(IP1_16, DU1_DG7_Y3_DATA11),
+	PINMUX_IPSR_DATA(IP1_17, A20),
+	PINMUX_IPSR_DATA(IP1_17, MOSI_IO0),
+	PINMUX_IPSR_DATA(IP1_18, A21),
+	PINMUX_IPSR_DATA(IP1_18, MISO_IO1),
+	PINMUX_IPSR_DATA(IP1_19, A22),
+	PINMUX_IPSR_DATA(IP1_19, IO2),
+	PINMUX_IPSR_DATA(IP1_20, A23),
+	PINMUX_IPSR_DATA(IP1_20, IO3),
+	PINMUX_IPSR_DATA(IP1_21, A24),
+	PINMUX_IPSR_DATA(IP1_21, SPCLK),
+	PINMUX_IPSR_DATA(IP1_22, A25),
+	PINMUX_IPSR_DATA(IP1_22, SSL),
+
+	PINMUX_IPSR_DATA(IP2_0, VI2_CLK),
+	PINMUX_IPSR_DATA(IP2_0, AVB_RX_CLK),
+	PINMUX_IPSR_DATA(IP2_1, VI2_CLKENB),
+	PINMUX_IPSR_DATA(IP2_1, AVB_RX_DV),
+	PINMUX_IPSR_DATA(IP2_2, VI2_HSYNC),
+	PINMUX_IPSR_DATA(IP2_2, AVB_RXD0),
+	PINMUX_IPSR_DATA(IP2_3, VI2_VSYNC),
+	PINMUX_IPSR_DATA(IP2_3, AVB_RXD1),
+	PINMUX_IPSR_DATA(IP2_4, VI2_D0_C0),
+	PINMUX_IPSR_DATA(IP2_4, AVB_RXD2),
+	PINMUX_IPSR_DATA(IP2_5, VI2_D1_C1),
+	PINMUX_IPSR_DATA(IP2_5, AVB_RXD3),
+	PINMUX_IPSR_DATA(IP2_6, VI2_D2_C2),
+	PINMUX_IPSR_DATA(IP2_6, AVB_RXD4),
+	PINMUX_IPSR_DATA(IP2_7, VI2_D3_C3),
+	PINMUX_IPSR_DATA(IP2_7, AVB_RXD5),
+	PINMUX_IPSR_DATA(IP2_8, VI2_D4_C4),
+	PINMUX_IPSR_DATA(IP2_8, AVB_RXD6),
+	PINMUX_IPSR_DATA(IP2_9, VI2_D5_C5),
+	PINMUX_IPSR_DATA(IP2_9, AVB_RXD7),
+	PINMUX_IPSR_DATA(IP2_10, VI2_D6_C6),
+	PINMUX_IPSR_DATA(IP2_10, AVB_RX_ER),
+	PINMUX_IPSR_DATA(IP2_11, VI2_D7_C7),
+	PINMUX_IPSR_DATA(IP2_11, AVB_COL),
+	PINMUX_IPSR_DATA(IP2_12, VI2_D8_Y0),
+	PINMUX_IPSR_DATA(IP2_12, AVB_TXD3),
+	PINMUX_IPSR_DATA(IP2_13, VI2_D9_Y1),
+	PINMUX_IPSR_DATA(IP2_13, AVB_TX_EN),
+	PINMUX_IPSR_DATA(IP2_14, VI2_D10_Y2),
+	PINMUX_IPSR_DATA(IP2_14, AVB_TXD0),
+	PINMUX_IPSR_DATA(IP2_15, VI2_D11_Y3),
+	PINMUX_IPSR_DATA(IP2_15, AVB_TXD1),
+	PINMUX_IPSR_DATA(IP2_16, VI2_FIELD),
+	PINMUX_IPSR_DATA(IP2_16, AVB_TXD2),
+
+	PINMUX_IPSR_DATA(IP3_0, VI3_CLK),
+	PINMUX_IPSR_DATA(IP3_0, AVB_TX_CLK),
+	PINMUX_IPSR_DATA(IP3_1, VI3_CLKENB),
+	PINMUX_IPSR_DATA(IP3_1, AVB_TXD4),
+	PINMUX_IPSR_DATA(IP3_2, VI3_HSYNC),
+	PINMUX_IPSR_DATA(IP3_2, AVB_TXD5),
+	PINMUX_IPSR_DATA(IP3_3, VI3_VSYNC),
+	PINMUX_IPSR_DATA(IP3_3, AVB_TXD6),
+	PINMUX_IPSR_DATA(IP3_4, VI3_D0_C0),
+	PINMUX_IPSR_DATA(IP3_4, AVB_TXD7),
+	PINMUX_IPSR_DATA(IP3_5, VI3_D1_C1),
+	PINMUX_IPSR_DATA(IP3_5, AVB_TX_ER),
+	PINMUX_IPSR_DATA(IP3_6, VI3_D2_C2),
+	PINMUX_IPSR_DATA(IP3_6, AVB_GTX_CLK),
+	PINMUX_IPSR_DATA(IP3_7, VI3_D3_C3),
+	PINMUX_IPSR_DATA(IP3_7, AVB_MDC),
+	PINMUX_IPSR_DATA(IP3_8, VI3_D4_C4),
+	PINMUX_IPSR_DATA(IP3_8, AVB_MDIO),
+	PINMUX_IPSR_DATA(IP3_9, VI3_D5_C5),
+	PINMUX_IPSR_DATA(IP3_9, AVB_LINK),
+	PINMUX_IPSR_DATA(IP3_10, VI3_D6_C6),
+	PINMUX_IPSR_DATA(IP3_10, AVB_MAGIC),
+	PINMUX_IPSR_DATA(IP3_11, VI3_D7_C7),
+	PINMUX_IPSR_DATA(IP3_11, AVB_PHY_INT),
+	PINMUX_IPSR_DATA(IP3_12, VI3_D8_Y0),
+	PINMUX_IPSR_DATA(IP3_12, AVB_CRS),
+	PINMUX_IPSR_DATA(IP3_13, VI3_D9_Y1),
+	PINMUX_IPSR_DATA(IP3_13, AVB_GTXREFCLK),
+	PINMUX_IPSR_DATA(IP3_14, VI3_D11_Y3),
+
+	PINMUX_IPSR_DATA(IP4_0, VI4_CLKENB),
+	PINMUX_IPSR_DATA(IP4_0, VI0_D12_G4_Y4),
+	PINMUX_IPSR_DATA(IP4_1, VI4_HSYNC),
+	PINMUX_IPSR_DATA(IP4_1, VI0_D13_G5_Y5),
+	PINMUX_IPSR_DATA(IP4_3_2, VI4_VSYNC),
+	PINMUX_IPSR_DATA(IP4_3_2, VI0_D14_G6_Y6),
+	PINMUX_IPSR_DATA(IP4_4, VI4_D0_C0),
+	PINMUX_IPSR_DATA(IP4_4, VI0_D15_G7_Y7),
+	PINMUX_IPSR_DATA(IP4_6_5, VI4_D1_C1),
+	PINMUX_IPSR_DATA(IP4_6_5, VI0_D16_R0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_6_5, VI1_D12_G4_Y4_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_8_7, VI4_D2_C2),
+	PINMUX_IPSR_DATA(IP4_8_7, VI0_D17_R1),
+	PINMUX_IPSR_MODSEL_DATA(IP4_8_7, VI1_D13_G5_Y5_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_10_9, VI4_D3_C3),
+	PINMUX_IPSR_DATA(IP4_10_9, VI0_D18_R2),
+	PINMUX_IPSR_MODSEL_DATA(IP4_10_9, VI1_D14_G6_Y6_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_12_11, VI4_D4_C4),
+	PINMUX_IPSR_DATA(IP4_12_11, VI0_D19_R3),
+	PINMUX_IPSR_MODSEL_DATA(IP4_12_11, VI1_D15_G7_Y7_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_14_13, VI4_D5_C5),
+	PINMUX_IPSR_DATA(IP4_14_13, VI0_D20_R4),
+	PINMUX_IPSR_DATA(IP4_14_13, VI2_D12_Y4),
+	PINMUX_IPSR_DATA(IP4_16_15, VI4_D6_C6),
+	PINMUX_IPSR_DATA(IP4_16_15, VI0_D21_R5),
+	PINMUX_IPSR_DATA(IP4_16_15, VI2_D13_Y5),
+	PINMUX_IPSR_DATA(IP4_18_17, VI4_D7_C7),
+	PINMUX_IPSR_DATA(IP4_18_17, VI0_D22_R6),
+	PINMUX_IPSR_DATA(IP4_18_17, VI2_D14_Y6),
+	PINMUX_IPSR_DATA(IP4_20_19, VI4_D8_Y0),
+	PINMUX_IPSR_DATA(IP4_20_19, VI0_D23_R7),
+	PINMUX_IPSR_DATA(IP4_20_19, VI2_D15_Y7),
+	PINMUX_IPSR_DATA(IP4_21, VI4_D9_Y1),
+	PINMUX_IPSR_DATA(IP4_21, VI3_D12_Y4),
+	PINMUX_IPSR_DATA(IP4_22, VI4_D10_Y2),
+	PINMUX_IPSR_DATA(IP4_22, VI3_D13_Y5),
+	PINMUX_IPSR_DATA(IP4_23, VI4_D11_Y3),
+	PINMUX_IPSR_DATA(IP4_23, VI3_D14_Y6),
+	PINMUX_IPSR_DATA(IP4_24, VI4_FIELD),
+	PINMUX_IPSR_DATA(IP4_24, VI3_D15_Y7),
+
+	PINMUX_IPSR_DATA(IP5_0, VI5_CLKENB),
+	PINMUX_IPSR_MODSEL_DATA(IP5_0, VI1_D12_G4_Y4_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_1, VI5_HSYNC),
+	PINMUX_IPSR_MODSEL_DATA(IP5_1, VI1_D13_G5_Y5_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_2, VI5_VSYNC),
+	PINMUX_IPSR_MODSEL_DATA(IP5_2, VI1_D14_G6_Y6_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_3, VI5_D0_C0),
+	PINMUX_IPSR_MODSEL_DATA(IP5_3, VI1_D15_G7_Y7_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_4, VI5_D1_C1),
+	PINMUX_IPSR_DATA(IP5_4, VI1_D16_R0),
+	PINMUX_IPSR_DATA(IP5_5, VI5_D2_C2),
+	PINMUX_IPSR_DATA(IP5_5, VI1_D17_R1),
+	PINMUX_IPSR_DATA(IP5_6, VI5_D3_C3),
+	PINMUX_IPSR_DATA(IP5_6, VI1_D18_R2),
+	PINMUX_IPSR_DATA(IP5_7, VI5_D4_C4),
+	PINMUX_IPSR_DATA(IP5_7, VI1_D19_R3),
+	PINMUX_IPSR_DATA(IP5_8, VI5_D5_C5),
+	PINMUX_IPSR_DATA(IP5_8, VI1_D20_R4),
+	PINMUX_IPSR_DATA(IP5_9, VI5_D6_C6),
+	PINMUX_IPSR_DATA(IP5_9, VI1_D21_R5),
+	PINMUX_IPSR_DATA(IP5_10, VI5_D7_C7),
+	PINMUX_IPSR_DATA(IP5_10, VI1_D22_R6),
+	PINMUX_IPSR_DATA(IP5_11, VI5_D8_Y0),
+	PINMUX_IPSR_DATA(IP5_11, VI1_D23_R7),
+
+	PINMUX_IPSR_DATA(IP6_0, MSIOF0_SCK),
+	PINMUX_IPSR_DATA(IP6_0, HSCK0),
+	PINMUX_IPSR_DATA(IP6_1, MSIOF0_SYNC),
+	PINMUX_IPSR_DATA(IP6_1, HCTS0),
+	PINMUX_IPSR_DATA(IP6_2, MSIOF0_TXD),
+	PINMUX_IPSR_DATA(IP6_2, HTX0),
+	PINMUX_IPSR_DATA(IP6_3, MSIOF0_RXD),
+	PINMUX_IPSR_DATA(IP6_3, HRX0),
+	PINMUX_IPSR_DATA(IP6_4, MSIOF1_SCK),
+	PINMUX_IPSR_DATA(IP6_4, HSCK1),
+	PINMUX_IPSR_DATA(IP6_5, MSIOF1_SYNC),
+	PINMUX_IPSR_DATA(IP6_5, HRTS1),
+	PINMUX_IPSR_DATA(IP6_6, MSIOF1_TXD),
+	PINMUX_IPSR_DATA(IP6_6, HTX1),
+	PINMUX_IPSR_DATA(IP6_7, MSIOF1_RXD),
+	PINMUX_IPSR_DATA(IP6_7, HRX1),
+	PINMUX_IPSR_DATA(IP6_9_8, DRACK0),
+	PINMUX_IPSR_DATA(IP6_9_8, SCK2),
+	PINMUX_IPSR_DATA(IP6_11_10, DACK0),
+	PINMUX_IPSR_DATA(IP6_11_10, TX2),
+	PINMUX_IPSR_DATA(IP6_13_12, DREQ0),
+	PINMUX_IPSR_DATA(IP6_13_12, RX2),
+	PINMUX_IPSR_DATA(IP6_15_14, DACK1),
+	PINMUX_IPSR_DATA(IP6_15_14, SCK3),
+	PINMUX_IPSR_DATA(IP6_16, TX3),
+	PINMUX_IPSR_DATA(IP6_18_17, DREQ1),
+	PINMUX_IPSR_DATA(IP6_18_17, RX3),
+
+	PINMUX_IPSR_DATA(IP7_1_0, PWM0),
+	PINMUX_IPSR_DATA(IP7_1_0, TCLK1),
+	PINMUX_IPSR_DATA(IP7_1_0, FSO_CFE_0),
+	PINMUX_IPSR_DATA(IP7_3_2, PWM1),
+	PINMUX_IPSR_DATA(IP7_3_2, TCLK2),
+	PINMUX_IPSR_DATA(IP7_3_2, FSO_CFE_1),
+	PINMUX_IPSR_DATA(IP7_5_4, PWM2),
+	PINMUX_IPSR_DATA(IP7_5_4, TCLK3),
+	PINMUX_IPSR_DATA(IP7_5_4, FSO_TOE),
+	PINMUX_IPSR_DATA(IP7_6, PWM3),
+	PINMUX_IPSR_DATA(IP7_7, PWM4),
+	PINMUX_IPSR_DATA(IP7_9_8, SSI_SCK3),
+	PINMUX_IPSR_DATA(IP7_9_8, TPU0TO0),
+	PINMUX_IPSR_DATA(IP7_11_10, SSI_WS3),
+	PINMUX_IPSR_DATA(IP7_11_10, TPU0TO1),
+	PINMUX_IPSR_DATA(IP7_13_12, SSI_SDATA3),
+	PINMUX_IPSR_DATA(IP7_13_12, TPU0TO2),
+	PINMUX_IPSR_DATA(IP7_15_14, SSI_SCK4),
+	PINMUX_IPSR_DATA(IP7_15_14, TPU0TO3),
+	PINMUX_IPSR_DATA(IP7_16, SSI_WS4),
+	PINMUX_IPSR_DATA(IP7_17, SSI_SDATA4),
+	PINMUX_IPSR_DATA(IP7_18, AUDIO_CLKOUT),
+	PINMUX_IPSR_DATA(IP7_19, AUDIO_CLKA),
+	PINMUX_IPSR_DATA(IP7_20, AUDIO_CLKB),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	GPIO_FN(DU1_DB2_C0_DATA12), GPIO_FN(DU1_DB3_C1_DATA13),
+	GPIO_FN(DU1_DB4_C2_DATA14), GPIO_FN(DU1_DB5_C3_DATA15),
+	GPIO_FN(DU1_DB6_C4), GPIO_FN(DU1_DB7_C5),
+	GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC),
+	GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(DU1_DISP), GPIO_FN(DU1_CDE),
+
+	GPIO_FN(D0), GPIO_FN(D1), GPIO_FN(D2), GPIO_FN(D3),
+	GPIO_FN(D4), GPIO_FN(D5), GPIO_FN(D6), GPIO_FN(D7),
+	GPIO_FN(D8), GPIO_FN(D9), GPIO_FN(D10), GPIO_FN(D11),
+	GPIO_FN(D12), GPIO_FN(D13), GPIO_FN(D14), GPIO_FN(D15),
+	GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
+	GPIO_FN(A4), GPIO_FN(A5), GPIO_FN(A6), GPIO_FN(A7),
+	GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), GPIO_FN(A11),
+	GPIO_FN(A12), GPIO_FN(A13), GPIO_FN(A14), GPIO_FN(A15),
+
+	GPIO_FN(A16), GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19),
+	GPIO_FN(CS1_A26), GPIO_FN(EX_CS0), GPIO_FN(EX_CS1), GPIO_FN(EX_CS2),
+	GPIO_FN(EX_CS3), GPIO_FN(EX_CS4), GPIO_FN(EX_CS5), GPIO_FN(BS),
+	GPIO_FN(RD), GPIO_FN(RD_WR), GPIO_FN(WE0), GPIO_FN(WE1),
+	GPIO_FN(EX_WAIT0), GPIO_FN(IRQ0), GPIO_FN(IRQ1), GPIO_FN(IRQ2),
+	GPIO_FN(IRQ3), GPIO_FN(CS0),
+
+	GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB), GPIO_FN(VI0_HSYNC),
+	GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_D0_B0_C0), GPIO_FN(VI0_D1_B1_C1),
+	GPIO_FN(VI0_D2_B2_C2), GPIO_FN(VI0_D3_B3_C3), GPIO_FN(VI0_D4_B4_C4),
+	GPIO_FN(VI0_D5_B5_C5), GPIO_FN(VI0_D6_B6_C6), GPIO_FN(VI0_D7_B7_C7),
+	GPIO_FN(VI0_D8_G0_Y0), GPIO_FN(VI0_D9_G1_Y1), GPIO_FN(VI0_D10_G2_Y2),
+	GPIO_FN(VI0_D11_G3_Y3), GPIO_FN(VI0_FIELD),
+
+	GPIO_FN(VI1_CLK), GPIO_FN(VI1_CLKENB), GPIO_FN(VI1_HSYNC),
+	GPIO_FN(VI1_VSYNC), GPIO_FN(VI1_D0_B0_C0), GPIO_FN(VI1_D1_B1_C1),
+	GPIO_FN(VI1_D2_B2_C2), GPIO_FN(VI1_D3_B3_C3), GPIO_FN(VI1_D4_B4_C4),
+	GPIO_FN(VI1_D5_B5_C5), GPIO_FN(VI1_D6_B6_C6), GPIO_FN(VI1_D7_B7_C7),
+	GPIO_FN(VI1_D8_G0_Y0), GPIO_FN(VI1_D9_G1_Y1), GPIO_FN(VI1_D10_G2_Y2),
+	GPIO_FN(VI1_D11_G3_Y3), GPIO_FN(VI1_FIELD),
+
+	GPIO_FN(VI3_D10_Y2), GPIO_FN(VI3_FIELD),
+
+	GPIO_FN(VI4_CLK),
+
+	GPIO_FN(VI5_CLK), GPIO_FN(VI5_D9_Y1), GPIO_FN(VI5_D10_Y2),
+	GPIO_FN(VI5_D11_Y3), GPIO_FN(VI5_FIELD),
+
+	GPIO_FN(HRTS0), GPIO_FN(HCTS1), GPIO_FN(SCK0), GPIO_FN(CTS0),
+	GPIO_FN(RTS0), GPIO_FN(TX0), GPIO_FN(RX0), GPIO_FN(SCK1),
+	GPIO_FN(CTS1), GPIO_FN(RTS1), GPIO_FN(TX1), GPIO_FN(RX1),
+	GPIO_FN(SCIF_CLK), GPIO_FN(CAN0_TX), GPIO_FN(CAN0_RX), GPIO_FN(CAN_CLK),
+	GPIO_FN(CAN1_TX), GPIO_FN(CAN1_RX),
+
+	GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD), GPIO_FN(SD0_DAT0),
+	GPIO_FN(SD0_DAT1), GPIO_FN(SD0_DAT2), GPIO_FN(SD0_DAT3),
+	GPIO_FN(SD0_CD), GPIO_FN(SD0_WP), GPIO_FN(ADICLK),
+	GPIO_FN(ADICS_SAMP), GPIO_FN(ADIDATA), GPIO_FN(ADICHS0),
+	GPIO_FN(ADICHS1), GPIO_FN(ADICHS2), GPIO_FN(AVS1),
+	GPIO_FN(AVS2),
+
+	GPIO_FN(DU0_DR0_DATA0), GPIO_FN(DU0_DR1_DATA1),
+	GPIO_FN(DU0_DR2_Y4_DATA2), GPIO_FN(DU0_DR3_Y5_DATA3),
+	GPIO_FN(DU0_DR4_Y6_DATA4), GPIO_FN(DU0_DR5_Y7_DATA5),
+	GPIO_FN(DU0_DR6_Y8_DATA6), GPIO_FN(DU0_DR7_Y9_DATA7),
+	GPIO_FN(DU0_DG0_DATA8), GPIO_FN(DU0_DG1_DATA9),
+	GPIO_FN(DU0_DG2_C6_DATA10), GPIO_FN(DU0_DG3_C7_DATA11),
+	GPIO_FN(DU0_DG4_Y0_DATA12), GPIO_FN(DU0_DG5_Y1_DATA13),
+	GPIO_FN(DU0_DG6_Y2_DATA14), GPIO_FN(DU0_DG7_Y3_DATA15),
+	GPIO_FN(DU0_DB0), GPIO_FN(DU0_DB1),
+	GPIO_FN(DU0_DB2_C0), GPIO_FN(DU0_DB3_C1), GPIO_FN(DU0_DB4_C2),
+	GPIO_FN(DU0_DB5_C3), GPIO_FN(DU0_DB6_C4), GPIO_FN(DU0_DB7_C5),
+
+	GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(DU0_EXVSYNC_DU0_VSYNC),
+	GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(DU0_DISP),
+	GPIO_FN(DU0_CDE), GPIO_FN(DU1_DR2_Y4_DATA0), GPIO_FN(DU1_DR3_Y5_DATA1),
+	GPIO_FN(DU1_DR4_Y6_DATA2), GPIO_FN(DU1_DR5_Y7_DATA3),
+	GPIO_FN(DU1_DR6_DATA4), GPIO_FN(DU1_DR7_DATA5),
+	GPIO_FN(DU1_DG2_C6_DATA6), GPIO_FN(DU1_DG3_C7_DATA7),
+	GPIO_FN(DU1_DG4_Y0_DATA8), GPIO_FN(DU1_DG5_Y1_DATA9),
+	GPIO_FN(DU1_DG6_Y2_DATA10), GPIO_FN(DU1_DG7_Y3_DATA11),
+	GPIO_FN(A20), GPIO_FN(MOSI_IO0), GPIO_FN(A21), GPIO_FN(MISO_IO1),
+	GPIO_FN(A22), GPIO_FN(IO2), GPIO_FN(A23), GPIO_FN(IO3),
+	GPIO_FN(A24), GPIO_FN(SPCLK), GPIO_FN(A25), GPIO_FN(SSL),
+
+	GPIO_FN(VI2_CLK), GPIO_FN(AVB_RX_CLK), GPIO_FN(VI2_CLKENB),
+	GPIO_FN(AVB_RX_DV), GPIO_FN(VI2_HSYNC), GPIO_FN(AVB_RXD0),
+	GPIO_FN(VI2_VSYNC), GPIO_FN(AVB_RXD1), GPIO_FN(VI2_D0_C0),
+	GPIO_FN(AVB_RXD2), GPIO_FN(VI2_D1_C1), GPIO_FN(AVB_RXD3),
+	GPIO_FN(VI2_D2_C2), GPIO_FN(AVB_RXD4), GPIO_FN(VI2_D3_C3),
+	GPIO_FN(AVB_RXD5), GPIO_FN(VI2_D4_C4), GPIO_FN(AVB_RXD6),
+	GPIO_FN(VI2_D5_C5), GPIO_FN(AVB_RXD7), GPIO_FN(VI2_D6_C6),
+	GPIO_FN(AVB_RX_ER), GPIO_FN(VI2_D7_C7), GPIO_FN(AVB_COL),
+	GPIO_FN(VI2_D8_Y0), GPIO_FN(AVB_TXD3), GPIO_FN(VI2_D9_Y1),
+	GPIO_FN(AVB_TX_EN), GPIO_FN(VI2_D10_Y2), GPIO_FN(AVB_TXD0),
+	GPIO_FN(VI2_D11_Y3), GPIO_FN(AVB_TXD1), GPIO_FN(VI2_FIELD),
+	GPIO_FN(AVB_TXD2),
+
+	GPIO_FN(VI3_CLK), GPIO_FN(AVB_TX_CLK), GPIO_FN(VI3_CLKENB),
+	GPIO_FN(AVB_TXD4), GPIO_FN(VI3_HSYNC), GPIO_FN(AVB_TXD5),
+	GPIO_FN(VI3_VSYNC), GPIO_FN(AVB_TXD6), GPIO_FN(VI3_D0_C0),
+	GPIO_FN(AVB_TXD7), GPIO_FN(VI3_D1_C1), GPIO_FN(AVB_TX_ER),
+	GPIO_FN(VI3_D2_C2), GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI3_D3_C3),
+	GPIO_FN(AVB_MDC), GPIO_FN(VI3_D4_C4), GPIO_FN(AVB_MDIO),
+	GPIO_FN(VI3_D5_C5), GPIO_FN(AVB_LINK), GPIO_FN(VI3_D6_C6),
+	GPIO_FN(AVB_MAGIC), GPIO_FN(VI3_D7_C7), GPIO_FN(AVB_PHY_INT),
+	GPIO_FN(VI3_D8_Y0), GPIO_FN(AVB_CRS), GPIO_FN(VI3_D9_Y1),
+	GPIO_FN(AVB_GTXREFCLK), GPIO_FN(VI3_D11_Y3),
+
+	GPIO_FN(VI4_CLKENB), GPIO_FN(VI0_D12_G4_Y4), GPIO_FN(VI4_HSYNC),
+	GPIO_FN(VI0_D13_G5_Y5), GPIO_FN(VI4_VSYNC), GPIO_FN(VI0_D14_G6_Y6),
+	GPIO_FN(VI4_D0_C0), GPIO_FN(VI0_D15_G7_Y7), GPIO_FN(VI4_D1_C1),
+	GPIO_FN(VI0_D16_R0), GPIO_FN(VI1_D12_G4_Y4_0), GPIO_FN(VI4_D2_C2),
+	GPIO_FN(VI0_D17_R1), GPIO_FN(VI1_D13_G5_Y5_0), GPIO_FN(VI4_D3_C3),
+	GPIO_FN(VI0_D18_R2), GPIO_FN(VI1_D14_G6_Y6_0), GPIO_FN(VI4_D4_C4),
+	GPIO_FN(VI0_D19_R3), GPIO_FN(VI1_D15_G7_Y7_0), GPIO_FN(VI4_D5_C5),
+	GPIO_FN(VI0_D20_R4), GPIO_FN(VI2_D12_Y4), GPIO_FN(VI4_D6_C6),
+	GPIO_FN(VI0_D21_R5), GPIO_FN(VI2_D13_Y5), GPIO_FN(VI4_D7_C7),
+	GPIO_FN(VI0_D22_R6), GPIO_FN(VI2_D14_Y6), GPIO_FN(VI4_D8_Y0),
+	GPIO_FN(VI0_D23_R7), GPIO_FN(VI2_D15_Y7), GPIO_FN(VI4_D9_Y1),
+	GPIO_FN(VI3_D12_Y4), GPIO_FN(VI4_D10_Y2), GPIO_FN(VI3_D13_Y5),
+	GPIO_FN(VI4_D11_Y3), GPIO_FN(VI3_D14_Y6), GPIO_FN(VI4_FIELD),
+	GPIO_FN(VI3_D15_Y7),
+
+	GPIO_FN(VI5_CLKENB), GPIO_FN(VI1_D12_G4_Y4_1), GPIO_FN(VI5_HSYNC),
+	GPIO_FN(VI1_D13_G5_Y5_1), GPIO_FN(VI5_VSYNC), GPIO_FN(VI1_D14_G6_Y6_1),
+	GPIO_FN(VI5_D0_C0), GPIO_FN(VI1_D15_G7_Y7_1), GPIO_FN(VI5_D1_C1),
+	GPIO_FN(VI1_D16_R0), GPIO_FN(VI5_D2_C2), GPIO_FN(VI1_D17_R1),
+	GPIO_FN(VI5_D3_C3), GPIO_FN(VI1_D18_R2), GPIO_FN(VI5_D4_C4),
+	GPIO_FN(VI1_D19_R3), GPIO_FN(VI5_D5_C5), GPIO_FN(VI1_D20_R4),
+	GPIO_FN(VI5_D6_C6), GPIO_FN(VI1_D21_R5), GPIO_FN(VI5_D7_C7),
+	GPIO_FN(VI1_D22_R6), GPIO_FN(VI5_D8_Y0), GPIO_FN(VI1_D23_R7),
+
+	GPIO_FN(MSIOF0_SCK), GPIO_FN(HSCK0), GPIO_FN(MSIOF0_SYNC),
+	GPIO_FN(HCTS0), GPIO_FN(MSIOF0_TXD), GPIO_FN(HTX0),
+	GPIO_FN(MSIOF0_RXD), GPIO_FN(HRX0), GPIO_FN(MSIOF1_SCK),
+	GPIO_FN(HSCK1), GPIO_FN(MSIOF1_SYNC), GPIO_FN(HRTS1),
+	GPIO_FN(MSIOF1_TXD), GPIO_FN(HTX1), GPIO_FN(MSIOF1_RXD),
+	GPIO_FN(HRX1), GPIO_FN(DRACK0), GPIO_FN(SCK2),
+	GPIO_FN(DACK0), GPIO_FN(TX2), GPIO_FN(DREQ0),
+	GPIO_FN(RX2), GPIO_FN(DACK1), GPIO_FN(SCK3),
+	GPIO_FN(TX3), GPIO_FN(DREQ1), GPIO_FN(RX3),
+
+	GPIO_FN(PWM0), GPIO_FN(TCLK1), GPIO_FN(FSO_CFE_0),
+	GPIO_FN(PWM1), GPIO_FN(TCLK2), GPIO_FN(FSO_CFE_1),
+	GPIO_FN(PWM2), GPIO_FN(TCLK3), GPIO_FN(FSO_TOE),
+	GPIO_FN(PWM3), GPIO_FN(PWM4),
+	GPIO_FN(SSI_SCK3), GPIO_FN(TPU0TO0),
+	GPIO_FN(SSI_WS3), GPIO_FN(TPU0TO1),
+	GPIO_FN(SSI_SDATA3), GPIO_FN(TPU0TO2),
+	GPIO_FN(SSI_SCK4), GPIO_FN(TPU0TO3),
+	GPIO_FN(SSI_WS4), GPIO_FN(SSI_SDATA4),
+	GPIO_FN(AUDIO_CLKOUT), GPIO_FN(AUDIO_CLKA), GPIO_FN(AUDIO_CLKB),
+
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_0_28_FN, FN_IP1_4,
+		GP_0_27_FN, FN_IP1_3,
+		GP_0_26_FN, FN_IP1_2,
+		GP_0_25_FN, FN_IP1_1,
+		GP_0_24_FN, FN_IP1_0,
+		GP_0_23_FN, FN_IP0_23,
+		GP_0_22_FN, FN_IP0_22,
+		GP_0_21_FN, FN_IP0_21,
+		GP_0_20_FN, FN_IP0_20,
+		GP_0_19_FN, FN_IP0_19,
+		GP_0_18_FN, FN_IP0_18,
+		GP_0_17_FN, FN_IP0_17,
+		GP_0_16_FN, FN_IP0_16,
+		GP_0_15_FN, FN_IP0_15,
+		GP_0_14_FN, FN_IP0_14,
+		GP_0_13_FN, FN_IP0_13,
+		GP_0_12_FN, FN_IP0_12,
+		GP_0_11_FN, FN_IP0_11,
+		GP_0_10_FN, FN_IP0_10,
+		GP_0_9_FN, FN_IP0_9,
+		GP_0_8_FN, FN_IP0_8,
+		GP_0_7_FN, FN_IP0_7,
+		GP_0_6_FN, FN_IP0_6,
+		GP_0_5_FN, FN_IP0_5,
+		GP_0_4_FN, FN_IP0_4,
+		GP_0_3_FN, FN_IP0_3,
+		GP_0_2_FN, FN_IP0_2,
+		GP_0_1_FN, FN_IP0_1,
+		GP_0_0_FN, FN_IP0_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_22_FN, FN_DU1_CDE,
+		GP_1_21_FN, FN_DU1_DISP,
+		GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+		GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
+		GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
+		GP_1_17_FN, FN_DU1_DB7_C5,
+		GP_1_16_FN, FN_DU1_DB6_C4,
+		GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
+		GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
+		GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
+		GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
+		GP_1_11_FN, FN_IP1_16,
+		GP_1_10_FN, FN_IP1_15,
+		GP_1_9_FN, FN_IP1_14,
+		GP_1_8_FN, FN_IP1_13,
+		GP_1_7_FN, FN_IP1_12,
+		GP_1_6_FN, FN_IP1_11,
+		GP_1_5_FN, FN_IP1_10,
+		GP_1_4_FN, FN_IP1_9,
+		GP_1_3_FN, FN_IP1_8,
+		GP_1_2_FN, FN_IP1_7,
+		GP_1_1_FN, FN_IP1_6,
+		GP_1_0_FN, FN_IP1_5, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		GP_2_31_FN, FN_A15,
+		GP_2_30_FN, FN_A14,
+		GP_2_29_FN, FN_A13,
+		GP_2_28_FN, FN_A12,
+		GP_2_27_FN, FN_A11,
+		GP_2_26_FN, FN_A10,
+		GP_2_25_FN, FN_A9,
+		GP_2_24_FN, FN_A8,
+		GP_2_23_FN, FN_A7,
+		GP_2_22_FN, FN_A6,
+		GP_2_21_FN, FN_A5,
+		GP_2_20_FN, FN_A4,
+		GP_2_19_FN, FN_A3,
+		GP_2_18_FN, FN_A2,
+		GP_2_17_FN, FN_A1,
+		GP_2_16_FN, FN_A0,
+		GP_2_15_FN, FN_D15,
+		GP_2_14_FN, FN_D14,
+		GP_2_13_FN, FN_D13,
+		GP_2_12_FN, FN_D12,
+		GP_2_11_FN, FN_D11,
+		GP_2_10_FN, FN_D10,
+		GP_2_9_FN, FN_D9,
+		GP_2_8_FN, FN_D8,
+		GP_2_7_FN, FN_D7,
+		GP_2_6_FN, FN_D6,
+		GP_2_5_FN, FN_D5,
+		GP_2_4_FN, FN_D4,
+		GP_2_3_FN, FN_D3,
+		GP_2_2_FN, FN_D2,
+		GP_2_1_FN, FN_D1,
+		GP_2_0_FN, FN_D0 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_3_27_FN, FN_CS0,
+		GP_3_26_FN, FN_IP1_22,
+		GP_3_25_FN, FN_IP1_21,
+		GP_3_24_FN, FN_IP1_20,
+		GP_3_23_FN, FN_IP1_19,
+		GP_3_22_FN, FN_IRQ3,
+		GP_3_21_FN, FN_IRQ2,
+		GP_3_20_FN, FN_IRQ1,
+		GP_3_19_FN, FN_IRQ0,
+		GP_3_18_FN, FN_EX_WAIT0,
+		GP_3_17_FN, FN_WE1,
+		GP_3_16_FN, FN_WE0,
+		GP_3_15_FN, FN_RD_WR,
+		GP_3_14_FN, FN_RD,
+		GP_3_13_FN, FN_BS,
+		GP_3_12_FN, FN_EX_CS5,
+		GP_3_11_FN, FN_EX_CS4,
+		GP_3_10_FN, FN_EX_CS3,
+		GP_3_9_FN, FN_EX_CS2,
+		GP_3_8_FN, FN_EX_CS1,
+		GP_3_7_FN, FN_EX_CS0,
+		GP_3_6_FN, FN_CS1_A26,
+		GP_3_5_FN, FN_IP1_18,
+		GP_3_4_FN, FN_IP1_17,
+		GP_3_3_FN, FN_A19,
+		GP_3_2_FN, FN_A18,
+		GP_3_1_FN, FN_A17,
+		GP_3_0_FN, FN_A16 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_16_FN, FN_VI0_FIELD,
+		GP_4_15_FN, FN_VI0_D11_G3_Y3,
+		GP_4_14_FN, FN_VI0_D10_G2_Y2,
+		GP_4_13_FN, FN_VI0_D9_G1_Y1,
+		GP_4_12_FN, FN_VI0_D8_G0_Y0,
+		GP_4_11_FN, FN_VI0_D7_B7_C7,
+		GP_4_10_FN, FN_VI0_D6_B6_C6,
+		GP_4_9_FN, FN_VI0_D5_B5_C5,
+		GP_4_8_FN, FN_VI0_D4_B4_C4,
+		GP_4_7_FN, FN_VI0_D3_B3_C3,
+		GP_4_6_FN, FN_VI0_D2_B2_C2,
+		GP_4_5_FN, FN_VI0_D1_B1_C1,
+		GP_4_4_FN, FN_VI0_D0_B0_C0,
+		GP_4_3_FN, FN_VI0_VSYNC,
+		GP_4_2_FN, FN_VI0_HSYNC,
+		GP_4_1_FN, FN_VI0_CLKENB,
+		GP_4_0_FN, FN_VI0_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_16_FN, FN_VI1_FIELD,
+		GP_5_15_FN, FN_VI1_D11_G3_Y3,
+		GP_5_14_FN, FN_VI1_D10_G2_Y2,
+		GP_5_13_FN, FN_VI1_D9_G1_Y1,
+		GP_5_12_FN, FN_VI1_D8_G0_Y0,
+		GP_5_11_FN, FN_VI1_D7_B7_C7,
+		GP_5_10_FN, FN_VI1_D6_B6_C6,
+		GP_5_9_FN, FN_VI1_D5_B5_C5,
+		GP_5_8_FN, FN_VI1_D4_B4_C4,
+		GP_5_7_FN, FN_VI1_D3_B3_C3,
+		GP_5_6_FN, FN_VI1_D2_B2_C2,
+		GP_5_5_FN, FN_VI1_D1_B1_C1,
+		GP_5_4_FN, FN_VI1_D0_B0_C0,
+		GP_5_3_FN, FN_VI1_VSYNC,
+		GP_5_2_FN, FN_VI1_HSYNC,
+		GP_5_1_FN, FN_VI1_CLKENB,
+		GP_5_0_FN, FN_VI1_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_16_FN, FN_IP2_16,
+		GP_6_15_FN, FN_IP2_15,
+		GP_6_14_FN, FN_IP2_14,
+		GP_6_13_FN, FN_IP2_13,
+		GP_6_12_FN, FN_IP2_12,
+		GP_6_11_FN, FN_IP2_11,
+		GP_6_10_FN, FN_IP2_10,
+		GP_6_9_FN, FN_IP2_9,
+		GP_6_8_FN, FN_IP2_8,
+		GP_6_7_FN, FN_IP2_7,
+		GP_6_6_FN, FN_IP2_6,
+		GP_6_5_FN, FN_IP2_5,
+		GP_6_4_FN, FN_IP2_4,
+		GP_6_3_FN, FN_IP2_3,
+		GP_6_2_FN, FN_IP2_2,
+		GP_6_1_FN, FN_IP2_1,
+		GP_6_0_FN, FN_IP2_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_16_FN, FN_VI3_FIELD,
+		GP_7_15_FN, FN_IP3_14,
+		GP_7_14_FN, FN_VI3_D10_Y2,
+		GP_7_13_FN, FN_IP3_13,
+		GP_7_12_FN, FN_IP3_12,
+		GP_7_11_FN, FN_IP3_11,
+		GP_7_10_FN, FN_IP3_10,
+		GP_7_9_FN, FN_IP3_9,
+		GP_7_8_FN, FN_IP3_8,
+		GP_7_7_FN, FN_IP3_7,
+		GP_7_6_FN, FN_IP3_6,
+		GP_7_5_FN, FN_IP3_5,
+		GP_7_4_FN, FN_IP3_4,
+		GP_7_3_FN, FN_IP3_3,
+		GP_7_2_FN, FN_IP3_2,
+		GP_7_1_FN, FN_IP3_1,
+		GP_7_0_FN, FN_IP3_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_8_16_FN, FN_IP4_24,
+		GP_8_15_FN, FN_IP4_23,
+		GP_8_14_FN, FN_IP4_22,
+		GP_8_13_FN, FN_IP4_21,
+		GP_8_12_FN, FN_IP4_20_19,
+		GP_8_11_FN, FN_IP4_18_17,
+		GP_8_10_FN, FN_IP4_16_15,
+		GP_8_9_FN, FN_IP4_14_13,
+		GP_8_8_FN, FN_IP4_12_11,
+		GP_8_7_FN, FN_IP4_10_9,
+		GP_8_6_FN, FN_IP4_8_7,
+		GP_8_5_FN, FN_IP4_6_5,
+		GP_8_4_FN, FN_IP4_4,
+		GP_8_3_FN, FN_IP4_3_2,
+		GP_8_2_FN, FN_IP4_1,
+		GP_8_1_FN, FN_IP4_0,
+		GP_8_0_FN, FN_VI4_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_9_16_FN, FN_VI5_FIELD,
+		GP_9_15_FN, FN_VI5_D11_Y3,
+		GP_9_14_FN, FN_VI5_D10_Y2,
+		GP_9_13_FN, FN_VI5_D9_Y1,
+		GP_9_12_FN, FN_IP5_11,
+		GP_9_11_FN, FN_IP5_10,
+		GP_9_10_FN, FN_IP5_9,
+		GP_9_9_FN, FN_IP5_8,
+		GP_9_8_FN, FN_IP5_7,
+		GP_9_7_FN, FN_IP5_6,
+		GP_9_6_FN, FN_IP5_5,
+		GP_9_5_FN, FN_IP5_4,
+		GP_9_4_FN, FN_IP5_3,
+		GP_9_3_FN, FN_IP5_2,
+		GP_9_2_FN, FN_IP5_1,
+		GP_9_1_FN, FN_IP5_0,
+		GP_9_0_FN, FN_VI5_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
+		GP_10_31_FN, FN_CAN1_RX,
+		GP_10_30_FN, FN_CAN1_TX,
+		GP_10_29_FN, FN_CAN_CLK,
+		GP_10_28_FN, FN_CAN0_RX,
+		GP_10_27_FN, FN_CAN0_TX,
+		GP_10_26_FN, FN_SCIF_CLK,
+		GP_10_25_FN, FN_IP6_18_17,
+		GP_10_24_FN, FN_IP6_16,
+		GP_10_23_FN, FN_IP6_15_14,
+		GP_10_22_FN, FN_IP6_13_12,
+		GP_10_21_FN, FN_IP6_11_10,
+		GP_10_20_FN, FN_IP6_9_8,
+		GP_10_19_FN, FN_RX1,
+		GP_10_18_FN, FN_TX1,
+		GP_10_17_FN, FN_RTS1,
+		GP_10_16_FN, FN_CTS1,
+		GP_10_15_FN, FN_SCK1,
+		GP_10_14_FN, FN_RX0,
+		GP_10_13_FN, FN_TX0,
+		GP_10_12_FN, FN_RTS0,
+		GP_10_11_FN, FN_CTS0,
+		GP_10_10_FN, FN_SCK0,
+		GP_10_9_FN, FN_IP6_7,
+		GP_10_8_FN, FN_IP6_6,
+		GP_10_7_FN, FN_HCTS1,
+		GP_10_6_FN, FN_IP6_5,
+		GP_10_5_FN, FN_IP6_4,
+		GP_10_4_FN, FN_IP6_3,
+		GP_10_3_FN, FN_IP6_2,
+		GP_10_2_FN, FN_HRTS0,
+		GP_10_1_FN, FN_IP6_1,
+		GP_10_0_FN, FN_IP6_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_11_29_FN, FN_AVS2,
+		GP_11_28_FN, FN_AVS1,
+		GP_11_27_FN, FN_ADICHS2,
+		GP_11_26_FN, FN_ADICHS1,
+		GP_11_25_FN, FN_ADICHS0,
+		GP_11_24_FN, FN_ADIDATA,
+		GP_11_23_FN, FN_ADICS_SAMP,
+		GP_11_22_FN, FN_ADICLK,
+		GP_11_21_FN, FN_IP7_20,
+		GP_11_20_FN, FN_IP7_19,
+		GP_11_19_FN, FN_IP7_18,
+		GP_11_18_FN, FN_IP7_17,
+		GP_11_17_FN, FN_IP7_16,
+		GP_11_16_FN, FN_IP7_15_14,
+		GP_11_15_FN, FN_IP7_13_12,
+		GP_11_14_FN, FN_IP7_11_10,
+		GP_11_13_FN, FN_IP7_9_8,
+		GP_11_12_FN, FN_SD0_WP,
+		GP_11_11_FN, FN_SD0_CD,
+		GP_11_10_FN, FN_SD0_DAT3,
+		GP_11_9_FN, FN_SD0_DAT2,
+		GP_11_8_FN, FN_SD0_DAT1,
+		GP_11_7_FN, FN_SD0_DAT0,
+		GP_11_6_FN, FN_SD0_CMD,
+		GP_11_5_FN, FN_SD0_CLK,
+		GP_11_4_FN, FN_IP7_7,
+		GP_11_3_FN, FN_IP7_6,
+		GP_11_2_FN, FN_IP7_5_4,
+		GP_11_1_FN, FN_IP7_3_2,
+		GP_11_0_FN, FN_IP7_1_0 }
+	},
+	/* IPSR0 */
+	{ PINMUX_CFG_REG("IPSR0", 0xE6060040, 32 ,1) {
+		/* IP0_31 [1] */
+		0, 0,
+		/* IP0_30 [1] */
+		0, 0,
+		/* IP0_29 [1] */
+		0, 0,
+		/* IP0_28 [1] */
+		0, 0,
+		/* IP0_27 [1] */
+		0, 0,
+		/* IP0_26 [1] */
+		0, 0,
+		/* IP0_25 [1] */
+		0, 0,
+		/* IP0_24 [1] */
+		0, 0,
+		/* IP0_23 [1] */
+		FN_DU0_DB7_C5, 0,
+		/* IP0_22 [1] */
+		FN_DU0_DB6_C4, 0,
+		/* IP0_21 [1] */
+		FN_DU0_DB5_C3, 0,
+		/* IP0_20 [1] */
+		FN_DU0_DB4_C2, 0,
+		/* IP0_19 [1] */
+		FN_DU0_DB3_C1, 0,
+		/* IP0_18 [1] */
+		FN_DU0_DB2_C0, 0,
+		/* IP0_17 [1] */
+		FN_DU0_DB1, 0,
+		/* IP0_16 [1] */
+		FN_DU0_DB0, 0,
+		/* IP0_15 [1] */
+		FN_DU0_DG7_Y3_DATA15, 0,
+		/* IP0_14 [1] */
+		FN_DU0_DG6_Y2_DATA14, 0,
+		/* IP0_13 [1] */
+		FN_DU0_DG5_Y1_DATA13, 0,
+		/* IP0_12 [1] */
+		FN_DU0_DG4_Y0_DATA12, 0,
+		/* IP0_11 [1] */
+		FN_DU0_DG3_C7_DATA11, 0,
+		/* IP0_10 [1] */
+		FN_DU0_DG2_C6_DATA10, 0,
+		/* IP0_9 [1] */
+		FN_DU0_DG1_DATA9, 0,
+		/* IP0_8 [1] */
+		FN_DU0_DG0_DATA8, 0,
+		/* IP0_7 [1] */
+		FN_DU0_DR7_Y9_DATA7, 0,
+		/* IP0_6 [1] */
+		FN_DU0_DR6_Y8_DATA6, 0,
+		/* IP0_5 [1] */
+		FN_DU0_DR5_Y7_DATA5, 0,
+		/* IP0_4 [1] */
+		FN_DU0_DR4_Y6_DATA4, 0,
+		/* IP0_3 [1] */
+		FN_DU0_DR3_Y5_DATA3, 0,
+		/* IP0_2 [1] */
+		FN_DU0_DR2_Y4_DATA2, 0,
+		/* IP0_1 [1] */
+		FN_DU0_DR1_DATA1, 0,
+		/* IP0_0 [1] */
+		FN_DU0_DR0_DATA0, 0, }
+	},
+	/* IPSR1 */
+	{ PINMUX_CFG_REG("IPSR1", 0xE6060044, 32, 1) {
+		/* IP1_31 [1] */
+		0, 0,
+		/* IP1_30 [1] */
+		0, 0,
+		/* IP1_29 [1] */
+		0, 0,
+		/* IP1_28 [1] */
+		0, 0,
+		/* IP1_27 [1] */
+		0, 0,
+		/* IP1_26 [1] */
+		0, 0,
+		/* IP1_25 [1] */
+		0, 0,
+		/* IP1_24 [1] */
+		0, 0,
+		/* IP1_23 [1] */
+		0, 0,
+		/* IP1_22 [1] */
+		FN_A25, FN_SSL,
+		/* IP1_21 [1] */
+		FN_A24, FN_SPCLK,
+		/* IP1_20 [1] */
+		FN_A23, FN_IO3,
+		/* IP1_19 [1] */
+		FN_A22, FN_IO2,
+		/* IP1_18 [1] */
+		FN_A21, FN_MISO_IO1,
+		/* IP1_17 [1] */
+		FN_A20, FN_MOSI_IO0,
+		/* IP1_16 [1] */
+		FN_DU1_DG7_Y3_DATA11, 0,
+		/* IP1_15 [1] */
+		FN_DU1_DG6_Y2_DATA10, 0,
+		/* IP1_14 [1] */
+		FN_DU1_DG5_Y1_DATA9, 0,
+		/* IP1_13 [1] */
+		FN_DU1_DG4_Y0_DATA8, 0,
+		/* IP1_12 [1] */
+		FN_DU1_DG3_C7_DATA7, 0,
+		/* IP1_11 [1] */
+		FN_DU1_DG2_C6_DATA6, 0,
+		/* IP1_10 [1] */
+		FN_DU1_DR7_DATA5, 0,
+		/* IP1_9 [1] */
+		FN_DU1_DR6_DATA4, 0,
+		/* IP1_8 [1] */
+		FN_DU1_DR5_Y7_DATA3, 0,
+		/* IP1_7 [1] */
+		FN_DU1_DR4_Y6_DATA2, 0,
+		/* IP1_6 [1] */
+		FN_DU1_DR3_Y5_DATA1, 0,
+		/* IP1_5 [1] */
+		FN_DU1_DR2_Y4_DATA0, 0,
+		/* IP1_4 [1] */
+		FN_DU0_CDE, 0,
+		/* IP1_3 [1] */
+		FN_DU0_DISP, 0,
+		/* IP1_2 [1] */
+		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
+		/* IP1_1 [1] */
+		FN_DU0_EXVSYNC_DU0_VSYNC, 0,
+		/* IP1_0 [1] */
+		FN_DU0_EXHSYNC_DU0_HSYNC, 0, }
+	},
+	/* IPSR2 */
+	{ PINMUX_CFG_REG("IPSR2", 0xE6060048, 32, 1) {
+		/* IP2_31 [1] */
+		0, 0,
+		/* IP2_30 [1] */
+		0, 0,
+		/* IP2_29 [1] */
+		0, 0,
+		/* IP2_28 [1] */
+		0, 0,
+		/* IP2_27 [1] */
+		0, 0,
+		/* IP2_26 [1] */
+		0, 0,
+		/* IP2_25 [1] */
+		0, 0,
+		/* IP2_24 [1] */
+		0, 0,
+		/* IP2_23 [1] */
+		0, 0,
+		/* IP2_22 [1] */
+		0, 0,
+		/* IP2_21 [1] */
+		0, 0,
+		/* IP2_20 [1] */
+		0, 0,
+		/* IP2_19 [1] */
+		0, 0,
+		/* IP2_18 [1] */
+		0, 0,
+		/* IP2_17 [1] */
+		0, 0,
+		/* IP2_16 [1] */
+		FN_VI2_FIELD, FN_AVB_TXD2,
+		/* IP2_15 [1] */
+		FN_VI2_D11_Y3, FN_AVB_TXD1,
+		/* IP2_14 [1] */
+		FN_VI2_D10_Y2, FN_AVB_TXD0,
+		/* IP2_13 [1] */
+		FN_VI2_D9_Y1, FN_AVB_TX_EN,
+		/* IP2_12 [1] */
+		FN_VI2_D8_Y0, FN_AVB_TXD3,
+		/* IP2_11 [1] */
+		FN_VI2_D7_C7, FN_AVB_COL,
+		/* IP2_10 [1] */
+		FN_VI2_D6_C6, FN_AVB_RX_ER,
+		/* IP2_9 [1] */
+		FN_VI2_D5_C5, FN_AVB_RXD7,
+		/* IP2_8 [1] */
+		FN_VI2_D4_C4, FN_AVB_RXD6,
+		/* IP2_7 [1] */
+		FN_VI2_D3_C3, FN_AVB_RXD5,
+		/* IP2_6 [1] */
+		FN_VI2_D2_C2, FN_AVB_RXD4,
+		/* IP2_5 [1] */
+		FN_VI2_D1_C1, FN_AVB_RXD3,
+		/* IP2_4 [1] */
+		FN_VI2_D0_C0, FN_AVB_RXD2,
+		/* IP2_3 [1] */
+		FN_VI2_VSYNC, FN_AVB_RXD1,
+		/* IP2_2 [1] */
+		FN_VI2_HSYNC, FN_AVB_RXD0,
+		/* IP2_1 [1] */
+		FN_VI2_CLKENB, FN_AVB_RX_DV,
+		/* IP2_0 [1] */
+		FN_VI2_CLK, FN_AVB_RX_CLK, }
+	},
+	/* IPSR3 */
+	{ PINMUX_CFG_REG("IPSR3", 0xE606004C, 32, 1) {
+		/* IP3_31 [1] */
+		0, 0,
+		/* IP3_30 [1] */
+		0, 0,
+		/* IP3_29 [1] */
+		0, 0,
+		/* IP3_28 [1] */
+		0, 0,
+		/* IP3_27 [1] */
+		0, 0,
+		/* IP3_26 [1] */
+		0, 0,
+		/* IP3_25 [1] */
+		0, 0,
+		/* IP3_24 [1] */
+		0, 0,
+		/* IP3_23 [1] */
+		0, 0,
+		/* IP3_22 [1] */
+		0, 0,
+		/* IP3_21 [1] */
+		0, 0,
+		/* IP3_20 [1] */
+		0, 0,
+		/* IP3_19 [1] */
+		0, 0,
+		/* IP3_18 [1] */
+		0, 0,
+		/* IP3_17 [1] */
+		0, 0,
+		/* IP3_16 [1] */
+		0, 0,
+		/* IP3_15 [1] */
+		0, 0,
+		/* IP3_14 [1] */
+		FN_VI3_D11_Y3, 0,
+		/* IP3_13 [1] */
+		FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
+		/* IP3_12 [1] */
+		FN_VI3_D8_Y0, FN_AVB_CRS,
+		/* IP3_11 [1] */
+		FN_VI3_D7_C7, FN_AVB_PHY_INT,
+		/* IP3_10 [1] */
+		FN_VI3_D6_C6, FN_AVB_MAGIC,
+		/* IP3_9 [1] */
+		FN_VI3_D5_C5, FN_AVB_LINK,
+		/* IP3_8 [1] */
+		FN_VI3_D4_C4, FN_AVB_MDIO,
+		/* IP3_7 [1] */
+		FN_VI3_D3_C3, FN_AVB_MDC,
+		/* IP3_6 [1] */
+		FN_VI3_D2_C2, FN_AVB_GTX_CLK,
+		/* IP3_5 [1] */
+		FN_VI3_D1_C1, FN_AVB_TX_ER,
+		/* IP3_4 [1] */
+		FN_VI3_D0_C0, FN_AVB_TXD7,
+		/* IP3_3 [1] */
+		FN_VI3_VSYNC, FN_AVB_TXD6,
+		/* IP3_2 [1] */
+		FN_VI3_HSYNC, FN_AVB_TXD5,
+		/* IP3_1 [1] */
+		FN_VI3_CLKENB, FN_AVB_TXD4,
+		/* IP3_0 [1] */
+		FN_VI3_CLK, FN_AVB_TX_CLK,}
+	},
+	/* IPSR4 */
+	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
+			     1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 1, 1) {
+		/* IP4_31 [1] */
+		0, 0,
+		/* IP4_30 [1] */
+		0, 0,
+		/* IP4_29 [1] */
+		0, 0,
+		/* IP4_28 [1] */
+		0, 0,
+		/* IP4_27 [1] */
+		0, 0,
+		/* IP4_26 [1] */
+		0, 0,
+		/* IP4_25 [1] */
+		0, 0,
+		/* IP4_24 [1] */
+		FN_VI4_FIELD, FN_VI3_D15_Y7,
+		/* IP4_23 [1] */
+		FN_VI4_D11_Y3, FN_VI3_D14_Y6,
+		/* IP4_22 [1] */
+		FN_VI4_D10_Y2, FN_VI3_D13_Y5,
+		/* IP4_21 [1] */
+		FN_VI4_D9_Y1, FN_VI3_D12_Y4,
+		/* IP4_20_19 [2] */
+		FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
+		/* IP4_18_17 [2] */
+		FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
+		/* IP4_16_15 [2] */
+		FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
+		/* IP4_14_13 [2] */
+		FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
+		/* IP4_12_11 [2] */
+		FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7_0, 0,
+		/* IP4_10_9 [2] */
+		FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6_0, 0,
+		/* IP4_8_7 [2] */
+		FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5_0, 0,
+		/* IP4_6_5 [2] */
+		FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4_0, 0,
+		/* IP4_4 [1] */
+		FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
+		/* IP4_3_2 [2] */
+		FN_VI4_VSYNC, FN_VI0_D14_G6_Y6, 0, 0,
+		/* IP4_1 [1] */
+		FN_VI4_HSYNC, FN_VI0_D13_G5_Y5,
+		/* IP4_0 [1] */
+		FN_VI4_CLKENB, FN_VI0_D12_G4_Y4,}
+	},
+	/* IPSR5 */
+	{ PINMUX_CFG_REG("IPSR5", 0xE6060054, 32, 1) {
+		/* IP5_31 [1] */
+		0, 0,
+		/* IP5_30 [1] */
+		0, 0,
+		/* IP5_29 [1] */
+		0, 0,
+		/* IP5_28 [1] */
+		0, 0,
+		/* IP5_27 [1] */
+		0, 0,
+		/* IP5_26 [1] */
+		0, 0,
+		/* IP5_25 [1] */
+		0, 0,
+		/* IP5_24 [1] */
+		0, 0,
+		/* IP5_23 [1] */
+		0, 0,
+		/* IP5_22 [1] */
+		0, 0,
+		/* IP5_21 [1] */
+		0, 0,
+		/* IP5_20 [1] */
+		0, 0,
+		/* IP5_19 [1] */
+		0, 0,
+		/* IP5_18 [1] */
+		0, 0,
+		/* IP5_17 [1] */
+		0, 0,
+		/* IP5_16 [1] */
+		0, 0,
+		/* IP5_15 [1] */
+		0, 0,
+		/* IP5_14 [1] */
+		0, 0,
+		/* IP5_13 [1] */
+		0, 0,
+		/* IP5_12 [1] */
+		0, 0,
+		/* IP5_11 [1] */
+		FN_VI5_D8_Y0, FN_VI1_D23_R7,
+		/* IP5_10 [1] */
+		FN_VI5_D7_C7, FN_VI1_D22_R6,
+		/* IP5_9 [1] */
+		FN_VI5_D6_C6, FN_VI1_D21_R5,
+		/* IP5_8 [1] */
+		FN_VI5_D5_C5, FN_VI1_D20_R4,
+		/* IP5_7 [1] */
+		FN_VI5_D4_C4, FN_VI1_D19_R3,
+		/* IP5_6 [1] */
+		FN_VI5_D3_C3, FN_VI1_D18_R2,
+		/* IP5_5 [1] */
+		FN_VI5_D2_C2, FN_VI1_D17_R1,
+		/* IP5_4 [1] */
+		FN_VI5_D1_C1, FN_VI1_D16_R0,
+		/* IP5_3 [1] */
+		FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_1,
+		/* IP5_2 [1] */
+		FN_VI5_VSYNC, FN_VI1_D14_G6_Y6_1,
+		/* IP5_1 [1] */
+		FN_VI5_HSYNC, FN_VI1_D13_G5_Y5_1,
+		/* IP5_0 [1] */
+		FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_1,}
+	},
+	/* IPSR6 */
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			     2, 1, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1) {
+		/* IP6_31 [1] */
+		0, 0,
+		/* IP6_30 [1] */
+		0, 0,
+		/* IP6_29 [1] */
+		0, 0,
+		/* IP6_28 [1] */
+		0, 0,
+		/* IP6_27 [1] */
+		0, 0,
+		/* IP6_26 [1] */
+		0, 0,
+		/* IP6_25 [1] */
+		0, 0,
+		/* IP6_24 [1] */
+		0, 0,
+		/* IP6_23 [1] */
+		0, 0,
+		/* IP6_22 [1] */
+		0, 0,
+		/* IP6_21 [1] */
+		0, 0,
+		/* IP6_20 [1] */
+		0, 0,
+		/* IP6_19 [1] */
+		0, 0,
+		/* IP6_18_17 [2] */
+		FN_DREQ1, FN_RX3, 0, 0,
+		/* IP6_16 [1] */
+		FN_TX3, 0,
+		/* IP6_15_14 [2] */
+		FN_DACK1, FN_SCK3, 0, 0,
+		/* IP6_13_12 [2] */
+		FN_DREQ0, FN_RX2, 0, 0,
+		/* IP6_11_10 [2] */
+		FN_DACK0, FN_TX2, 0, 0,
+		/* IP6_9_8 [2] */
+		FN_DRACK0, FN_SCK2, 0, 0,
+		/* IP6_7 [1] */
+		FN_MSIOF1_RXD, FN_HRX1,
+		/* IP6_6 [1] */
+		FN_MSIOF1_TXD, FN_HTX1,
+		/* IP6_5 [1] */
+		FN_MSIOF1_SYNC, FN_HRTS1,
+		/* IP6_4 [1] */
+		FN_MSIOF1_SCK, FN_HSCK1,
+		/* IP6_3 [1] */
+		FN_MSIOF0_RXD, FN_HRX0,
+		/* IP6_2 [1] */
+		FN_MSIOF0_TXD, FN_HTX0,
+		/* IP6_1 [1] */
+		FN_MSIOF0_SYNC, FN_HCTS0,
+		/* IP6_0 [1] */
+		FN_MSIOF0_SCK, FN_HSCK0, }
+	},
+	/* IPSR7 */
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 1, 2, 2, 2, 2, 1, 1, 2, 2, 2) {
+		/* IP7_31 [1] */
+		0, 0,
+		/* IP7_30 [1] */
+		0, 0,
+		/* IP7_29 [1] */
+		0, 0,
+		/* IP7_28 [1] */
+		0, 0,
+		/* IP7_27 [1] */
+		0, 0,
+		/* IP7_26 [1] */
+		0, 0,
+		/* IP7_25 [1] */
+		0, 0,
+		/* IP7_24 [1] */
+		0, 0,
+		/* IP7_23 [1] */
+		0, 0,
+		/* IP7_22 [1] */
+		0, 0,
+		/* IP7_21 [1] */
+		0, 0,
+		/* IP7_20 [1] */
+		FN_AUDIO_CLKB, 0,
+		/* IP7_19 [1] */
+		FN_AUDIO_CLKA, 0,
+		/* IP7_18 [1] */
+		FN_AUDIO_CLKOUT, 0,
+		/* IP7_17 [1] */
+		FN_SSI_SDATA4, 0,
+		/* IP7_16 [1] */
+		FN_SSI_WS4, 0,
+		/* IP7_15_14 [2] */
+		FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
+		/* IP7_13_12 [2] */
+		FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
+		/* IP7_11_10 [2] */
+		FN_SSI_WS3, FN_TPU0TO1, 0, 0,
+		/* IP7_9_8 [2] */
+		FN_SSI_SCK3, FN_TPU0TO0, 0, 0,
+		/* IP7_7 [1] */
+		FN_PWM4, 0,
+		/* IP7_6 [1] */
+		FN_PWM3, 0,
+		/* IP7_5_4 [2] */
+		FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
+		/* IP7_3_2 [2] */
+		FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
+		/* IP7_1_0 [2] */
+		FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0, }
+	},
+	/* MOD SEL */
+	{ PINMUX_CFG_REG("MOD_SEL", 0xE6060140, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		/* MOD_SEL [1] */
+		FN_SEL_VI1_0, FN_SEL_VI1_1, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_0_28_IN, GP_0_28_OUT,
+		GP_0_27_IN, GP_0_27_OUT,
+		GP_0_26_IN, GP_0_26_OUT,
+		GP_0_25_IN, GP_0_25_OUT,
+		GP_0_24_IN, GP_0_24_OUT,
+		GP_0_23_IN, GP_0_23_OUT,
+		GP_0_22_IN, GP_0_22_OUT,
+		GP_0_21_IN, GP_0_21_OUT,
+		GP_0_20_IN, GP_0_20_OUT,
+		GP_0_19_IN, GP_0_19_OUT,
+		GP_0_18_IN, GP_0_18_OUT,
+		GP_0_17_IN, GP_0_17_OUT,
+		GP_0_16_IN, GP_0_16_OUT,
+		GP_0_15_IN, GP_0_15_OUT,
+		GP_0_14_IN, GP_0_14_OUT,
+		GP_0_13_IN, GP_0_13_OUT,
+		GP_0_12_IN, GP_0_12_OUT,
+		GP_0_11_IN, GP_0_11_OUT,
+		GP_0_10_IN, GP_0_10_OUT,
+		GP_0_9_IN, GP_0_9_OUT,
+		GP_0_8_IN, GP_0_8_OUT,
+		GP_0_7_IN, GP_0_7_OUT,
+		GP_0_6_IN, GP_0_6_OUT,
+		GP_0_5_IN, GP_0_5_OUT,
+		GP_0_4_IN, GP_0_4_OUT,
+		GP_0_3_IN, GP_0_3_OUT,
+		GP_0_2_IN, GP_0_2_OUT,
+		GP_0_1_IN, GP_0_1_OUT,
+		GP_0_0_IN, GP_0_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_3_27_IN, GP_3_27_OUT,
+		GP_3_26_IN, GP_3_26_OUT,
+		GP_3_25_IN, GP_3_25_OUT,
+		GP_3_24_IN, GP_3_24_OUT,
+		GP_3_23_IN, GP_3_23_OUT,
+		GP_3_22_IN, GP_3_22_OUT,
+		GP_3_21_IN, GP_3_21_OUT,
+		GP_3_20_IN, GP_3_20_OUT,
+		GP_3_19_IN, GP_3_19_OUT,
+		GP_3_18_IN, GP_3_18_OUT,
+		GP_3_17_IN, GP_3_17_OUT,
+		GP_3_16_IN, GP_3_16_OUT,
+		GP_3_15_IN, GP_3_15_OUT,
+		GP_3_14_IN, GP_3_14_OUT,
+		GP_3_13_IN, GP_3_13_OUT,
+		GP_3_12_IN, GP_3_12_OUT,
+		GP_3_11_IN, GP_3_11_OUT,
+		GP_3_10_IN, GP_3_10_OUT,
+		GP_3_9_IN, GP_3_9_OUT,
+		GP_3_8_IN, GP_3_8_OUT,
+		GP_3_7_IN, GP_3_7_OUT,
+		GP_3_6_IN, GP_3_6_OUT,
+		GP_3_5_IN, GP_3_5_OUT,
+		GP_3_4_IN, GP_3_4_OUT,
+		GP_3_3_IN, GP_3_3_OUT,
+		GP_3_2_IN, GP_3_2_OUT,
+		GP_3_1_IN, GP_3_1_OUT,
+		GP_3_0_IN, GP_3_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_16_IN, GP_4_16_OUT,
+		GP_4_15_IN, GP_4_15_OUT,
+		GP_4_14_IN, GP_4_14_OUT,
+		GP_4_13_IN, GP_4_13_OUT,
+		GP_4_12_IN, GP_4_12_OUT,
+		GP_4_11_IN, GP_4_11_OUT,
+		GP_4_10_IN, GP_4_10_OUT,
+		GP_4_9_IN, GP_4_9_OUT,
+		GP_4_8_IN, GP_4_8_OUT,
+		GP_4_7_IN, GP_4_7_OUT,
+		GP_4_6_IN, GP_4_6_OUT,
+		GP_4_5_IN, GP_4_5_OUT,
+		GP_4_4_IN, GP_4_4_OUT,
+		GP_4_3_IN, GP_4_3_OUT,
+		GP_4_2_IN, GP_4_2_OUT,
+		GP_4_1_IN, GP_4_1_OUT,
+		GP_4_0_IN, GP_4_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_16_IN, GP_5_16_OUT,
+		GP_5_15_IN, GP_5_15_OUT,
+		GP_5_14_IN, GP_5_14_OUT,
+		GP_5_13_IN, GP_5_13_OUT,
+		GP_5_12_IN, GP_5_12_OUT,
+		GP_5_11_IN, GP_5_11_OUT,
+		GP_5_10_IN, GP_5_10_OUT,
+		GP_5_9_IN, GP_5_9_OUT,
+		GP_5_8_IN, GP_5_8_OUT,
+		GP_5_7_IN, GP_5_7_OUT,
+		GP_5_6_IN, GP_5_6_OUT,
+		GP_5_5_IN, GP_5_5_OUT,
+		GP_5_4_IN, GP_5_4_OUT,
+		GP_5_3_IN, GP_5_3_OUT,
+		GP_5_2_IN, GP_5_2_OUT,
+		GP_5_1_IN, GP_5_1_OUT,
+		GP_5_0_IN, GP_5_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055104, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_16_IN, GP_6_16_OUT,
+		GP_6_15_IN, GP_6_15_OUT,
+		GP_6_14_IN, GP_6_14_OUT,
+		GP_6_13_IN, GP_6_13_OUT,
+		GP_6_12_IN, GP_6_12_OUT,
+		GP_6_11_IN, GP_6_11_OUT,
+		GP_6_10_IN, GP_6_10_OUT,
+		GP_6_9_IN, GP_6_9_OUT,
+		GP_6_8_IN, GP_6_8_OUT,
+		GP_6_7_IN, GP_6_7_OUT,
+		GP_6_6_IN, GP_6_6_OUT,
+		GP_6_5_IN, GP_6_5_OUT,
+		GP_6_4_IN, GP_6_4_OUT,
+		GP_6_3_IN, GP_6_3_OUT,
+		GP_6_2_IN, GP_6_2_OUT,
+		GP_6_1_IN, GP_6_1_OUT,
+		GP_6_0_IN, GP_6_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL7", 0xE6055204, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_16_IN, GP_7_16_OUT,
+		GP_7_15_IN, GP_7_15_OUT,
+		GP_7_14_IN, GP_7_14_OUT,
+		GP_7_13_IN, GP_7_13_OUT,
+		GP_7_12_IN, GP_7_12_OUT,
+		GP_7_11_IN, GP_7_11_OUT,
+		GP_7_10_IN, GP_7_10_OUT,
+		GP_7_9_IN, GP_7_9_OUT,
+		GP_7_8_IN, GP_7_8_OUT,
+		GP_7_7_IN, GP_7_7_OUT,
+		GP_7_6_IN, GP_7_6_OUT,
+		GP_7_5_IN, GP_7_5_OUT,
+		GP_7_4_IN, GP_7_4_OUT,
+		GP_7_3_IN, GP_7_3_OUT,
+		GP_7_2_IN, GP_7_2_OUT,
+		GP_7_1_IN, GP_7_1_OUT,
+		GP_7_0_IN, GP_7_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL8", 0xE6055304, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_8_16_IN, GP_8_16_OUT,
+		GP_8_15_IN, GP_8_15_OUT,
+		GP_8_14_IN, GP_8_14_OUT,
+		GP_8_13_IN, GP_8_13_OUT,
+		GP_8_12_IN, GP_8_12_OUT,
+		GP_8_11_IN, GP_8_11_OUT,
+		GP_8_10_IN, GP_8_10_OUT,
+		GP_8_9_IN, GP_8_9_OUT,
+		GP_8_8_IN, GP_8_8_OUT,
+		GP_8_7_IN, GP_8_7_OUT,
+		GP_8_6_IN, GP_8_6_OUT,
+		GP_8_5_IN, GP_8_5_OUT,
+		GP_8_4_IN, GP_8_4_OUT,
+		GP_8_3_IN, GP_8_3_OUT,
+		GP_8_2_IN, GP_8_2_OUT,
+		GP_8_1_IN, GP_8_1_OUT,
+		GP_8_0_IN, GP_8_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL9", 0xE6055404, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_9_16_IN, GP_9_16_OUT,
+		GP_9_15_IN, GP_9_15_OUT,
+		GP_9_14_IN, GP_9_14_OUT,
+		GP_9_13_IN, GP_9_13_OUT,
+		GP_9_12_IN, GP_9_12_OUT,
+		GP_9_11_IN, GP_9_11_OUT,
+		GP_9_10_IN, GP_9_10_OUT,
+		GP_9_9_IN, GP_9_9_OUT,
+		GP_9_8_IN, GP_9_8_OUT,
+		GP_9_7_IN, GP_9_7_OUT,
+		GP_9_6_IN, GP_9_6_OUT,
+		GP_9_5_IN, GP_9_5_OUT,
+		GP_9_4_IN, GP_9_4_OUT,
+		GP_9_3_IN, GP_9_3_OUT,
+		GP_9_2_IN, GP_9_2_OUT,
+		GP_9_1_IN, GP_9_1_OUT,
+		GP_9_0_IN, GP_9_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL10", 0xE6055504, 32, 1) { GP_INOUTSEL(10) } },
+	{ PINMUX_CFG_REG("INOUTSEL11", 0xE6055604, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_11_29_IN, GP_11_29_OUT,
+		GP_11_28_IN, GP_11_28_OUT,
+		GP_11_27_IN, GP_11_27_OUT,
+		GP_11_26_IN, GP_11_26_OUT,
+		GP_11_25_IN, GP_11_25_OUT,
+		GP_11_24_IN, GP_11_24_OUT,
+		GP_11_23_IN, GP_11_23_OUT,
+		GP_11_22_IN, GP_11_22_OUT,
+		GP_11_21_IN, GP_11_21_OUT,
+		GP_11_20_IN, GP_11_20_OUT,
+		GP_11_19_IN, GP_11_19_OUT,
+		GP_11_18_IN, GP_11_18_OUT,
+		GP_11_17_IN, GP_11_17_OUT,
+		GP_11_16_IN, GP_11_16_OUT,
+		GP_11_15_IN, GP_11_15_OUT,
+		GP_11_14_IN, GP_11_14_OUT,
+		GP_11_13_IN, GP_11_13_OUT,
+		GP_11_12_IN, GP_11_12_OUT,
+		GP_11_11_IN, GP_11_11_OUT,
+		GP_11_10_IN, GP_11_10_OUT,
+		GP_11_9_IN, GP_11_9_OUT,
+		GP_11_8_IN, GP_11_8_OUT,
+		GP_11_7_IN, GP_11_7_OUT,
+		GP_11_6_IN, GP_11_6_OUT,
+		GP_11_5_IN, GP_11_5_OUT,
+		GP_11_4_IN, GP_11_4_OUT,
+		GP_11_3_IN, GP_11_3_OUT,
+		GP_11_2_IN, GP_11_2_OUT,
+		GP_11_1_IN, GP_11_1_OUT,
+		GP_11_0_IN, GP_11_0_OUT, }
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
+		0, 0, 0, GP_0_28_DATA,
+		GP_0_27_DATA, GP_0_26_DATA, GP_0_25_DATA, GP_0_24_DATA,
+		GP_0_23_DATA, GP_0_22_DATA, GP_0_21_DATA, GP_0_20_DATA,
+		GP_0_19_DATA, GP_0_18_DATA, GP_0_17_DATA, GP_0_16_DATA,
+		GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
+		GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
+		GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
+		GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
+		0, 0, 0, 0,
+		GP_3_27_DATA, GP_3_26_DATA, GP_3_25_DATA, GP_3_24_DATA,
+		GP_3_23_DATA, GP_3_22_DATA, GP_3_21_DATA, GP_3_20_DATA,
+		GP_3_19_DATA, GP_3_18_DATA, GP_3_17_DATA, GP_3_16_DATA,
+		GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
+		GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
+		GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
+		GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_4_16_DATA,
+		GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
+		GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
+		GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
+		GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_5_16_DATA,
+		GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
+		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
+		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
+		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT6", 0xE6055108, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_6_16_DATA,
+		GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
+		GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
+		GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
+		GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT7", 0xE6055208, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_7_16_DATA,
+		GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
+		GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
+		GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
+		GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT8", 0xE6055308, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_8_16_DATA,
+		GP_8_15_DATA, GP_8_14_DATA, GP_8_13_DATA, GP_8_12_DATA,
+		GP_8_11_DATA, GP_8_10_DATA, GP_8_9_DATA, GP_8_8_DATA,
+		GP_8_7_DATA, GP_8_6_DATA, GP_8_5_DATA, GP_8_4_DATA,
+		GP_8_3_DATA, GP_8_2_DATA, GP_8_1_DATA, GP_8_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT9", 0xE6055408, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_9_16_DATA,
+		GP_9_15_DATA, GP_9_14_DATA, GP_9_13_DATA, GP_9_12_DATA,
+		GP_9_11_DATA, GP_9_10_DATA, GP_9_9_DATA, GP_9_8_DATA,
+		GP_9_7_DATA, GP_9_6_DATA, GP_9_5_DATA, GP_9_4_DATA,
+		GP_9_3_DATA, GP_9_2_DATA, GP_9_1_DATA, GP_9_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT10", 0xE6055508, 32) { GP_INDT(10) } },
+	{ PINMUX_DATA_REG("INDT11", 0xE6055608, 32) {
+		0, 0, GP_11_29_DATA, GP_11_28_DATA,
+		GP_11_27_DATA, GP_11_26_DATA, GP_11_25_DATA, GP_11_24_DATA,
+		GP_11_23_DATA, GP_11_22_DATA, GP_11_21_DATA, GP_11_20_DATA,
+		GP_11_19_DATA, GP_11_18_DATA, GP_11_17_DATA, GP_11_16_DATA,
+		GP_11_15_DATA, GP_11_14_DATA, GP_11_13_DATA, GP_11_12_DATA,
+		GP_11_11_DATA, GP_11_10_DATA, GP_11_9_DATA, GP_11_8_DATA,
+		GP_11_7_DATA, GP_11_6_DATA, GP_11_5_DATA, GP_11_4_DATA,
+		GP_11_3_DATA, GP_11_2_DATA, GP_11_1_DATA, GP_11_0_DATA }
+	},
+	{ },
+};
+
+static struct pinmux_info r8a7792_pinmux_info = {
+	.name = "r8a7792_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_AUDIO_CLKB,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7792_pinmux_init(void)
+{
+	register_pinmux(&r8a7792_pinmux_info);
+}
+
diff --git a/board/renesas/blanche/Kconfig b/board/renesas/blanche/Kconfig
new file mode 100644
index 0000000..ac4730a
--- /dev/null
+++ b/board/renesas/blanche/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BLANCHE
+
+config SYS_BOARD
+	default "blanche"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "blanche"
+
+endif
diff --git a/board/renesas/blanche/Makefile b/board/renesas/blanche/Makefile
new file mode 100644
index 0000000..bdbfb29
--- /dev/null
+++ b/board/renesas/blanche/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/blanche/Makefile
+#
+# Copyright (C) 2016 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= blanche.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
new file mode 100644
index 0000000..717c169
--- /dev/null
+++ b/board/renesas/blanche/blanche.c
@@ -0,0 +1,458 @@
+/*
+ * board/renesas/blanche/blanche.c
+ *     This file is blanche board support.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pin_db {
+	u32	addr;	/* register address */
+	u32	mask;	/* mask value */
+	u32	val;	/* setting value */
+};
+
+#define	PMMR		0xE6060000
+#define	GPSR10		0xE606002C
+#define	PUPR3		0xE606010C
+#define	PUPR10		0xE6060128
+#define	PUPR11		0xE606012C
+
+#define	CPG_PLL1CR	0xE6150028
+#define	CPG_PLL3CR	0xE61500DC
+
+#define	SetREG(x) \
+	writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
+
+#define	SetGuardREG(x)				\
+{ \
+	u32	val; \
+	val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
+	writel(~val, PMMR); \
+	writel(val, (x)->addr); \
+}
+
+struct pin_db	pin_guard[] = {
+	{ GPSR10,	0xFFFFFFFF,	0x04006000 },
+};
+
+struct pin_db	pin_tbl[] = {
+	{ PUPR3,	0xFFFFFFFF,	0x0803FF40 },
+	{ PUPR10,	0xFFFFFFFF,	0xC0438001 },
+	{ PUPR11,	0xFFFFFFFF,	0x0FC00007 },
+};
+
+void pin_init(void)
+{
+	struct pin_db	*db;
+
+	for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
+		SetGuardREG(db);
+	}
+	for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
+		SetREG(db);
+	}
+}
+
+#define s_init_wait(cnt) \
+		({	\
+			volatile u32 i = 0x10000 * cnt;	\
+			while (i > 0)	\
+				i--;	\
+		})
+
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 cpu_type;
+
+	cpu_type = rmobile_get_cpu_type();
+	if (cpu_type == 0x4A) {
+		writel(0x4D000000, CPG_PLL1CR);
+		writel(0x4F000000, CPG_PLL3CR);
+	}
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+
+	/* SCIF Init */
+	pin_init();
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+	struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
+	struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x2A103320, &lbsc->cswcr0);
+	writel(0x2A103320, &lbsc->cswcr1);
+	writel(0x19102110, &lbsc->ecswcr0);
+	writel(0x19102110, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+
+	writel(0x21000000, &dbsc3_0->dbcmd);		/* opc=RstH (RESET => H) */
+	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */
+	writel(0x10000000, &dbsc3_0->dbcmd);		/* opc=PDEn(CKE=L) */
+
+	/* Stop Auto-Calibration */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* PLLCR: PLL Control Register */
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);	// > DDR1440
+
+	/* DXCCR: DATX8 Common Configuration Register */
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	/* DSGCR	:DDR System General Configuration Register */
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF00464DB, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000061, &dbsc3_0->dbpdrga);
+	writel(0x0000008D, &dbsc3_0->dbpdrgd);
+
+	/* Re-Execute ZQ calibration */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000073, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x0F030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+
+	writel(0x0000000B, &dbsc3_0->dbtr0);	// tCL=11
+	writel(0x00000008, &dbsc3_0->dbtr1);	// tCWL=8
+	writel(0x00000000, &dbsc3_0->dbtr2);	// tAL=0
+	writel(0x0000000B, &dbsc3_0->dbtr3);	// tRCD=11
+	writel(0x000C000B, &dbsc3_0->dbtr4);	// tRPA=12,tRP=11
+	writel(0x00000027, &dbsc3_0->dbtr5);	// tRC = 39
+	writel(0x0000001C, &dbsc3_0->dbtr6);	// tRAS = 28
+	writel(0x00000006, &dbsc3_0->dbtr7);	// tRRD = 6
+	writel(0x00000020, &dbsc3_0->dbtr8);	// tRFAW = 32
+	writel(0x00000008, &dbsc3_0->dbtr9);	// tRDPR = 8
+	writel(0x0000000C, &dbsc3_0->dbtr10);	// tWR = 12
+	writel(0x00000009, &dbsc3_0->dbtr11);	// tRDWR = 9
+	writel(0x00000012, &dbsc3_0->dbtr12);	// tWRRD = 18
+	writel(0x000000D0, &dbsc3_0->dbtr13);	// tRFC = 208
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);		/* DQL = 35, WDQL = 5 */
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082004, &dbsc3_0->dbadj2);		/* blanche QoS rev0.1 */
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);	/* 1600 */
+	writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
+
+	while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
+	writel(0x00000011, &dbsc3_0->dbdficnt);
+
+	/* PGCR1	:PHY General Configuration Register 1 */
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C4E1, &dbsc3_0->dbpdrgd);		/* DDR3 */
+
+	/* PGCR2: PHY General Configuration Registers 2 */
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	/* DTPR0	:DRAM Timing Parameters Register 0 */
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
+
+	/* DTPR1	:DRAM Timing Parameters Register 1 */
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868400, &dbsc3_0->dbpdrgd);
+
+	/* DTPR2	::DRAM Timing Parameters Register 2 */
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	/* MR0	:Mode Register 0 */
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	/* MR1	:Mode Register 1 */
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000004, &dbsc3_0->dbpdrgd);	/* DRAM Drv 40ohm */
+
+	/* MR2	:Mode Register 2 */
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);	/* CWL=8 */
+
+	/* VREF(ZQCAL) */
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x910035C7, &dbsc3_0->dbpdrgd);
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* DRAM Init (set MRx etc) */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	/* CKE  = H */
+	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* RAM ACC Training */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	/* Bus control 0 */
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	/* DDR3 Calibration set */
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	/* DDR3 Calibration timing */
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	/* Refresh */
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* Enable Auto-Refresh */
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	/* Permit DDR-Access */
+	writel(0x00000001, &dbsc3_0->dbacen);
+
+	/* This locks the access to the PHY unit registers */
+	writel(0x00000000, &dbsc3_0->dbpdlck);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+}
+
+#define TMU0_MSTP125	(1 << 25)
+#define SCIF0_MSTP721	(1 << 21)
+#define SDHI0_MSTP314	(1 << 14)
+#define QSPI_MSTP917	(1 << 17)
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	/* SCIF0 */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+	/* SDHI0 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
+	/* QSPI */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7792_pinmux_init();
+
+	gpio_request(GPIO_FN_D0, NULL);
+	gpio_request(GPIO_FN_D1, NULL);
+	gpio_request(GPIO_FN_D2, NULL);
+	gpio_request(GPIO_FN_D3, NULL);
+	gpio_request(GPIO_FN_D4, NULL);
+	gpio_request(GPIO_FN_D5, NULL);
+	gpio_request(GPIO_FN_D6, NULL);
+	gpio_request(GPIO_FN_D7, NULL);
+	gpio_request(GPIO_FN_D8, NULL);
+	gpio_request(GPIO_FN_D9, NULL);
+	gpio_request(GPIO_FN_D10, NULL);
+	gpio_request(GPIO_FN_D11, NULL);
+	gpio_request(GPIO_FN_D12, NULL);
+	gpio_request(GPIO_FN_D13, NULL);
+	gpio_request(GPIO_FN_D14, NULL);
+	gpio_request(GPIO_FN_D15, NULL);
+	gpio_request(GPIO_FN_A0, NULL);
+	gpio_request(GPIO_FN_A1, NULL);
+	gpio_request(GPIO_FN_A2, NULL);
+	gpio_request(GPIO_FN_A3, NULL);
+	gpio_request(GPIO_FN_A4, NULL);
+	gpio_request(GPIO_FN_A5, NULL);
+	gpio_request(GPIO_FN_A6, NULL);
+	gpio_request(GPIO_FN_A7, NULL);
+	gpio_request(GPIO_FN_A8, NULL);
+	gpio_request(GPIO_FN_A9, NULL);
+	gpio_request(GPIO_FN_A10, NULL);
+	gpio_request(GPIO_FN_A11, NULL);
+	gpio_request(GPIO_FN_A12, NULL);
+	gpio_request(GPIO_FN_A13, NULL);
+	gpio_request(GPIO_FN_A14, NULL);
+	gpio_request(GPIO_FN_A15, NULL);
+	gpio_request(GPIO_FN_A16, NULL);
+	gpio_request(GPIO_FN_A17, NULL);
+	gpio_request(GPIO_FN_A18, NULL);
+	gpio_request(GPIO_FN_A19, NULL);
+#if defined(CONFIG_SYS_NO_FLASH)
+	gpio_request(GPIO_FN_MOSI_IO0, NULL);
+	gpio_request(GPIO_FN_MISO_IO1, NULL);
+	gpio_request(GPIO_FN_IO2, NULL);
+	gpio_request(GPIO_FN_IO3, NULL);
+	gpio_request(GPIO_FN_SPCLK, NULL);
+	gpio_request(GPIO_FN_SSL, NULL);
+#else	/* CONFIG_SYS_NO_FLASH */
+	gpio_request(GPIO_FN_A20, NULL);
+	gpio_request(GPIO_FN_A21, NULL);
+	gpio_request(GPIO_FN_A22, NULL);
+	gpio_request(GPIO_FN_A23, NULL);
+	gpio_request(GPIO_FN_A24, NULL);
+	gpio_request(GPIO_FN_A25, NULL);
+#endif	/* CONFIG_SYS_NO_FLASH */
+
+	gpio_request(GPIO_FN_CS1_A26, NULL);
+	gpio_request(GPIO_FN_EX_CS0, NULL);
+	gpio_request(GPIO_FN_EX_CS1, NULL);
+	gpio_request(GPIO_FN_BS, NULL);
+	gpio_request(GPIO_FN_RD, NULL);
+	gpio_request(GPIO_FN_WE0, NULL);
+	gpio_request(GPIO_FN_WE1, NULL);
+	gpio_request(GPIO_FN_EX_WAIT0, NULL);
+	gpio_request(GPIO_FN_IRQ0, NULL);
+	gpio_request(GPIO_FN_IRQ2, NULL);
+	gpio_request(GPIO_FN_IRQ3, NULL);
+	gpio_request(GPIO_FN_CS0, NULL);
+
+	/* Init timer */
+	timer_init();
+
+	return 0;
+}
+
+/*
+ Added for BLANCHE(R-CarV2H board)
+*/
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR	"ethaddr"
+
+	struct eth_device *dev;
+	uchar eth_addr[6];
+
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+		dev = eth_get_dev_by_index(0);
+		if (dev) {
+			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+		} else {
+			printf("blanche: Couldn't get eth device\n");
+			rc = -1;
+		}
+	}
+
+#endif
+
+	return rc;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+#ifdef CONFIG_SH_SDHI
+	gpio_request(GPIO_FN_SD0_DAT0, NULL);
+	gpio_request(GPIO_FN_SD0_DAT1, NULL);
+	gpio_request(GPIO_FN_SD0_DAT2, NULL);
+	gpio_request(GPIO_FN_SD0_DAT3, NULL);
+	gpio_request(GPIO_FN_SD0_CLK, NULL);
+	gpio_request(GPIO_FN_SD0_CMD, NULL);
+	gpio_request(GPIO_FN_SD0_CD, NULL);
+
+	gpio_request(GPIO_GP_11_12, NULL);
+	gpio_direction_output(GPIO_GP_11_12, 1);	/* power on */
+
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+			   SH_SDHI_QUIRK_16BIT_BUF);
+
+	if (ret)
+		return ret;
+#endif
+	return ret;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+}
+
+static const struct sh_serial_platdata serial_platdata = {
+	.base = SCIF0_BASE,
+	.type = PORT_SCIF,
+	.clk = 14745600,
+	.clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(blanche_serials) = {
+	.name = "serial_sh",
+	.platdata = &serial_platdata,
+};
diff --git a/board/renesas/blanche/qos.c b/board/renesas/blanche/qos.c
new file mode 100644
index 0000000..f1327f6
--- /dev/null
+++ b/board/renesas/blanche/qos.c
@@ -0,0 +1,1366 @@
+/*
+ * board/renesas/blanche/qos.c
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20082004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	// writel(0x00000000, &s3c->s3cadsplcr);
+	writel(0x1F0D0C0C, &s3c->s3crorr);
+	writel(0x1F1F0C0C, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000204B, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FC4, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000205A, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000100, &mxi->mxaxirtcr);
+	writel(0xFF530100, &mxi->mxaxiwtcr);
+	writel(0x00000100, &mxi->mxs3crtcr);
+	writel(0xFF530100, &mxi->mxs3cwtcr);
+	writel(0x004000C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADM_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AXI64TO128W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVBW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2DW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTXBW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRABW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADMW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADSW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYXW_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000211B, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256W_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXMW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2W_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RT_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHXW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBGW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTW_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000000A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002018, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002259, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_RDRW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002006, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002042, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* DMS Register(SYS-AXI) */
+	writel(0x00000000, SYS_AXI_AVBDMSCR);
+	writel(0x00000000, SYS_AXI_AX2MDMSCR);
+	writel(0x00000000, SYS_AXI_CC50DMSCR);
+	writel(0x00000000, SYS_AXI_CCIDMSCR);
+	writel(0x00000000, SYS_AXI_CSDMSCR);
+	writel(0x00000000, SYS_AXI_G2DDMSCR);
+	writel(0x00000000, SYS_AXI_IMP1DMSCR);
+	writel(0x00000000, SYS_AXI_LBSMDMSCR);
+	writel(0x00000000, SYS_AXI_MMUDSDMSCR);
+	writel(0x00000000, SYS_AXI_MMUMXDMSCR);
+	writel(0x00000000, SYS_AXI_MMUS0DMSCR);
+	writel(0x00000000, SYS_AXI_MMUS1DMSCR);
+	writel(0x00000000, SYS_AXI_RTMXDMSCR);
+	writel(0x00000000, SYS_AXI_SDM0DMSCR);
+	writel(0x00000000, SYS_AXI_SDM1DMSCR);
+	writel(0x00000000, SYS_AXI_SDS0DMSCR);
+	writel(0x00000000, SYS_AXI_SDS1DMSCR);
+	writel(0x00000000, SYS_AXI_TRABDMSCR);
+	writel(0x00000000, SYS_AXI_X128TO64SLVDMSCR);
+	writel(0x00000000, SYS_AXI_X64TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI_AVBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_AX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_GICSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_LBSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_MXTSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_QSAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_RTXSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC65SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC8SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SGXSLV1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STMSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBDSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_ROT0DMSCR);
+	writel(0x00000000, SYS_AXI_ROT1DMSCR);
+	writel(0x00000000, SYS_AXI_ROT2DMSCR);
+	writel(0x00000000, SYS_AXI_ROT3DMSCR);
+	writel(0x00000000, SYS_AXI_ROT4DMSCR);
+	writel(0x00000000, SYS_AXI_IMUX3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_ADM_DMSCR);
+	writel(0x00000000, SYS_AXI_ADS_DMSCR);
+
+	/* DMS Register(RT-AXI) */
+	writel(0x00000000, DM_AXI_DMAXICONF);
+	writel(0x00000019, DM_AXI_DMAPBCONF);
+	writel(0x00000000, DM_AXI_DMADMCONF);
+	writel(0x00000000, DM_AXI_DMSDM0CONF);
+	writel(0x00000000, DM_AXI_DMSDM1CONF);
+	writel(0x00000004, DM_AXI_DMQSPAPSLVCONF);
+	writel(0x00000004, DM_AXI_RAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD5SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD6SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD65DSLVCONF);
+	writel(0x00000004, DM_AXI_SDAP0SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD2SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD3SLVCONF);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVCONF);
+	writel(0x00000100, DM_AXI_DMADMRQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMRQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMRQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMRQOSQON);
+	writel(0x00000005, DM_AXI_DMADMRQOSIN);
+	writel(0x00000000, DM_AXI_DMADMRQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSSTAT);
+	writel(0x00002041, DM_AXI_DMRQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMRQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMRQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMRQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMRQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMRQOSTHRES2);
+	writel(0x00000100, DM_AXI_DMADMWQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMWQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMWQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMWQOSQON);
+	writel(0x00000005, DM_AXI_DMADMWQOSIN);
+	writel(0x00000000, DM_AXI_DMADMWQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSSTAT);
+	writel(0x00002041, DM_AXI_DMWQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMWQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMWQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMWQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMWQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMWQOSTHRES2);
+	writel(0x00000000, DM_AXI_RDMDMSCR);
+	writel(0x00000000, DM_AXI_SDM0DMSCR);
+	writel(0x00000000, DM_AXI_SDM1DMSCR);
+	writel(0x00000000, DM_AXI_DMQSPAPSLVDMSCR);
+	writel(0x00000000, DM_AXI_RAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD5SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD6SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD65DSLVDMSCR);
+	writel(0x00000000, DM_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD2SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD3SLVDMSCR);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000001, DM_AXI_DMXREGDMSENN);
+
+	/* DMS Register(SYS-AXI256) */
+	writel(0x00000000, SYS_AXI256_SYXDMSCR);
+	writel(0x00000000, SYS_AXI256_MXIDMSCR);
+	writel(0x00000000, SYS_AXI256_X128TO256SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_X256TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_SYXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_CCXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_S3CSLVDMSCR);
+
+	/* DMS Register(MXT) */
+	writel(0x00000000, MXT_SYXDMSCR);
+	writel(0x00000000, MXT_IMRSLVDMSCR);
+	writel(0x00000000, MXT_VINSLVDMSCR);
+	writel(0x00000000, MXT_VPC1SLVDMSCR);
+	writel(0x00000000, MXT_VSPD0SLVDMSCR);
+	writel(0x00000000, MXT_VSPD1SLVDMSCR);
+	writel(0x00000000, MXT_MAP1SLVDMSCR);
+	writel(0x00000000, MXT_MAP2SLVDMSCR);
+	writel(0x00000000, MXT_MAP2BSLVDMSCR);
+
+	/* DMS Register(MXI) */
+	writel(0x00000002, MXI_JPURDMSCR);
+	writel(0x00000002, MXI_JPUWDMSCR);
+	writel(0x00000002, MXI_VCTU0RDMSCR);
+	writel(0x00000002, MXI_VCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU0RDMSCR);
+	writel(0x00000002, MXI_VDCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU1RDMSCR);
+	writel(0x00000002, MXI_VDCTU1WDMSCR);
+	writel(0x00000002, MXI_VIN0WDMSCR);
+	writel(0x00000002, MXI_VIN1WDMSCR);
+	writel(0x00000002, MXI_RDRWDMSCR);
+	writel(0x00000002, MXI_IMS01RDMSCR);
+	writel(0x00000002, MXI_IMS01WDMSCR);
+	writel(0x00000002, MXI_IMS23RDMSCR);
+	writel(0x00000002, MXI_IMS23WDMSCR);
+	writel(0x00000002, MXI_IMS45RDMSCR);
+	writel(0x00000002, MXI_IMS45WDMSCR);
+	writel(0x00000002, MXI_IMRRDMSCR);
+	writel(0x00000002, MXI_IMRWDMSCR);
+	writel(0x00000002, MXI_ROTCE4RDMSCR);
+	writel(0x00000002, MXI_ROTCE4WDMSCR);
+	writel(0x00000002, MXI_ROTVLC4RDMSCR);
+	writel(0x00000002, MXI_ROTVLC4WDMSCR);
+	writel(0x00000002, MXI_VSPD0RDMSCR);
+	writel(0x00000002, MXI_VSPD0WDMSCR);
+	writel(0x00000002, MXI_VSPD1RDMSCR);
+	writel(0x00000002, MXI_VSPD1WDMSCR);
+	writel(0x00000002, MXI_DU0RDMSCR);
+	writel(0x00000002, MXI_DU0WDMSCR);
+	writel(0x00000002, MXI_VSP0RDMSCR);
+	writel(0x00000002, MXI_VSP0WDMSCR);
+	writel(0x00000002, MXI_ROTCE0RDMSCR);
+	writel(0x00000002, MXI_ROTCE0WDMSCR);
+	writel(0x00000002, MXI_ROTVLC0RDMSCR);
+	writel(0x00000002, MXI_ROTVLC0WDMSCR);
+	writel(0x00000002, MXI_ROTCE1RDMSCR);
+	writel(0x00000002, MXI_ROTCE1WDMSCR);
+	writel(0x00000002, MXI_ROTVLC1RDMSCR);
+	writel(0x00000002, MXI_ROTVLC1WDMSCR);
+	writel(0x00000002, MXI_ROTCE2RDMSCR);
+	writel(0x00000002, MXI_ROTCE2WDMSCR);
+	writel(0x00000002, MXI_ROTVLC2RDMSCR);
+	writel(0x00000002, MXI_ROTVLC2WDMSCR);
+	writel(0x00000002, MXI_ROTCE3RDMSCR);
+	writel(0x00000002, MXI_ROTCE3WDMSCR);
+	writel(0x00000002, MXI_ROTVLC3RDMSCR);
+	writel(0x00000002, MXI_ROTVLC3WDMSCR);
+
+	/* DMS Register(CCI-AXI) */
+	writel(0x00000000, CCI_AXI_MMUS0DMSCR);
+	writel(0x00000000, CCI_AXI_SYX2DMSCR);
+	writel(0x00000000, CCI_AXI_MMURDMSCR);
+	writel(0x00000000, CCI_AXI_MMUDSDMSCR);
+	writel(0x00000000, CCI_AXI_MMUMDMSCR);
+	writel(0x00000000, CCI_AXI_MXIDMSCR);
+	writel(0x00000000, CCI_AXI_MMUS1DMSCR);
+	writel(0x00000000, CCI_AXI_MMUMPDMSCR);
+	writel(0x00000000, CCI_AXI_DVMDMSCR);
+	writel(0x00000000, CCI_AXI_CCISLVDMSCR);
+
+	/* CC-AXI Function Register */
+	writel(0x00000011, CCI_AXI_IPMMUIDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMURDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS0DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS1DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUMPDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUDSDVMCR);
+	writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
+
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/blanche/qos.h b/board/renesas/blanche/qos.h
new file mode 100644
index 0000000..e3ecddf
--- /dev/null
+++ b/board/renesas/blanche/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
new file mode 100644
index 0000000..180e771
--- /dev/null
+++ b/configs/blanche_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_RMOBILE=y
+CONFIG_TARGET_BLANCHE=y
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_SH_SDHI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
index dc4c686..e9d99a2 100644
--- a/drivers/mmc/sh_sdhi.c
+++ b/drivers/mmc/sh_sdhi.c
@@ -399,7 +399,6 @@ static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
 {
 	unsigned short i, j, cnt = 1;
 	unsigned short resp[8];
-	unsigned long *p1, *p2;
 
 	if (cmd->resp_type & MMC_RSP_136) {
 		cnt = 4;
@@ -418,30 +417,29 @@ static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
 			resp[i] |= (resp[j--] >> 8) & 0x00ff;
 		}
 		resp[0] = (resp[0] << 8) & 0xff00;
-
-		/* SDHI REGISTER SPECIFICATION */
-		p1 = ((unsigned long *)resp) + 3;
-
 	} else {
 		resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
 		resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
-
-		p1 = ((unsigned long *)resp);
 	}
 
-	p2 = (unsigned long *)cmd->response;
-
-	barrier();
-
 #if defined(__BIG_ENDIAN_BITFIELD)
-	for (i = 0; i < cnt; i++) {
-		*p2++ = ((*p1 >> 16) & 0x0000ffff) |
-				((*p1 << 16) & 0xffff0000);
-		p1--;
+	if (cnt == 4) {
+		cmd->response[0] = (resp[6] << 16) | resp[7];
+		cmd->response[1] = (resp[4] << 16) | resp[5];
+		cmd->response[2] = (resp[2] << 16) | resp[3];
+		cmd->response[3] = (resp[0] << 16) | resp[1];
+	} else {
+		cmd->response[0] = (resp[0] << 16) | resp[1];
 	}
 #else
-	for (i = 0; i < cnt; i++)
-		*p2++ = *p1--;
+	if (cnt == 4) {
+		cmd->response[0] = (resp[7] << 16) | resp[6];
+		cmd->response[1] = (resp[5] << 16) | resp[4];
+		cmd->response[2] = (resp[3] << 16) | resp[2];
+		cmd->response[3] = (resp[1] << 16) | resp[0];
+	} else {
+		cmd->response[0] = (resp[1] << 16) | resp[0];
+	}
 #endif /* __BIG_ENDIAN_BITFIELD */
 }
 
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index a95684b..348f544 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -225,8 +225,8 @@ struct uart_port {
 # define SCIF_ORER 0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \
-	defined(CONFIG_R8A7795)
+	defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
+	defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795)
 # if defined(CONFIG_SCIF_A)
 #  define SCIF_ORER	0x0200
 # else
@@ -308,7 +308,7 @@ struct uart_port {
 /* SH7763 SCIF2 support */
 # define SCIF2_RFDC_MASK 0x001f
 # define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 # if defined(CONFIG_SCIF_A)
@@ -566,7 +566,7 @@ SCIF_FNS(SCFCR,  0x18, 16)
 SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCLSR,  0x24, 16)
 SCIF_FNS(DL,	 0x00,  0) /* dummy */
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 /* SCIFA and SCIF register offsets and size */
 SCIx_FNS(SCSMR,  0,  0, 0x00, 16, 0,  0, 0x00, 16, 0,  0)
@@ -762,7 +762,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
  #if defined(CONFIG_SCIF_A)
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
new file mode 100755
index 0000000..7da87f7
--- /dev/null
+++ b/include/configs/blanche.h
@@ -0,0 +1,124 @@
+/*
+ * include/configs/blanche.h
+ *     This file is blanche board configuration.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BLANCHE_H
+#define __BLANCHE_H
+
+#undef DEBUG
+#define CONFIG_R8A7792
+#define CONFIG_RMOBILE_BOARD_STRING "Blanche"
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE817FFFC
+#define STACK_AREA_SIZE			0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+
+#define CONFIG_SYS_MEMTEST_START	(RCAR_GEN2_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
+
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+/* #define CONFIG_SYS_NO_FLASH */	/* uncomment if use QSPI-FLASH */
+#if defined(CONFIG_SYS_NO_FLASH)
+#define CONFIG_SYS_TEXT_BASE	0x40000000
+#define CONFIG_SPI
+#define CONFIG_SH_QSPI
+#define CONFIG_SH_QSPI_BASE	0xE6B10000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+#define CONFIG_CMD_FLASH
+#undef  CONFIG_CMD_SF
+#undef  CONFIG_CMD_SPI
+#endif
+
+/* BLANCHE on board LANC: SMC89218 (ExCS0) */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X                  1
+#define CONFIG_SMC911X_16_BIT           1
+#define CONFIG_SMC911X_BASE             0x18000000
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+/* ENV setting */
+#if defined(CONFIG_SYS_NO_FLASH)
+#else
+#undef  CONFIG_ENV_IS_IN_SPI_FLASH
+#undef  CONFIG_ENV_ADDR
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+#endif
+
+/* USB */
+#undef CONFIG_CMD_USB
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA	0x00400000
+/* SDHI0 */
+#define CONFIG_SMSTP3_ENA	0x00004000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA	0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA	0x00200000
+/* QSPI */
+#define CONFIG_SMSTP9_ENA	0x00020000
+/* SYS-DMAC0 */
+#define CONFIG_RMSTP2_ENA	0x00080000
+
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ	97500000
+
+#endif	/* __BLANCHE_H */