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| author | Gabriel Huau <contact@huau-gabriel.fr> | 2015-04-25 13:16:03 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-04-29 18:51:49 -0600 |
| commit | 4a34e4b86f75547ff2a546f02196cdfb9439eca4 (patch) | |
| tree | 96fec4f379ef415af395390965b7b9384c7e218c | |
| parent | 685224815bee3a79472ab1a8f345c04d7ea2804b (diff) | |
| download | u-boot-imx-4a34e4b86f75547ff2a546f02196cdfb9439eca4.zip u-boot-imx-4a34e4b86f75547ff2a546f02196cdfb9439eca4.tar.gz u-boot-imx-4a34e4b86f75547ff2a546f02196cdfb9439eca4.tar.bz2 | |
x86: baytrail: fix the GPIOBASE address
The correct GPIOBASE address on the baytrail is 0x48
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/x86/include/asm/arch-baytrail/gpio.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/arch-baytrail/gpio.h b/arch/x86/include/asm/arch-baytrail/gpio.h index ab4e059..4e8987c 100644 --- a/arch/x86/include/asm/arch-baytrail/gpio.h +++ b/arch/x86/include/asm/arch-baytrail/gpio.h @@ -8,6 +8,6 @@ #define _X86_ARCH_GPIO_H_ /* Where in config space is the register that points to the GPIO registers? */ -#define PCI_CFG_GPIOBASE 0x44 +#define PCI_CFG_GPIOBASE 0x48 #endif /* _X86_ARCH_GPIO_H_ */ |