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| author | Marek Vasut <marex@denx.de> | 2014-09-15 01:29:08 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2014-10-06 17:46:50 +0200 |
| commit | 40e7bcdee72830fa51d9e98428f1a61f9126527e (patch) | |
| tree | b2cd09665f2813bd3f5de81840c9979f85f77347 | |
| parent | 9ca2116ce49449602eb9e2f8a0cafe811bcc3086 (diff) | |
| download | u-boot-imx-40e7bcdee72830fa51d9e98428f1a61f9126527e.zip u-boot-imx-40e7bcdee72830fa51d9e98428f1a61f9126527e.tar.gz u-boot-imx-40e7bcdee72830fa51d9e98428f1a61f9126527e.tar.bz2 | |
arm: socfpga: cache: Enable D-Cache
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
| -rw-r--r-- | board/altera/socfpga/socfpga_cyclone5.c | 1 | ||||
| -rw-r--r-- | include/configs/socfpga_cyclone5.h | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 4149842..6b98277 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -35,6 +35,7 @@ int board_early_init_f(void) int board_init(void) { icache_enable(); + dcache_enable(); /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 76979b1..de60bb2 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -18,7 +18,6 @@ #undef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 -#define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ #define CONFIG_MISC_INIT_R @@ -26,6 +25,7 @@ #define CONFIG_SOCFPGA #define CONFIG_CLOCKS +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 /* base address for .text section */ |